machdep.c revision 1.1.2.15
1 /* $NetBSD: machdep.c,v 1.1.2.15 2010/01/20 09:04:33 matt Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74 /* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114 #include <sys/cdefs.h> 115 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.1.2.15 2010/01/20 09:04:33 matt Exp $"); 116 117 #include "opt_ddb.h" 118 #include "opt_com.h" 119 #include "opt_execfmt.h" 120 #include "opt_memsize.h" 121 122 #include <sys/param.h> 123 #include <sys/systm.h> 124 #include <sys/kernel.h> 125 #include <sys/buf.h> 126 #include <sys/reboot.h> 127 #include <sys/user.h> 128 #include <sys/mount.h> 129 #include <sys/kcore.h> 130 #include <sys/boot_flag.h> 131 #include <sys/termios.h> 132 #include <sys/ksyms.h> 133 #include <sys/bus.h> 134 #include <sys/device.h> 135 #include <sys/extent.h> 136 #include <sys/malloc.h> 137 138 #include <uvm/uvm_extern.h> 139 140 #include <dev/cons.h> 141 142 #include "ksyms.h" 143 144 #if NKSYMS || defined(DDB) || defined(LKM) 145 #include <machine/db_machdep.h> 146 #include <ddb/db_extern.h> 147 #endif 148 149 #include <machine/cpu.h> 150 #include <machine/psl.h> 151 152 #include "com.h" 153 #if NCOM == 0 154 #error no serial console 155 #endif 156 157 #include <dev/ic/comreg.h> 158 #include <dev/ic/comvar.h> 159 160 #include <mips/rmi/rmixl_comvar.h> 161 #include <mips/rmi/rmixlvar.h> 162 #include <mips/rmi/rmixl_firmware.h> 163 #include <mips/rmi/rmixlreg.h> 164 165 #ifdef MACHDEP_DEBUG 166 int machdep_debug=MACHDEP_DEBUG; 167 # define DPRINTF(x) do { if (machdep_debug) printf x ; } while(0) 168 #else 169 # define DPRINTF(x) 170 #endif 171 172 #ifndef CONSFREQ 173 # define CONSFREQ 66000000 174 #endif 175 #ifndef CONSPEED 176 # define CONSPEED 38400 177 #endif 178 #ifndef CONMODE 179 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 180 #endif 181 #ifndef CONSADDR 182 # define CONSADDR RMIXL_IO_DEV_UART_1 183 #endif 184 185 int comcnfreq = CONSFREQ; 186 int comcnspeed = CONSPEED; 187 tcflag_t comcnmode = CONMODE; 188 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 189 190 struct rmixl_config rmixl_configuration; 191 192 193 /* 194 * array of tested firmware versions 195 * if you find new ones and they work 196 * please add them 197 */ 198 static uint64_t rmiclfw_psb_versions[] = { 199 0x4958d4fb00000056ULL, 200 0x49a5a8fa00000056ULL, 201 0x4aacdb6a00000056ULL, 202 }; 203 #define RMICLFW_PSB_VERSIONS_LEN \ 204 (sizeof(rmiclfw_psb_versions)/sizeof(rmiclfw_psb_versions[0])) 205 206 /* 207 * kernel copies of firmware info 208 */ 209 static rmixlfw_info_t rmixlfw_info; 210 static rmixlfw_mmap_t rmixlfw_phys_mmap; 211 static rmixlfw_mmap_t rmixlfw_avail_mmap; 212 #define RMIXLFW_INFOP_LEGAL 0x8c000000 213 214 215 /* 216 * storage for fixed extent used to allocate physical address regions 217 * because extent(9) start and end values are u_long, they are only 218 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 219 * address is 40 bits wide. So the "physaddr" map stores regions 220 * in units of megabytes. 221 */ 222 static u_long rmixl_physaddr_storage[ 223 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 224 ]; 225 226 /* For sysctl_hw. */ 227 extern char cpu_model[]; 228 229 /* Our exported CPU info; we can have only one. */ 230 struct cpu_info cpu_info_store; 231 232 /* Maps for VM objects. */ 233 struct vm_map *mb_map = NULL; 234 struct vm_map *phys_map = NULL; 235 236 int physmem; /* Total physical memory */ 237 238 int netboot; /* Are we netbooting? */ 239 240 241 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 242 u_int mem_cluster_cnt; 243 244 245 void configure(void); 246 void mach_init(int, int32_t *, void *, int64_t); 247 static u_long rmixlfw_init(int64_t); 248 static u_long mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 249 static void __attribute__((__noreturn__)) rmixl_reset(void); 250 static void rmixl_physaddr_init(void); 251 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 252 void rmixlfw_mmap_print(rmixlfw_mmap_t *); 253 254 #ifdef MULTIPROCESSOR 255 void rmixl_get_wakeup_info(struct rmixl_config *); 256 #ifdef MACHDEP_DEBUG 257 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 258 #endif 259 #endif 260 261 262 /* 263 * safepri is a safe priority for sleep to set for a spin-wait during 264 * autoconfiguration or after a panic. Used as an argument to splx(). 265 */ 266 int safepri = MIPS1_PSL_LOWIPL; 267 268 /* 269 * Do all the stuff that locore normally does before calling main(). 270 */ 271 void 272 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 273 { 274 struct rmixl_config *rcp = &rmixl_configuration; 275 void *kernend; 276 u_long memsize; 277 u_int vm_cluster_cnt; 278 uint32_t r; 279 phys_ram_seg_t vm_clusters[VM_PHYSSEG_MAX]; 280 extern char edata[], end[]; 281 282 #ifndef MULTIPROCESSOR 283 rmixl_mtcr(0, 1); /* disable all threads except #0 */ 284 #endif 285 286 r = rmixl_mfcr(0x300); 287 r &= ~__BIT(14); /* disabled Unaligned Access */ 288 rmixl_mtcr(0x300, r); 289 290 rmixl_mtcr(0x400, 0); /* enable MMU clock gating */ 291 /* set single MMU Thread Mode */ 292 /* TLB is partitioned (1 partition) */ 293 294 /* 295 * Clear the BSS segment. 296 */ 297 kernend = (void *)mips_round_page(end); 298 memset(edata, 0, (char *)kernend - edata); 299 300 /* 301 * Set up the exception vectors and CPU-specific function 302 * vectors early on. We need the wbflush() vector set up 303 * before comcnattach() is called (or at least before the 304 * first printf() after that is called). 305 * Also clears the I+D caches. 306 */ 307 mips_vector_init(); 308 309 /* mips_vector_init initialized mips_options */ 310 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 311 312 /* get system info from firmware */ 313 memsize = rmixlfw_init(infop); 314 315 /* set the VM page size */ 316 uvm_setpagesize(); 317 318 physmem = btoc(memsize); 319 320 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 321 322 #if NCOM > 0 323 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 324 COM_TYPE_NORMAL, comcnmode); 325 #endif 326 327 printf("\nNetBSD/rmixl\n"); 328 printf("memsize = %#lx\n", memsize); 329 330 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 331 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 332 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 333 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 334 rcp->rc_cpu_wakeup_info, 335 rcp->rc_cpu_wakeup_end); 336 #endif 337 338 rmixl_physaddr_init(); 339 340 /* 341 * Obtain the cpu frequency 342 * Compute the number of ticks for hz. 343 * Compute the delay divisor. 344 * Double the Hz if this CPU runs at twice the 345 * external/cp0-count frequency 346 */ 347 curcpu()->ci_cpu_freq = rmixlfw_info.cpu_frequency; 348 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 349 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 350 curcpu()->ci_divisor_delay = 351 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 352 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 353 curcpu()->ci_cpu_freq *= 2; 354 355 /* 356 * Look at arguments passed to us and compute boothowto. 357 * - rmixl firmware gives us a 32 bit argv[i], so adapt 358 * by forcing sign extension in cast to (char *) 359 */ 360 boothowto = RB_AUTOBOOT; 361 for (int i = 1; i < argc; i++) { 362 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 363 int howto; 364 /* Ignore superfluous '-', if there is one */ 365 if (*cp == '-') 366 continue; 367 368 howto = 0; 369 BOOT_FLAG(*cp, howto); 370 if (howto != 0) 371 boothowto |= howto; 372 #ifdef DIAGNOSTIC 373 else 374 printf("bootflag '%c' not recognised\n", *cp); 375 #endif 376 } 377 } 378 #ifdef DIAGNOSTIC 379 printf("boothowto %#x\n", boothowto); 380 #endif 381 382 /* 383 * Reserve pages from the VM system. 384 * to maintain mem_clusters[] as a map of raw ram, 385 * copy into temporary table vm_clusters[] 386 * work on that and use it to feed vm_physload() 387 */ 388 KASSERT(sizeof(mem_clusters) == sizeof(vm_clusters)); 389 memcpy(&vm_clusters, &mem_clusters, sizeof(vm_clusters)); 390 vm_cluster_cnt = mem_cluster_cnt; 391 392 /* reserve 0..start..kernend pages */ 393 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 394 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 395 396 /* reserve reset exception vector page */ 397 /* should never be in our clusters anyway... */ 398 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 399 0x1FC00000, 0x1FC00000+NBPG); 400 401 #ifdef MULTIPROCEESOR 402 /* reserve the cpu_wakeup_info area */ 403 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 404 (u_quad_t)trunc_page(rcp->rc_cpu_wakeup_info), 405 (u_quad_t)round_page(rcp->rc_cpu_wakeup_end)); 406 #endif 407 408 #if 0 409 /* reserve everything > 4GB */ 410 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 411 0x100000000, (u_quad_t)~0); 412 #endif 413 414 /* 415 * Load vm_clusters[] into the VM system. 416 */ 417 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 418 vm_clusters, vm_cluster_cnt, NULL, 0); 419 420 /* 421 * Initialize error message buffer (at end of core). 422 */ 423 mips_init_msgbuf(); 424 425 pmap_bootstrap(); 426 427 /* 428 * Allocate space for proc0's USPACE. 429 */ 430 mips_init_lwp0_uarea(); 431 432 /* 433 * Initialize debuggers, and break into them, if appropriate. 434 */ 435 #if NKSYMS || defined(DDB) || defined(LKM) 436 ksyms_init(0, 0, 0); 437 #endif 438 439 #if defined(DDB) 440 if (boothowto & RB_KDB) 441 Debugger(); 442 #endif 443 } 444 445 /* 446 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 447 * 448 * we simply build a new table of segs, then copy it back over the given one 449 * this is inefficient but simple and called only a few times 450 * 451 * note: 'last' here means 1st addr past the end of the segment (start+size) 452 */ 453 static u_int 454 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 455 u_quad_t resv_first, u_quad_t resv_last) 456 { 457 u_quad_t first, last; 458 int new_nsegs=0; 459 int resv_flag; 460 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 461 462 for (u_int i=0; i < nsegs; i++) { 463 resv_flag = 0; 464 first = trunc_page(segs[i].start); 465 last = round_page(segs[i].start + segs[i].size); 466 467 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 468 if ((resv_first <= first) && (resv_last >= last)) { 469 /* whole segment is resverved */ 470 continue; 471 } 472 if ((resv_first > first) && (resv_first < last)) { 473 u_quad_t new_last; 474 475 /* 476 * reserved start in segment 477 * salvage the leading fragment 478 */ 479 resv_flag = 1; 480 new_last = last - (last - resv_first); 481 KASSERT (new_last > first); 482 new_segs[new_nsegs].start = first; 483 new_segs[new_nsegs].size = new_last - first; 484 new_nsegs++; 485 } 486 if ((resv_last > first) && (resv_last < last)) { 487 u_quad_t new_first; 488 489 /* 490 * reserved end in segment 491 * salvage the trailing fragment 492 */ 493 resv_flag = 1; 494 new_first = first + (resv_last - first); 495 KASSERT (last > (new_first + NBPG)); 496 new_segs[new_nsegs].start = new_first; 497 new_segs[new_nsegs].size = last - new_first; 498 new_nsegs++; 499 } 500 if (resv_flag == 0) { 501 /* 502 * nothing reserved here, take it all 503 */ 504 new_segs[new_nsegs].start = first; 505 new_segs[new_nsegs].size = last - first; 506 new_nsegs++; 507 } 508 509 } 510 511 memcpy(segs, new_segs, sizeof(new_segs)); 512 513 return new_nsegs; 514 } 515 516 /* 517 * create an extent for physical address space 518 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 519 * allocate the regions where we have known functions (DRAM, IO, etc) 520 * what remains can be allocated as needed for other stuff 521 * e.g. to configure BARs that are not already initialized and enabled. 522 */ 523 static void 524 rmixl_physaddr_init(void) 525 { 526 struct extent *ext; 527 unsigned long start = 0UL; 528 unsigned long end = (__BIT(40) / (1024 * 1024)) -1; 529 u_long base; 530 u_long size; 531 uint32_t r; 532 533 ext = extent_create("physaddr", start, end, M_DEVBUF, 534 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 535 EX_NOWAIT | EX_NOCOALESCE); 536 537 if (ext == NULL) 538 panic("%s: extent_create failed", __func__); 539 540 /* 541 * grab regions per DRAM BARs 542 */ 543 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 544 r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 545 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 546 continue; /* not enabled */ 547 base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024)); 548 size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024)); 549 550 DPRINTF(("%s: %d: %d: 0x%08x -- 0x%010lx:%lu MB\n", 551 __func__, __LINE__, i, r, base * (1024 * 1024), size)); 552 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 553 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 554 "failed", __func__, ext, base, size, EX_NOWAIT); 555 } 556 557 /* 558 * grab regions per PCIe CFG, ECFG, IO, MEM BARs 559 */ 560 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_CFG_BAR); 561 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 562 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 563 / (1024 * 1024)); 564 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 565 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 566 __LINE__, "CFG", r, base * 1024 * 1024, size)); 567 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 568 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 569 "failed", __func__, ext, base, size, EX_NOWAIT); 570 } 571 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_ECFG_BAR); 572 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 573 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 574 / (1024 * 1024)); 575 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 576 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 577 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 578 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 579 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 580 "failed", __func__, ext, base, size, EX_NOWAIT); 581 } 582 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_MEM_BAR); 583 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 584 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 585 / (1024 * 1024)); 586 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 587 / (1024 * 1024)); 588 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 589 __LINE__, "MEM", r, base * 1024 * 1024, size)); 590 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 591 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 592 "failed", __func__, ext, base, size, EX_NOWAIT); 593 } 594 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_IO_BAR); 595 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 596 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 597 / (1024 * 1024)); 598 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 599 / (1024 * 1024)); 600 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 601 __LINE__, "IO", r, base * 1024 * 1024, size)); 602 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 603 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 604 "failed", __func__, ext, base, size, EX_NOWAIT); 605 } 606 607 /* 608 * at this point all regions left in "physaddr" extent 609 * are unused holes in the physical adress space 610 * available for use as needed. 611 */ 612 rmixl_configuration.rc_phys_ex = ext; 613 #ifdef MACHDEP_DEBUG 614 extent_print(ext); 615 #endif 616 } 617 618 static u_long 619 rmixlfw_init(int64_t infop) 620 { 621 struct rmixl_config *rcp = &rmixl_configuration; 622 623 #ifdef MULTIPROCESSOR 624 rmixl_get_wakeup_info(rcp); 625 #endif 626 627 infop |= MIPS_KSEG0_START; 628 rmixlfw_info = *(rmixlfw_info_t *)(intptr_t)infop; 629 630 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 631 if (rmiclfw_psb_versions[i] == rmixlfw_info.psb_version) 632 goto found; 633 } 634 635 rcp->rc_io_pbase = RMIXL_IO_DEV_PBASE; 636 rmixl_putchar_init(rcp->rc_io_pbase); 637 638 #ifdef DIAGNOSTIC 639 rmixl_puts("\r\nWARNING: untested psb_version: "); 640 rmixl_puthex64(rmixlfw_info.psb_version); 641 rmixl_puts("\r\n"); 642 #endif 643 644 #ifdef MEMSIZE 645 /* XXX trust and use MEMSIZE */ 646 mem_clusters[0].start = 0; 647 mem_clusters[0].size = MEMSIZE; 648 mem_cluster_cnt = 1; 649 return MEMSIZE; 650 #else 651 rmixl_puts("\r\nERROR: configure MEMSIZE\r\n"); 652 cpu_reboot(RB_HALT, NULL); 653 /* NOTREACHED */ 654 #endif 655 656 found: 657 rcp->rc_io_pbase = MIPS_KSEG1_TO_PHYS(rmixlfw_info.io_base); 658 rmixl_putchar_init(rcp->rc_io_pbase); 659 #ifdef MACHDEP_DEBUG 660 rmixl_puts("\r\ninfop: "); 661 rmixl_puthex64((uint64_t)(intptr_t)infop); 662 #endif 663 #ifdef DIAGNOSTIC 664 rmixl_puts("\r\nrecognized psb_version: "); 665 rmixl_puthex64(rmixlfw_info.psb_version); 666 rmixl_puts("\r\n"); 667 #endif 668 669 return mem_clusters_init( 670 (rmixlfw_mmap_t *)(intptr_t)rmixlfw_info.psb_physaddr_map, 671 (rmixlfw_mmap_t *)(intptr_t)rmixlfw_info.avail_mem_map); 672 } 673 674 void 675 rmixlfw_mmap_print(rmixlfw_mmap_t *map) 676 { 677 #ifdef MACHDEP_DEBUG 678 for (uint32_t i=0; i < map->nmmaps; i++) { 679 rmixl_puthex32(i); 680 rmixl_puts(", "); 681 rmixl_puthex64(map->entry[i].start); 682 rmixl_puts(", "); 683 rmixl_puthex64(map->entry[i].size); 684 rmixl_puts(", "); 685 rmixl_puthex32(map->entry[i].type); 686 rmixl_puts("\r\n"); 687 } 688 #endif 689 } 690 691 /* 692 * mem_clusters_init 693 * 694 * initialize mem_clusters[] table based on memory address mapping 695 * provided by boot firmware. 696 * 697 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 698 * these will be limited by MEMSIZE if it is configured. 699 * if neither are available, just use MEMSIZE. 700 */ 701 static u_long 702 mem_clusters_init( 703 rmixlfw_mmap_t *psb_physaddr_map, 704 rmixlfw_mmap_t *avail_mem_map) 705 { 706 rmixlfw_mmap_t *map = NULL; 707 const char *mapname; 708 uint64_t sz; 709 uint64_t sum; 710 u_int cnt; 711 #ifdef MEMSIZE 712 u_long memsize = MEMSIZE; 713 #endif 714 715 #ifdef MACHDEP_DEBUG 716 rmixl_puts("psb_physaddr_map: "); 717 rmixl_puthex64((uint64_t)(intptr_t)psb_physaddr_map); 718 rmixl_puts("\r\n"); 719 #endif 720 if (psb_physaddr_map != NULL) { 721 rmixlfw_phys_mmap = *psb_physaddr_map; 722 map = &rmixlfw_phys_mmap; 723 mapname = "psb_physaddr_map"; 724 rmixlfw_mmap_print(map); 725 } 726 #ifdef DIAGNOSTIC 727 else { 728 rmixl_puts("WARNING: no psb_physaddr_map\r\n"); 729 } 730 #endif 731 732 #ifdef MACHDEP_DEBUG 733 rmixl_puts("avail_mem_map: "); 734 rmixl_puthex64((uint64_t)(intptr_t)avail_mem_map); 735 rmixl_puts("\r\n"); 736 #endif 737 if (avail_mem_map != NULL) { 738 rmixlfw_avail_mmap = *avail_mem_map; 739 map = &rmixlfw_avail_mmap; 740 mapname = "avail_mem_map"; 741 rmixlfw_mmap_print(map); 742 } 743 #ifdef DIAGNOSTIC 744 else { 745 rmixl_puts("WARNING: no avail_mem_map\r\n"); 746 } 747 #endif 748 749 if (map == NULL) { 750 #ifndef MEMSIZE 751 rmixl_puts("panic: no firmware memory map, " 752 "must configure MEMSIZE\r\n"); 753 for(;;); /* XXX */ 754 #else 755 #ifdef DIAGNOSTIC 756 rmixl_puts("WARNING: no avail_mem_map, " 757 "using MEMSIZE\r\n"); 758 #endif 759 760 mem_clusters[0].start = 0; 761 mem_clusters[0].size = MEMSIZE; 762 mem_cluster_cnt = 1; 763 return MEMSIZE; 764 #endif /* MEMSIZE */ 765 } 766 767 #ifdef DIAGNOSTIC 768 rmixl_puts("using "); 769 rmixl_puts(mapname); 770 rmixl_puts("\r\n"); 771 #endif 772 #ifdef MACHDEP_DEBUG 773 rmixl_puts("memory clusters:\r\n"); 774 #endif 775 sum = 0; 776 cnt = 0; 777 for (uint32_t i=0; i < map->nmmaps; i++) { 778 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 779 continue; 780 mem_clusters[cnt].start = map->entry[i].start; 781 sz = map->entry[i].size; 782 sum += sz; 783 mem_clusters[cnt].size = sz; 784 #ifdef MACHDEP_DEBUG 785 rmixl_puthex32(i); 786 rmixl_puts(": "); 787 rmixl_puthex64(mem_clusters[cnt].start); 788 rmixl_puts(", "); 789 rmixl_puthex64(sz); 790 rmixl_puts(": "); 791 rmixl_puthex64(sum); 792 rmixl_puts("\r\n"); 793 #endif 794 #ifdef MEMSIZE 795 /* 796 * configurably limit memsize 797 */ 798 if (sum == memsize) 799 break; 800 if (sum > memsize) { 801 uint64_t tmp; 802 803 tmp = sum - memsize; 804 sz -= tmp; 805 sum -= tmp; 806 mem_clusters[cnt].size = sz; 807 cnt++; 808 break; 809 } 810 #endif 811 cnt++; 812 } 813 mem_cluster_cnt = cnt; 814 return sum; 815 } 816 817 #ifdef MULTIPROCESSOR 818 /* 819 * firmware passes wakeup info structure in CP0 OS Scratch reg #7 820 * they do not explicitly give us the size of the wakeup area. 821 * we "know" that firmware loader sets wip->gp thusly: 822 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 823 * so 824 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 825 * Only the "master" cpu runs this function, so 826 * vcpu = wip->master_cpu 827 */ 828 void 829 rmixl_get_wakeup_info(struct rmixl_config *rcp) 830 { 831 volatile rmixlfw_cpu_wakeup_info_t *wip; 832 int32_t scratch_7; 833 intptr_t end; 834 835 __asm__ volatile( 836 ".set push" "\n" 837 ".set noreorder" "\n" 838 ".set mips64" "\n" 839 "dmfc0 %0, $22, 7" "\n" 840 ".set pop" "\n" 841 : "=r"(scratch_7)); 842 843 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 844 (intptr_t)scratch_7; 845 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 846 847 if (wip->valid == 1) { 848 rcp->rc_cpu_wakeup_end = (const void *)end; 849 rcp->rc_cpu_wakeup_info = wip; 850 } 851 }; 852 853 #ifdef MACHDEP_DEBUG 854 static void 855 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 856 { 857 int i; 858 859 printf("%s: wip %p\n", __func__, wip); 860 861 printf("cpu_status %#x\n", wip->cpu_status); 862 printf("valid: %d\n", wip->valid); 863 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 864 wip->entry.addr, 865 wip->entry.args, 866 wip->entry.sp, 867 wip->entry.gp); 868 printf("master_cpu %d\n", wip->master_cpu); 869 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 870 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 871 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 872 printf("argc %d\n", wip->argc); 873 printf("argv:"); 874 for (i=0; i < wip->argc; i++) 875 printf(" %#x", wip->argv[i]); 876 printf("\n"); 877 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 878 printf("tlb_map:\n"); 879 for (i=0; i < wip->valid_tlb_entries; i++) { 880 volatile const struct lib_cpu_tlb_mapping *m = 881 &wip->tlb_map[i]; 882 printf(" %d", m->page_size); 883 printf(", %d", m->asid); 884 printf(", %d", m->coherency); 885 printf(", %d", m->coherency); 886 printf(", %d", m->attr); 887 printf(", %#x", m->virt); 888 printf(", %#"PRIx64"\n", m->phys); 889 } 890 printf("elf segs:\n"); 891 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 892 volatile const struct core_segment_info *e = 893 &wip->seg_info[i]; 894 printf(" %#"PRIx64"", e->vaddr); 895 printf(", %#"PRIx64"", e->memsz); 896 printf(", %#x\n", e->flags); 897 } 898 printf("envc %d\n", wip->envc); 899 for (i=0; i < wip->envc; i++) 900 printf(" %#x \"%s\"", wip->envs[i], 901 (char *)(intptr_t)(int32_t)(wip->envs[i])); 902 printf("\n"); 903 printf("app_mode %d\n", wip->app_mode); 904 printf("printk_lock %#x\n", wip->printk_lock); 905 printf("kseg_master %d\n", wip->kseg_master); 906 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 907 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 908 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 909 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 910 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 911 printf("loader_lock %#x\n", wip->loader_lock); 912 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 913 printf("unused_0 %#x\n", wip->unused_0); 914 } 915 #endif /* MACHDEP_DEBUG */ 916 #endif /* MULTIPROCESSOR */ 917 918 void 919 consinit(void) 920 { 921 922 /* 923 * Everything related to console initialization is done 924 * in mach_init(). 925 */ 926 } 927 928 /* 929 * Allocate memory for variable-sized tables, 930 */ 931 void 932 cpu_startup() 933 { 934 vaddr_t minaddr, maxaddr; 935 char pbuf[9]; 936 937 /* 938 * Good {morning,afternoon,evening,night}. 939 */ 940 printf("%s%s", copyright, version); 941 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 942 printf("total memory = %s\n", pbuf); 943 944 /* 945 * Virtual memory is bootstrapped -- notify the bus spaces 946 * that memory allocation is now safe. 947 */ 948 rmixl_configuration.rc_mallocsafe = 1; 949 950 minaddr = 0; 951 /* 952 * Allocate a submap for physio. 953 */ 954 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 955 VM_PHYS_SIZE, 0, FALSE, NULL); 956 957 /* 958 * (No need to allocate an mbuf cluster submap. Mbuf clusters 959 * are allocated via the pool allocator, and we use XKSEG to 960 * map those pages.) 961 */ 962 963 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 964 printf("avail memory = %s\n", pbuf); 965 } 966 967 int waittime = -1; 968 969 void 970 cpu_reboot(howto, bootstr) 971 int howto; 972 char *bootstr; 973 { 974 975 /* Take a snapshot before clobbering any registers. */ 976 if (curproc) 977 savectx((struct user *)curpcb); 978 979 if (cold) { 980 howto |= RB_HALT; 981 goto haltsys; 982 } 983 984 /* If "always halt" was specified as a boot flag, obey. */ 985 if (boothowto & RB_HALT) 986 howto |= RB_HALT; 987 988 boothowto = howto; 989 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 990 waittime = 0; 991 vfs_shutdown(); 992 993 /* 994 * If we've been adjusting the clock, the todr 995 * will be out of synch; adjust it now. 996 */ 997 resettodr(); 998 } 999 1000 splhigh(); 1001 1002 if (howto & RB_DUMP) 1003 dumpsys(); 1004 1005 haltsys: 1006 doshutdownhooks(); 1007 1008 if (howto & RB_HALT) { 1009 printf("\n"); 1010 printf("The operating system has halted.\n"); 1011 printf("Please press any key to reboot.\n\n"); 1012 cnpollc(1); /* For proper keyboard command handling */ 1013 cngetc(); 1014 cnpollc(0); 1015 } 1016 1017 printf("rebooting...\n\n"); 1018 1019 rmixl_reset(); 1020 } 1021 1022 /* 1023 * goodbye world 1024 */ 1025 void __attribute__((__noreturn__)) 1026 rmixl_reset(void) 1027 { 1028 uint32_t r; 1029 1030 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1031 r |= RMIXL_GPIO_RESET_RESET; 1032 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1033 1034 printf("soft reset failed, spinning...\n"); 1035 for (;;); 1036 } 1037
Indexes created Fri Oct 31 11:10:07 GMT 2025