machdep.c revision 1.1.2.17
1 /* $NetBSD: machdep.c,v 1.1.2.17 2010/01/24 05:34:20 cliff Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74 /* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114 #include <sys/cdefs.h> 115 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.1.2.17 2010/01/24 05:34:20 cliff Exp $"); 116 117 #include "opt_ddb.h" 118 #include "opt_com.h" 119 #include "opt_execfmt.h" 120 #include "opt_memsize.h" 121 122 #include <sys/param.h> 123 #include <sys/systm.h> 124 #include <sys/kernel.h> 125 #include <sys/buf.h> 126 #include <sys/reboot.h> 127 #include <sys/user.h> 128 #include <sys/mount.h> 129 #include <sys/kcore.h> 130 #include <sys/boot_flag.h> 131 #include <sys/termios.h> 132 #include <sys/ksyms.h> 133 #include <sys/bus.h> 134 #include <sys/device.h> 135 #include <sys/extent.h> 136 #include <sys/malloc.h> 137 138 #include <uvm/uvm_extern.h> 139 140 #include <dev/cons.h> 141 142 #include "ksyms.h" 143 144 #if NKSYMS || defined(DDB) || defined(LKM) 145 #include <machine/db_machdep.h> 146 #include <ddb/db_extern.h> 147 #endif 148 149 #include <machine/cpu.h> 150 #include <machine/psl.h> 151 152 #include "com.h" 153 #if NCOM == 0 154 #error no serial console 155 #endif 156 157 #include <dev/ic/comreg.h> 158 #include <dev/ic/comvar.h> 159 160 #include <mips/rmi/rmixl_comvar.h> 161 #include <mips/rmi/rmixlvar.h> 162 #include <mips/rmi/rmixl_firmware.h> 163 #include <mips/rmi/rmixlreg.h> 164 165 #ifdef MACHDEP_DEBUG 166 int machdep_debug=MACHDEP_DEBUG; 167 # define DPRINTF(x) do { if (machdep_debug) printf x ; } while(0) 168 #else 169 # define DPRINTF(x) 170 #endif 171 172 #ifndef CONSFREQ 173 # define CONSFREQ 66000000 174 #endif 175 #ifndef CONSPEED 176 # define CONSPEED 38400 177 #endif 178 #ifndef CONMODE 179 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 180 #endif 181 #ifndef CONSADDR 182 # define CONSADDR RMIXL_IO_DEV_UART_1 183 #endif 184 185 int comcnfreq = CONSFREQ; 186 int comcnspeed = CONSPEED; 187 tcflag_t comcnmode = CONMODE; 188 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 189 190 struct rmixl_config rmixl_configuration; 191 192 193 /* 194 * array of tested firmware versions 195 * if you find new ones and they work 196 * please add them 197 */ 198 static uint64_t rmiclfw_psb_versions[] = { 199 0x4958d4fb00000056ULL, 200 0x49a5a8fa00000056ULL, 201 0x4aacdb6a00000056ULL, 202 }; 203 #define RMICLFW_PSB_VERSIONS_LEN \ 204 (sizeof(rmiclfw_psb_versions)/sizeof(rmiclfw_psb_versions[0])) 205 206 /* 207 * storage for fixed extent used to allocate physical address regions 208 * because extent(9) start and end values are u_long, they are only 209 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 210 * address is 40 bits wide. So the "physaddr" map stores regions 211 * in units of megabytes. 212 */ 213 static u_long rmixl_physaddr_storage[ 214 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 215 ]; 216 217 /* For sysctl_hw. */ 218 extern char cpu_model[]; 219 220 /* Our exported CPU info; we can have only one. */ 221 struct cpu_info cpu_info_store; 222 223 /* Maps for VM objects. */ 224 struct vm_map *mb_map = NULL; 225 struct vm_map *phys_map = NULL; 226 227 int physmem; /* Total physical memory */ 228 229 int netboot; /* Are we netbooting? */ 230 231 232 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 233 u_int mem_cluster_cnt; 234 235 236 void configure(void); 237 void mach_init(int, int32_t *, void *, int64_t); 238 static uint64_t rmixlfw_init(int64_t); 239 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 240 static void __attribute__((__noreturn__)) rmixl_reset(void); 241 static void rmixl_physaddr_init(void); 242 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 243 void rmixlfw_mmap_print(rmixlfw_mmap_t *); 244 245 246 #ifdef MULTIPROCESSOR 247 void rmixl_get_wakeup_info(struct rmixl_config *); 248 #ifdef MACHDEP_DEBUG 249 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 250 #endif 251 #endif 252 253 254 /* 255 * safepri is a safe priority for sleep to set for a spin-wait during 256 * autoconfiguration or after a panic. Used as an argument to splx(). 257 */ 258 int safepri = MIPS1_PSL_LOWIPL; 259 260 /* 261 * Do all the stuff that locore normally does before calling main(). 262 */ 263 void 264 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 265 { 266 struct rmixl_config *rcp = &rmixl_configuration; 267 void *kernend; 268 uint64_t memsize; 269 u_int vm_cluster_cnt; 270 uint32_t r; 271 phys_ram_seg_t vm_clusters[VM_PHYSSEG_MAX]; 272 extern char edata[], end[]; 273 274 #ifndef MULTIPROCESSOR 275 rmixl_mtcr(0, 1); /* disable all threads except #0 */ 276 rmixl_mtcr(0x400, 0); /* enable MMU clock gating */ 277 /* set single MMU Thread Mode */ 278 /* TLB is partitioned (1 partition) */ 279 #endif 280 281 r = rmixl_mfcr(0x300); 282 r &= ~__BIT(14); /* disabled Unaligned Access */ 283 rmixl_mtcr(0x300, r); 284 285 /* 286 * Clear the BSS segment. 287 */ 288 kernend = (void *)mips_round_page(end); 289 memset(edata, 0, (char *)kernend - edata); 290 291 /* 292 * Set up the exception vectors and CPU-specific function 293 * vectors early on. We need the wbflush() vector set up 294 * before comcnattach() is called (or at least before the 295 * first printf() after that is called). 296 * Also clears the I+D caches. 297 */ 298 mips_vector_init(); 299 300 /* mips_vector_init initialized mips_options */ 301 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 302 303 /* get system info from firmware */ 304 memsize = rmixlfw_init(infop); 305 306 /* set the VM page size */ 307 uvm_setpagesize(); 308 309 physmem = btoc(memsize); 310 311 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 312 313 #if NCOM > 0 314 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 315 COM_TYPE_NORMAL, comcnmode); 316 #endif 317 318 printf("\nNetBSD/rmixl\n"); 319 printf("memsize = %#"PRIx64"\n", memsize); 320 321 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 322 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 323 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 324 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 325 rcp->rc_cpu_wakeup_info, 326 rcp->rc_cpu_wakeup_end); 327 printf("userapp_cpu_map: %#"PRIx64"\n", rcp->rc_psb_info.userapp_cpu_map); 328 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 329 { 330 register_t sp; 331 asm volatile ("move %0, $sp\n" : "=r"(sp)); 332 printf("sp: %#"PRIx64"\n", sp); 333 } 334 #endif 335 336 rmixl_physaddr_init(); 337 338 /* 339 * Obtain the cpu frequency 340 * Compute the number of ticks for hz. 341 * Compute the delay divisor. 342 * Double the Hz if this CPU runs at twice the 343 * external/cp0-count frequency 344 */ 345 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 346 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 347 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 348 curcpu()->ci_divisor_delay = 349 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 350 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 351 curcpu()->ci_cpu_freq *= 2; 352 353 /* 354 * Look at arguments passed to us and compute boothowto. 355 * - rmixl firmware gives us a 32 bit argv[i], so adapt 356 * by forcing sign extension in cast to (char *) 357 */ 358 boothowto = RB_AUTOBOOT; 359 for (int i = 1; i < argc; i++) { 360 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 361 int howto; 362 /* Ignore superfluous '-', if there is one */ 363 if (*cp == '-') 364 continue; 365 366 howto = 0; 367 BOOT_FLAG(*cp, howto); 368 if (howto != 0) 369 boothowto |= howto; 370 #ifdef DIAGNOSTIC 371 else 372 printf("bootflag '%c' not recognised\n", *cp); 373 #endif 374 } 375 } 376 #ifdef DIAGNOSTIC 377 printf("boothowto %#x\n", boothowto); 378 #endif 379 380 /* 381 * Reserve pages from the VM system. 382 * to maintain mem_clusters[] as a map of raw ram, 383 * copy into temporary table vm_clusters[] 384 * work on that and use it to feed vm_physload() 385 */ 386 KASSERT(sizeof(mem_clusters) == sizeof(vm_clusters)); 387 memcpy(&vm_clusters, &mem_clusters, sizeof(vm_clusters)); 388 vm_cluster_cnt = mem_cluster_cnt; 389 390 /* reserve 0..start..kernend pages */ 391 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 392 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 393 394 /* reserve reset exception vector page */ 395 /* should never be in our clusters anyway... */ 396 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 397 0x1FC00000, 0x1FC00000+NBPG); 398 399 #ifdef MULTIPROCEESOR 400 /* reserve the cpu_wakeup_info area */ 401 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 402 (u_quad_t)trunc_page(rcp->rc_cpu_wakeup_info), 403 (u_quad_t)round_page(rcp->rc_cpu_wakeup_end)); 404 #endif 405 406 #if 0 407 /* reserve everything > 4GB */ 408 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 409 0x100000000, (u_quad_t)~0); 410 #endif 411 412 /* 413 * Load vm_clusters[] into the VM system. 414 */ 415 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 416 vm_clusters, vm_cluster_cnt, NULL, 0); 417 418 /* 419 * Initialize error message buffer (at end of core). 420 */ 421 mips_init_msgbuf(); 422 423 pmap_bootstrap(); 424 425 /* 426 * Allocate space for proc0's USPACE. 427 */ 428 mips_init_lwp0_uarea(); 429 430 /* 431 * Initialize debuggers, and break into them, if appropriate. 432 */ 433 #if NKSYMS || defined(DDB) || defined(LKM) 434 ksyms_init(0, 0, 0); 435 #endif 436 437 #if defined(DDB) 438 if (boothowto & RB_KDB) 439 Debugger(); 440 #endif 441 } 442 443 /* 444 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 445 * 446 * we simply build a new table of segs, then copy it back over the given one 447 * this is inefficient but simple and called only a few times 448 * 449 * note: 'last' here means 1st addr past the end of the segment (start+size) 450 */ 451 static u_int 452 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 453 u_quad_t resv_first, u_quad_t resv_last) 454 { 455 u_quad_t first, last; 456 int new_nsegs=0; 457 int resv_flag; 458 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 459 460 for (u_int i=0; i < nsegs; i++) { 461 resv_flag = 0; 462 first = trunc_page(segs[i].start); 463 last = round_page(segs[i].start + segs[i].size); 464 465 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 466 if ((resv_first <= first) && (resv_last >= last)) { 467 /* whole segment is resverved */ 468 continue; 469 } 470 if ((resv_first > first) && (resv_first < last)) { 471 u_quad_t new_last; 472 473 /* 474 * reserved start in segment 475 * salvage the leading fragment 476 */ 477 resv_flag = 1; 478 new_last = last - (last - resv_first); 479 KASSERT (new_last > first); 480 new_segs[new_nsegs].start = first; 481 new_segs[new_nsegs].size = new_last - first; 482 new_nsegs++; 483 } 484 if ((resv_last > first) && (resv_last < last)) { 485 u_quad_t new_first; 486 487 /* 488 * reserved end in segment 489 * salvage the trailing fragment 490 */ 491 resv_flag = 1; 492 new_first = first + (resv_last - first); 493 KASSERT (last > (new_first + NBPG)); 494 new_segs[new_nsegs].start = new_first; 495 new_segs[new_nsegs].size = last - new_first; 496 new_nsegs++; 497 } 498 if (resv_flag == 0) { 499 /* 500 * nothing reserved here, take it all 501 */ 502 new_segs[new_nsegs].start = first; 503 new_segs[new_nsegs].size = last - first; 504 new_nsegs++; 505 } 506 507 } 508 509 memcpy(segs, new_segs, sizeof(new_segs)); 510 511 return new_nsegs; 512 } 513 514 /* 515 * create an extent for physical address space 516 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 517 * allocate the regions where we have known functions (DRAM, IO, etc) 518 * what remains can be allocated as needed for other stuff 519 * e.g. to configure BARs that are not already initialized and enabled. 520 */ 521 static void 522 rmixl_physaddr_init(void) 523 { 524 struct extent *ext; 525 unsigned long start = 0UL; 526 unsigned long end = (__BIT(40) / (1024 * 1024)) -1; 527 u_long base; 528 u_long size; 529 uint32_t r; 530 531 ext = extent_create("physaddr", start, end, M_DEVBUF, 532 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 533 EX_NOWAIT | EX_NOCOALESCE); 534 535 if (ext == NULL) 536 panic("%s: extent_create failed", __func__); 537 538 /* 539 * grab regions per DRAM BARs 540 */ 541 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 542 r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 543 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 544 continue; /* not enabled */ 545 base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024)); 546 size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024)); 547 548 DPRINTF(("%s: %d: %d: 0x%08x -- 0x%010lx:%lu MB\n", 549 __func__, __LINE__, i, r, base * (1024 * 1024), size)); 550 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 551 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 552 "failed", __func__, ext, base, size, EX_NOWAIT); 553 } 554 555 /* 556 * grab regions per PCIe CFG, ECFG, IO, MEM BARs 557 */ 558 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_CFG_BAR); 559 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 560 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 561 / (1024 * 1024)); 562 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 563 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 564 __LINE__, "CFG", r, base * 1024 * 1024, size)); 565 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 566 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 567 "failed", __func__, ext, base, size, EX_NOWAIT); 568 } 569 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_ECFG_BAR); 570 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 571 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 572 / (1024 * 1024)); 573 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 574 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 575 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 576 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 577 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 578 "failed", __func__, ext, base, size, EX_NOWAIT); 579 } 580 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_MEM_BAR); 581 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 582 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 583 / (1024 * 1024)); 584 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 585 / (1024 * 1024)); 586 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 587 __LINE__, "MEM", r, base * 1024 * 1024, size)); 588 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 589 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 590 "failed", __func__, ext, base, size, EX_NOWAIT); 591 } 592 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_IO_BAR); 593 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 594 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 595 / (1024 * 1024)); 596 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 597 / (1024 * 1024)); 598 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 599 __LINE__, "IO", r, base * 1024 * 1024, size)); 600 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 601 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 602 "failed", __func__, ext, base, size, EX_NOWAIT); 603 } 604 605 /* 606 * at this point all regions left in "physaddr" extent 607 * are unused holes in the physical adress space 608 * available for use as needed. 609 */ 610 rmixl_configuration.rc_phys_ex = ext; 611 #ifdef MACHDEP_DEBUG 612 extent_print(ext); 613 #endif 614 } 615 616 static uint64_t 617 rmixlfw_init(int64_t infop) 618 { 619 struct rmixl_config *rcp = &rmixl_configuration; 620 621 #ifdef MULTIPROCESSOR 622 rmixl_get_wakeup_info(rcp); 623 #endif 624 625 infop |= MIPS_KSEG0_START; 626 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 627 628 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 629 if (rmiclfw_psb_versions[i] == rcp->rc_psb_info.psb_version) 630 goto found; 631 } 632 633 rcp->rc_io_pbase = RMIXL_IO_DEV_PBASE; 634 rmixl_putchar_init(rcp->rc_io_pbase); 635 636 #ifdef DIAGNOSTIC 637 rmixl_puts("\r\nWARNING: untested psb_version: "); 638 rmixl_puthex64(rcp->rc_psb_info.psb_version); 639 rmixl_puts("\r\n"); 640 #endif 641 642 #ifdef MEMSIZE 643 /* XXX trust and use MEMSIZE */ 644 mem_clusters[0].start = 0; 645 mem_clusters[0].size = MEMSIZE; 646 mem_cluster_cnt = 1; 647 return MEMSIZE; 648 #else 649 rmixl_puts("\r\nERROR: configure MEMSIZE\r\n"); 650 cpu_reboot(RB_HALT, NULL); 651 /* NOTREACHED */ 652 #endif 653 654 found: 655 rcp->rc_io_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 656 rmixl_putchar_init(rcp->rc_io_pbase); 657 #ifdef MACHDEP_DEBUG 658 rmixl_puts("\r\ninfop: "); 659 rmixl_puthex64((uint64_t)(intptr_t)infop); 660 #endif 661 #ifdef DIAGNOSTIC 662 rmixl_puts("\r\nrecognized psb_version: "); 663 rmixl_puthex64(rcp->rc_psb_info.psb_version); 664 rmixl_puts("\r\n"); 665 #endif 666 667 return mem_clusters_init( 668 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 669 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 670 } 671 672 void 673 rmixlfw_mmap_print(rmixlfw_mmap_t *map) 674 { 675 #ifdef MACHDEP_DEBUG 676 for (uint32_t i=0; i < map->nmmaps; i++) { 677 rmixl_puthex32(i); 678 rmixl_puts(", "); 679 rmixl_puthex64(map->entry[i].start); 680 rmixl_puts(", "); 681 rmixl_puthex64(map->entry[i].size); 682 rmixl_puts(", "); 683 rmixl_puthex32(map->entry[i].type); 684 rmixl_puts("\r\n"); 685 } 686 #endif 687 } 688 689 /* 690 * mem_clusters_init 691 * 692 * initialize mem_clusters[] table based on memory address mapping 693 * provided by boot firmware. 694 * 695 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 696 * these will be limited by MEMSIZE if it is configured. 697 * if neither are available, just use MEMSIZE. 698 */ 699 static uint64_t 700 mem_clusters_init( 701 rmixlfw_mmap_t *psb_physaddr_map, 702 rmixlfw_mmap_t *avail_mem_map) 703 { 704 rmixlfw_mmap_t *map = NULL; 705 const char *mapname; 706 uint64_t sz; 707 uint64_t sum; 708 u_int cnt; 709 #ifdef MEMSIZE 710 uint64_t memsize = MEMSIZE; 711 #endif 712 713 #ifdef MACHDEP_DEBUG 714 rmixl_puts("psb_physaddr_map: "); 715 rmixl_puthex64((uint64_t)(intptr_t)psb_physaddr_map); 716 rmixl_puts("\r\n"); 717 #endif 718 if (psb_physaddr_map != NULL) { 719 map = psb_physaddr_map; 720 mapname = "psb_physaddr_map"; 721 rmixlfw_mmap_print(map); 722 } 723 #ifdef DIAGNOSTIC 724 else { 725 rmixl_puts("WARNING: no psb_physaddr_map\r\n"); 726 } 727 #endif 728 729 #ifdef MACHDEP_DEBUG 730 rmixl_puts("avail_mem_map: "); 731 rmixl_puthex64((uint64_t)(intptr_t)avail_mem_map); 732 rmixl_puts("\r\n"); 733 #endif 734 if (avail_mem_map != NULL) { 735 map = avail_mem_map; 736 mapname = "avail_mem_map"; 737 rmixlfw_mmap_print(map); 738 } 739 #ifdef DIAGNOSTIC 740 else { 741 rmixl_puts("WARNING: no avail_mem_map\r\n"); 742 } 743 #endif 744 745 if (map == NULL) { 746 #ifndef MEMSIZE 747 rmixl_puts("panic: no firmware memory map, " 748 "must configure MEMSIZE\r\n"); 749 for(;;); /* XXX */ 750 #else 751 #ifdef DIAGNOSTIC 752 rmixl_puts("WARNING: no avail_mem_map, " 753 "using MEMSIZE\r\n"); 754 #endif 755 756 mem_clusters[0].start = 0; 757 mem_clusters[0].size = MEMSIZE; 758 mem_cluster_cnt = 1; 759 return MEMSIZE; 760 #endif /* MEMSIZE */ 761 } 762 763 #ifdef DIAGNOSTIC 764 rmixl_puts("using "); 765 rmixl_puts(mapname); 766 rmixl_puts("\r\n"); 767 #endif 768 #ifdef MACHDEP_DEBUG 769 rmixl_puts("memory clusters:\r\n"); 770 #endif 771 sum = 0; 772 cnt = 0; 773 for (uint32_t i=0; i < map->nmmaps; i++) { 774 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 775 continue; 776 mem_clusters[cnt].start = map->entry[i].start; 777 sz = map->entry[i].size; 778 sum += sz; 779 mem_clusters[cnt].size = sz; 780 #ifdef MACHDEP_DEBUG 781 rmixl_puthex32(i); 782 rmixl_puts(": "); 783 rmixl_puthex64(mem_clusters[cnt].start); 784 rmixl_puts(", "); 785 rmixl_puthex64(sz); 786 rmixl_puts(": "); 787 rmixl_puthex64(sum); 788 rmixl_puts("\r\n"); 789 #endif 790 #ifdef MEMSIZE 791 /* 792 * configurably limit memsize 793 */ 794 if (sum == memsize) 795 break; 796 if (sum > memsize) { 797 uint64_t tmp; 798 799 tmp = sum - memsize; 800 sz -= tmp; 801 sum -= tmp; 802 mem_clusters[cnt].size = sz; 803 cnt++; 804 break; 805 } 806 #endif 807 cnt++; 808 } 809 mem_cluster_cnt = cnt; 810 return sum; 811 } 812 813 #ifdef MULTIPROCESSOR 814 /* 815 * firmware passes wakeup info structure in CP0 OS Scratch reg #7 816 * they do not explicitly give us the size of the wakeup area. 817 * we "know" that firmware loader sets wip->gp thusly: 818 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 819 * so 820 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 821 * Only the "master" cpu runs this function, so 822 * vcpu = wip->master_cpu 823 */ 824 void 825 rmixl_get_wakeup_info(struct rmixl_config *rcp) 826 { 827 volatile rmixlfw_cpu_wakeup_info_t *wip; 828 int32_t scratch_7; 829 intptr_t end; 830 831 __asm__ volatile( 832 ".set push" "\n" 833 ".set noreorder" "\n" 834 ".set mips64" "\n" 835 "dmfc0 %0, $22, 7" "\n" 836 ".set pop" "\n" 837 : "=r"(scratch_7)); 838 839 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 840 (intptr_t)scratch_7; 841 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 842 843 if (wip->valid == 1) { 844 rcp->rc_cpu_wakeup_end = (const void *)end; 845 rcp->rc_cpu_wakeup_info = wip; 846 } 847 }; 848 849 #ifdef MACHDEP_DEBUG 850 static void 851 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 852 { 853 int i; 854 855 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 856 857 printf("cpu_status %#x\n", wip->cpu_status); 858 printf("valid: %d\n", wip->valid); 859 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 860 wip->entry.addr, 861 wip->entry.args, 862 wip->entry.sp, 863 wip->entry.gp); 864 printf("master_cpu %d\n", wip->master_cpu); 865 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 866 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 867 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 868 printf("argc %d\n", wip->argc); 869 printf("argv:"); 870 for (i=0; i < wip->argc; i++) 871 printf(" %#x", wip->argv[i]); 872 printf("\n"); 873 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 874 printf("tlb_map:\n"); 875 for (i=0; i < wip->valid_tlb_entries; i++) { 876 volatile const struct lib_cpu_tlb_mapping *m = 877 &wip->tlb_map[i]; 878 printf(" %d", m->page_size); 879 printf(", %d", m->asid); 880 printf(", %d", m->coherency); 881 printf(", %d", m->coherency); 882 printf(", %d", m->attr); 883 printf(", %#x", m->virt); 884 printf(", %#"PRIx64"\n", m->phys); 885 } 886 printf("elf segs:\n"); 887 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 888 volatile const struct core_segment_info *e = 889 &wip->seg_info[i]; 890 printf(" %#"PRIx64"", e->vaddr); 891 printf(", %#"PRIx64"", e->memsz); 892 printf(", %#x\n", e->flags); 893 } 894 printf("envc %d\n", wip->envc); 895 for (i=0; i < wip->envc; i++) 896 printf(" %#x \"%s\"", wip->envs[i], 897 (char *)(intptr_t)(int32_t)(wip->envs[i])); 898 printf("\n"); 899 printf("app_mode %d\n", wip->app_mode); 900 printf("printk_lock %#x\n", wip->printk_lock); 901 printf("kseg_master %d\n", wip->kseg_master); 902 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 903 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 904 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 905 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 906 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 907 printf("loader_lock %#x\n", wip->loader_lock); 908 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 909 printf("unused_0 %#x\n", wip->unused_0); 910 } 911 #endif /* MACHDEP_DEBUG */ 912 #endif /* MULTIPROCESSOR */ 913 914 void 915 consinit(void) 916 { 917 918 /* 919 * Everything related to console initialization is done 920 * in mach_init(). 921 */ 922 } 923 924 /* 925 * Allocate memory for variable-sized tables, 926 */ 927 void 928 cpu_startup() 929 { 930 vaddr_t minaddr, maxaddr; 931 char pbuf[9]; 932 933 /* 934 * Good {morning,afternoon,evening,night}. 935 */ 936 printf("%s%s", copyright, version); 937 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 938 printf("total memory = %s\n", pbuf); 939 940 /* 941 * Virtual memory is bootstrapped -- notify the bus spaces 942 * that memory allocation is now safe. 943 */ 944 rmixl_configuration.rc_mallocsafe = 1; 945 946 minaddr = 0; 947 /* 948 * Allocate a submap for physio. 949 */ 950 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 951 VM_PHYS_SIZE, 0, FALSE, NULL); 952 953 /* 954 * (No need to allocate an mbuf cluster submap. Mbuf clusters 955 * are allocated via the pool allocator, and we use XKSEG to 956 * map those pages.) 957 */ 958 959 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 960 printf("avail memory = %s\n", pbuf); 961 } 962 963 int waittime = -1; 964 965 void 966 cpu_reboot(howto, bootstr) 967 int howto; 968 char *bootstr; 969 { 970 971 /* Take a snapshot before clobbering any registers. */ 972 if (curproc) 973 savectx((struct user *)curpcb); 974 975 if (cold) { 976 howto |= RB_HALT; 977 goto haltsys; 978 } 979 980 /* If "always halt" was specified as a boot flag, obey. */ 981 if (boothowto & RB_HALT) 982 howto |= RB_HALT; 983 984 boothowto = howto; 985 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 986 waittime = 0; 987 vfs_shutdown(); 988 989 /* 990 * If we've been adjusting the clock, the todr 991 * will be out of synch; adjust it now. 992 */ 993 resettodr(); 994 } 995 996 splhigh(); 997 998 if (howto & RB_DUMP) 999 dumpsys(); 1000 1001 haltsys: 1002 doshutdownhooks(); 1003 1004 if (howto & RB_HALT) { 1005 printf("\n"); 1006 printf("The operating system has halted.\n"); 1007 printf("Please press any key to reboot.\n\n"); 1008 cnpollc(1); /* For proper keyboard command handling */ 1009 cngetc(); 1010 cnpollc(0); 1011 } 1012 1013 printf("rebooting...\n\n"); 1014 1015 rmixl_reset(); 1016 } 1017 1018 /* 1019 * goodbye world 1020 */ 1021 void __attribute__((__noreturn__)) 1022 rmixl_reset(void) 1023 { 1024 uint32_t r; 1025 1026 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1027 r |= RMIXL_GPIO_RESET_RESET; 1028 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1029 1030 printf("soft reset failed, spinning...\n"); 1031 for (;;); 1032 } 1033
Indexes created Sat Nov 01 05:10:12 GMT 2025