machdep.c revision 1.1.2.19
1 /* $NetBSD: machdep.c,v 1.1.2.19 2010/02/01 04:17:51 matt Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74 /* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114 #include <sys/cdefs.h> 115 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.1.2.19 2010/02/01 04:17:51 matt Exp $"); 116 117 #include "opt_ddb.h" 118 #include "opt_com.h" 119 #include "opt_execfmt.h" 120 #include "opt_memsize.h" 121 122 #include <sys/param.h> 123 #include <sys/systm.h> 124 #include <sys/kernel.h> 125 #include <sys/buf.h> 126 #include <sys/reboot.h> 127 #include <sys/user.h> 128 #include <sys/mount.h> 129 #include <sys/kcore.h> 130 #include <sys/boot_flag.h> 131 #include <sys/termios.h> 132 #include <sys/ksyms.h> 133 #include <sys/bus.h> 134 #include <sys/device.h> 135 #include <sys/extent.h> 136 #include <sys/malloc.h> 137 138 #include <uvm/uvm_extern.h> 139 140 #include <dev/cons.h> 141 142 #include "ksyms.h" 143 144 #if NKSYMS || defined(DDB) || defined(LKM) 145 #include <machine/db_machdep.h> 146 #include <ddb/db_extern.h> 147 #endif 148 149 #include <machine/cpu.h> 150 #include <machine/psl.h> 151 152 #include "com.h" 153 #if NCOM == 0 154 #error no serial console 155 #endif 156 157 #include <dev/ic/comreg.h> 158 #include <dev/ic/comvar.h> 159 160 #include <mips/rmi/rmixl_comvar.h> 161 #include <mips/rmi/rmixlvar.h> 162 #include <mips/rmi/rmixl_firmware.h> 163 #include <mips/rmi/rmixlreg.h> 164 165 #ifdef MACHDEP_DEBUG 166 int machdep_debug=MACHDEP_DEBUG; 167 # define DPRINTF(x) do { if (machdep_debug) printf x ; } while(0) 168 #else 169 # define DPRINTF(x) 170 #endif 171 172 #ifndef CONSFREQ 173 # define CONSFREQ 66000000 174 #endif 175 #ifndef CONSPEED 176 # define CONSPEED 38400 177 #endif 178 #ifndef CONMODE 179 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 180 #endif 181 #ifndef CONSADDR 182 # define CONSADDR RMIXL_IO_DEV_UART_1 183 #endif 184 185 int comcnfreq = CONSFREQ; 186 int comcnspeed = CONSPEED; 187 tcflag_t comcnmode = CONMODE; 188 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 189 190 struct rmixl_config rmixl_configuration; 191 192 193 /* 194 * array of tested firmware versions 195 * if you find new ones and they work 196 * please add them 197 */ 198 typedef struct rmiclfw_psb_id { 199 uint64_t psb_version; 200 rmixlfw_psb_type_t psb_type; 201 } rmiclfw_psb_id_t; 202 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 203 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 204 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 205 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 206 }; 207 #define RMICLFW_PSB_VERSIONS_LEN \ 208 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 209 210 /* 211 * storage for fixed extent used to allocate physical address regions 212 * because extent(9) start and end values are u_long, they are only 213 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 214 * address is 40 bits wide. So the "physaddr" map stores regions 215 * in units of megabytes. 216 */ 217 static u_long rmixl_physaddr_storage[ 218 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 219 ]; 220 221 /* For sysctl_hw. */ 222 extern char cpu_model[]; 223 224 /* Our exported CPU info; we can have only one. */ 225 struct cpu_info cpu_info_store; 226 227 /* Maps for VM objects. */ 228 struct vm_map *mb_map = NULL; 229 struct vm_map *phys_map = NULL; 230 231 int physmem; /* Total physical memory */ 232 233 int netboot; /* Are we netbooting? */ 234 235 236 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 237 u_int mem_cluster_cnt; 238 239 240 void configure(void); 241 void mach_init(int, int32_t *, void *, int64_t); 242 static uint64_t rmixlfw_init(int64_t); 243 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 244 static void __attribute__((__noreturn__)) rmixl_reset(void); 245 static void rmixl_physaddr_init(void); 246 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 247 void rmixlfw_mmap_print(rmixlfw_mmap_t *); 248 249 250 #ifdef MULTIPROCESSOR 251 void rmixl_get_wakeup_info(struct rmixl_config *); 252 #ifdef MACHDEP_DEBUG 253 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 254 #endif 255 #endif 256 257 258 /* 259 * safepri is a safe priority for sleep to set for a spin-wait during 260 * autoconfiguration or after a panic. Used as an argument to splx(). 261 */ 262 int safepri = MIPS1_PSL_LOWIPL; 263 264 /* 265 * Do all the stuff that locore normally does before calling main(). 266 */ 267 void 268 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 269 { 270 struct rmixl_config *rcp = &rmixl_configuration; 271 void *kernend; 272 uint64_t memsize; 273 u_int vm_cluster_cnt; 274 uint32_t r; 275 phys_ram_seg_t vm_clusters[VM_PHYSSEG_MAX]; 276 extern char edata[], end[]; 277 278 #ifndef MULTIPROCESSOR 279 rmixl_mtcr(0, 1); /* disable all threads except #0 */ 280 rmixl_mtcr(0x400, 0); /* enable MMU clock gating */ 281 /* set single MMU Thread Mode */ 282 /* TLB is partitioned (1 partition) */ 283 #endif 284 285 r = rmixl_mfcr(0x300); 286 r &= ~__BIT(14); /* disabled Unaligned Access */ 287 rmixl_mtcr(0x300, r); 288 289 /* 290 * Clear the BSS segment. 291 */ 292 kernend = (void *)mips_round_page(end); 293 memset(edata, 0, (char *)kernend - edata); 294 295 /* 296 * Set up the exception vectors and CPU-specific function 297 * vectors early on. We need the wbflush() vector set up 298 * before comcnattach() is called (or at least before the 299 * first printf() after that is called). 300 * Also clears the I+D caches. 301 */ 302 mips_vector_init(); 303 304 /* mips_vector_init initialized mips_options */ 305 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 306 307 /* get system info from firmware */ 308 memsize = rmixlfw_init(infop); 309 310 /* set the VM page size */ 311 uvm_setpagesize(); 312 313 physmem = btoc(memsize); 314 315 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 316 317 #if NCOM > 0 318 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 319 COM_TYPE_NORMAL, comcnmode); 320 #endif 321 322 printf("\nNetBSD/rmixl\n"); 323 printf("memsize = %#"PRIx64"\n", memsize); 324 325 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 326 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 327 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 328 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 329 rcp->rc_cpu_wakeup_info, 330 rcp->rc_cpu_wakeup_end); 331 printf("userapp_cpu_map: %#"PRIx64"\n", 332 rcp->rc_psb_info.userapp_cpu_map); 333 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 334 { 335 register_t sp; 336 asm volatile ("move %0, $sp\n" : "=r"(sp)); 337 printf("sp: %#"PRIx64"\n", sp); 338 } 339 #endif 340 341 rmixl_physaddr_init(); 342 343 /* 344 * Obtain the cpu frequency 345 * Compute the number of ticks for hz. 346 * Compute the delay divisor. 347 * Double the Hz if this CPU runs at twice the 348 * external/cp0-count frequency 349 */ 350 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 351 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 352 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 353 curcpu()->ci_divisor_delay = 354 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 355 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 356 curcpu()->ci_cpu_freq *= 2; 357 358 /* 359 * Look at arguments passed to us and compute boothowto. 360 * - rmixl firmware gives us a 32 bit argv[i], so adapt 361 * by forcing sign extension in cast to (char *) 362 */ 363 boothowto = RB_AUTOBOOT; 364 for (int i = 1; i < argc; i++) { 365 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 366 int howto; 367 /* Ignore superfluous '-', if there is one */ 368 if (*cp == '-') 369 continue; 370 371 howto = 0; 372 BOOT_FLAG(*cp, howto); 373 if (howto != 0) 374 boothowto |= howto; 375 #ifdef DIAGNOSTIC 376 else 377 printf("bootflag '%c' not recognised\n", *cp); 378 #endif 379 } 380 } 381 #ifdef DIAGNOSTIC 382 printf("boothowto %#x\n", boothowto); 383 #endif 384 385 /* 386 * Reserve pages from the VM system. 387 * to maintain mem_clusters[] as a map of raw ram, 388 * copy into temporary table vm_clusters[] 389 * work on that and use it to feed vm_physload() 390 */ 391 KASSERT(sizeof(mem_clusters) == sizeof(vm_clusters)); 392 memcpy(&vm_clusters, &mem_clusters, sizeof(vm_clusters)); 393 vm_cluster_cnt = mem_cluster_cnt; 394 395 /* reserve 0..start..kernend pages */ 396 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 397 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 398 399 /* reserve reset exception vector page */ 400 /* should never be in our clusters anyway... */ 401 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 402 0x1FC00000, 0x1FC00000+NBPG); 403 404 #ifdef MULTIPROCEESOR 405 /* reserve the cpu_wakeup_info area */ 406 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 407 (u_quad_t)trunc_page(rcp->rc_cpu_wakeup_info), 408 (u_quad_t)round_page(rcp->rc_cpu_wakeup_end)); 409 #endif 410 411 #ifdef MEMLIMIT 412 /* reserve everything > MEMLIMIT */ 413 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 414 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 415 #endif 416 417 /* 418 * Load vm_clusters[] into the VM system. 419 */ 420 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 421 vm_clusters, vm_cluster_cnt, NULL, 0); 422 423 /* 424 * Initialize error message buffer (at end of core). 425 */ 426 mips_init_msgbuf(); 427 428 pmap_bootstrap(); 429 430 /* 431 * Allocate space for proc0's USPACE. 432 */ 433 mips_init_lwp0_uarea(); 434 435 /* 436 * Initialize debuggers, and break into them, if appropriate. 437 */ 438 #if NKSYMS || defined(DDB) || defined(LKM) 439 ksyms_init(0, 0, 0); 440 #endif 441 442 #if defined(DDB) 443 if (boothowto & RB_KDB) 444 Debugger(); 445 #endif 446 } 447 448 /* 449 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 450 * 451 * we simply build a new table of segs, then copy it back over the given one 452 * this is inefficient but simple and called only a few times 453 * 454 * note: 'last' here means 1st addr past the end of the segment (start+size) 455 */ 456 static u_int 457 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 458 u_quad_t resv_first, u_quad_t resv_last) 459 { 460 u_quad_t first, last; 461 int new_nsegs=0; 462 int resv_flag; 463 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 464 465 for (u_int i=0; i < nsegs; i++) { 466 resv_flag = 0; 467 first = trunc_page(segs[i].start); 468 last = round_page(segs[i].start + segs[i].size); 469 470 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 471 if ((resv_first <= first) && (resv_last >= last)) { 472 /* whole segment is resverved */ 473 continue; 474 } 475 if ((resv_first > first) && (resv_first < last)) { 476 u_quad_t new_last; 477 478 /* 479 * reserved start in segment 480 * salvage the leading fragment 481 */ 482 resv_flag = 1; 483 new_last = last - (last - resv_first); 484 KASSERT (new_last > first); 485 new_segs[new_nsegs].start = first; 486 new_segs[new_nsegs].size = new_last - first; 487 new_nsegs++; 488 } 489 if ((resv_last > first) && (resv_last < last)) { 490 u_quad_t new_first; 491 492 /* 493 * reserved end in segment 494 * salvage the trailing fragment 495 */ 496 resv_flag = 1; 497 new_first = first + (resv_last - first); 498 KASSERT (last > (new_first + NBPG)); 499 new_segs[new_nsegs].start = new_first; 500 new_segs[new_nsegs].size = last - new_first; 501 new_nsegs++; 502 } 503 if (resv_flag == 0) { 504 /* 505 * nothing reserved here, take it all 506 */ 507 new_segs[new_nsegs].start = first; 508 new_segs[new_nsegs].size = last - first; 509 new_nsegs++; 510 } 511 512 } 513 514 memcpy(segs, new_segs, sizeof(new_segs)); 515 516 return new_nsegs; 517 } 518 519 /* 520 * create an extent for physical address space 521 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 522 * allocate the regions where we have known functions (DRAM, IO, etc) 523 * what remains can be allocated as needed for other stuff 524 * e.g. to configure BARs that are not already initialized and enabled. 525 */ 526 static void 527 rmixl_physaddr_init(void) 528 { 529 struct extent *ext; 530 unsigned long start = 0UL; 531 unsigned long end = (__BIT(40) / (1024 * 1024)) -1; 532 u_long base; 533 u_long size; 534 uint32_t r; 535 536 ext = extent_create("physaddr", start, end, M_DEVBUF, 537 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 538 EX_NOWAIT | EX_NOCOALESCE); 539 540 if (ext == NULL) 541 panic("%s: extent_create failed", __func__); 542 543 /* 544 * grab regions per DRAM BARs 545 */ 546 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 547 r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 548 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 549 continue; /* not enabled */ 550 base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024)); 551 size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024)); 552 553 DPRINTF(("%s: %d: %d: 0x%08x -- 0x%010lx:%lu MB\n", 554 __func__, __LINE__, i, r, base * (1024 * 1024), size)); 555 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 556 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 557 "failed", __func__, ext, base, size, EX_NOWAIT); 558 } 559 560 /* 561 * grab regions per PCIe CFG, ECFG, IO, MEM BARs 562 */ 563 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_CFG_BAR); 564 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 565 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 566 / (1024 * 1024)); 567 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 568 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 569 __LINE__, "CFG", r, base * 1024 * 1024, size)); 570 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 571 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 572 "failed", __func__, ext, base, size, EX_NOWAIT); 573 } 574 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_ECFG_BAR); 575 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 576 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 577 / (1024 * 1024)); 578 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 579 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 580 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 581 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 582 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 583 "failed", __func__, ext, base, size, EX_NOWAIT); 584 } 585 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_MEM_BAR); 586 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 587 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 588 / (1024 * 1024)); 589 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 590 / (1024 * 1024)); 591 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 592 __LINE__, "MEM", r, base * 1024 * 1024, size)); 593 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 594 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 595 "failed", __func__, ext, base, size, EX_NOWAIT); 596 } 597 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_IO_BAR); 598 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 599 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 600 / (1024 * 1024)); 601 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 602 / (1024 * 1024)); 603 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 604 __LINE__, "IO", r, base * 1024 * 1024, size)); 605 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 606 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 607 "failed", __func__, ext, base, size, EX_NOWAIT); 608 } 609 610 /* 611 * at this point all regions left in "physaddr" extent 612 * are unused holes in the physical adress space 613 * available for use as needed. 614 */ 615 rmixl_configuration.rc_phys_ex = ext; 616 #ifdef MACHDEP_DEBUG 617 extent_print(ext); 618 #endif 619 } 620 621 static uint64_t 622 rmixlfw_init(int64_t infop) 623 { 624 struct rmixl_config *rcp = &rmixl_configuration; 625 626 #ifdef MULTIPROCESSOR 627 rmixl_get_wakeup_info(rcp); 628 #endif 629 630 infop |= MIPS_KSEG0_START; 631 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 632 633 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 634 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 635 if (rmiclfw_psb_id[i].psb_version == 636 rcp->rc_psb_info.psb_version) { 637 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 638 goto found; 639 } 640 } 641 642 rcp->rc_io_pbase = RMIXL_IO_DEV_PBASE; 643 rmixl_putchar_init(rcp->rc_io_pbase); 644 645 #ifdef DIAGNOSTIC 646 rmixl_puts("\r\nWARNING: untested psb_version: "); 647 rmixl_puthex64(rcp->rc_psb_info.psb_version); 648 rmixl_puts("\r\n"); 649 #endif 650 651 #ifdef MEMSIZE 652 /* XXX trust and use MEMSIZE */ 653 mem_clusters[0].start = 0; 654 mem_clusters[0].size = MEMSIZE; 655 mem_cluster_cnt = 1; 656 return MEMSIZE; 657 #else 658 rmixl_puts("\r\nERROR: configure MEMSIZE\r\n"); 659 cpu_reboot(RB_HALT, NULL); 660 /* NOTREACHED */ 661 #endif 662 663 found: 664 rcp->rc_io_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 665 rmixl_putchar_init(rcp->rc_io_pbase); 666 #ifdef MACHDEP_DEBUG 667 rmixl_puts("\r\ninfop: "); 668 rmixl_puthex64((uint64_t)(intptr_t)infop); 669 #endif 670 #ifdef DIAGNOSTIC 671 rmixl_puts("\r\nrecognized psb_version="); 672 rmixl_puthex64(rcp->rc_psb_info.psb_version); 673 rmixl_puts(", psb_type="); 674 rmixl_puts(rmixlfw_psb_type_name(rcp->rc_psb_type)); 675 rmixl_puts("\r\n"); 676 #endif 677 678 return mem_clusters_init( 679 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 680 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 681 } 682 683 void 684 rmixlfw_mmap_print(rmixlfw_mmap_t *map) 685 { 686 #ifdef MACHDEP_DEBUG 687 for (uint32_t i=0; i < map->nmmaps; i++) { 688 rmixl_puthex32(i); 689 rmixl_puts(", "); 690 rmixl_puthex64(map->entry[i].start); 691 rmixl_puts(", "); 692 rmixl_puthex64(map->entry[i].size); 693 rmixl_puts(", "); 694 rmixl_puthex32(map->entry[i].type); 695 rmixl_puts("\r\n"); 696 } 697 #endif 698 } 699 700 /* 701 * mem_clusters_init 702 * 703 * initialize mem_clusters[] table based on memory address mapping 704 * provided by boot firmware. 705 * 706 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 707 * these will be limited by MEMSIZE if it is configured. 708 * if neither are available, just use MEMSIZE. 709 */ 710 static uint64_t 711 mem_clusters_init( 712 rmixlfw_mmap_t *psb_physaddr_map, 713 rmixlfw_mmap_t *avail_mem_map) 714 { 715 rmixlfw_mmap_t *map = NULL; 716 const char *mapname; 717 uint64_t sz; 718 uint64_t sum; 719 u_int cnt; 720 #ifdef MEMSIZE 721 uint64_t memsize = MEMSIZE; 722 #endif 723 724 #ifdef MACHDEP_DEBUG 725 rmixl_puts("psb_physaddr_map: "); 726 rmixl_puthex64((uint64_t)(intptr_t)psb_physaddr_map); 727 rmixl_puts("\r\n"); 728 #endif 729 if (psb_physaddr_map != NULL) { 730 map = psb_physaddr_map; 731 mapname = "psb_physaddr_map"; 732 rmixlfw_mmap_print(map); 733 } 734 #ifdef DIAGNOSTIC 735 else { 736 rmixl_puts("WARNING: no psb_physaddr_map\r\n"); 737 } 738 #endif 739 740 #ifdef MACHDEP_DEBUG 741 rmixl_puts("avail_mem_map: "); 742 rmixl_puthex64((uint64_t)(intptr_t)avail_mem_map); 743 rmixl_puts("\r\n"); 744 #endif 745 if (avail_mem_map != NULL) { 746 map = avail_mem_map; 747 mapname = "avail_mem_map"; 748 rmixlfw_mmap_print(map); 749 } 750 #ifdef DIAGNOSTIC 751 else { 752 rmixl_puts("WARNING: no avail_mem_map\r\n"); 753 } 754 #endif 755 756 if (map == NULL) { 757 #ifndef MEMSIZE 758 rmixl_puts("panic: no firmware memory map, " 759 "must configure MEMSIZE\r\n"); 760 for(;;); /* XXX */ 761 #else 762 #ifdef DIAGNOSTIC 763 rmixl_puts("WARNING: no avail_mem_map, " 764 "using MEMSIZE\r\n"); 765 #endif 766 767 mem_clusters[0].start = 0; 768 mem_clusters[0].size = MEMSIZE; 769 mem_cluster_cnt = 1; 770 return MEMSIZE; 771 #endif /* MEMSIZE */ 772 } 773 774 #ifdef DIAGNOSTIC 775 rmixl_puts("using "); 776 rmixl_puts(mapname); 777 rmixl_puts("\r\n"); 778 #endif 779 #ifdef MACHDEP_DEBUG 780 rmixl_puts("memory clusters:\r\n"); 781 #endif 782 sum = 0; 783 cnt = 0; 784 for (uint32_t i=0; i < map->nmmaps; i++) { 785 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 786 continue; 787 mem_clusters[cnt].start = map->entry[i].start; 788 sz = map->entry[i].size; 789 sum += sz; 790 mem_clusters[cnt].size = sz; 791 #ifdef MACHDEP_DEBUG 792 rmixl_puthex32(i); 793 rmixl_puts(": "); 794 rmixl_puthex64(mem_clusters[cnt].start); 795 rmixl_puts(", "); 796 rmixl_puthex64(sz); 797 rmixl_puts(": "); 798 rmixl_puthex64(sum); 799 rmixl_puts("\r\n"); 800 #endif 801 #ifdef MEMSIZE 802 /* 803 * configurably limit memsize 804 */ 805 if (sum == memsize) 806 break; 807 if (sum > memsize) { 808 uint64_t tmp; 809 810 tmp = sum - memsize; 811 sz -= tmp; 812 sum -= tmp; 813 mem_clusters[cnt].size = sz; 814 cnt++; 815 break; 816 } 817 #endif 818 cnt++; 819 } 820 mem_cluster_cnt = cnt; 821 return sum; 822 } 823 824 #ifdef MULTIPROCESSOR 825 /* 826 * firmware passes wakeup info structure in CP0 OS Scratch reg #7 827 * they do not explicitly give us the size of the wakeup area. 828 * we "know" that firmware loader sets wip->gp thusly: 829 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 830 * so 831 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 832 * Only the "master" cpu runs this function, so 833 * vcpu = wip->master_cpu 834 */ 835 void 836 rmixl_get_wakeup_info(struct rmixl_config *rcp) 837 { 838 volatile rmixlfw_cpu_wakeup_info_t *wip; 839 int32_t scratch_7; 840 intptr_t end; 841 842 __asm__ volatile( 843 ".set push" "\n" 844 ".set noreorder" "\n" 845 ".set mips64" "\n" 846 "dmfc0 %0, $22, 7" "\n" 847 ".set pop" "\n" 848 : "=r"(scratch_7)); 849 850 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 851 (intptr_t)scratch_7; 852 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 853 854 if (wip->valid == 1) { 855 rcp->rc_cpu_wakeup_end = (const void *)end; 856 rcp->rc_cpu_wakeup_info = wip; 857 } 858 }; 859 860 #ifdef MACHDEP_DEBUG 861 static void 862 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 863 { 864 int i; 865 866 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 867 868 printf("cpu_status %#x\n", wip->cpu_status); 869 printf("valid: %d\n", wip->valid); 870 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 871 wip->entry.addr, 872 wip->entry.args, 873 wip->entry.sp, 874 wip->entry.gp); 875 printf("master_cpu %d\n", wip->master_cpu); 876 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 877 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 878 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 879 printf("argc %d\n", wip->argc); 880 printf("argv:"); 881 for (i=0; i < wip->argc; i++) 882 printf(" %#x", wip->argv[i]); 883 printf("\n"); 884 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 885 printf("tlb_map:\n"); 886 for (i=0; i < wip->valid_tlb_entries; i++) { 887 volatile const struct lib_cpu_tlb_mapping *m = 888 &wip->tlb_map[i]; 889 printf(" %d", m->page_size); 890 printf(", %d", m->asid); 891 printf(", %d", m->coherency); 892 printf(", %d", m->coherency); 893 printf(", %d", m->attr); 894 printf(", %#x", m->virt); 895 printf(", %#"PRIx64"\n", m->phys); 896 } 897 printf("elf segs:\n"); 898 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 899 volatile const struct core_segment_info *e = 900 &wip->seg_info[i]; 901 printf(" %#"PRIx64"", e->vaddr); 902 printf(", %#"PRIx64"", e->memsz); 903 printf(", %#x\n", e->flags); 904 } 905 printf("envc %d\n", wip->envc); 906 for (i=0; i < wip->envc; i++) 907 printf(" %#x \"%s\"", wip->envs[i], 908 (char *)(intptr_t)(int32_t)(wip->envs[i])); 909 printf("\n"); 910 printf("app_mode %d\n", wip->app_mode); 911 printf("printk_lock %#x\n", wip->printk_lock); 912 printf("kseg_master %d\n", wip->kseg_master); 913 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 914 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 915 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 916 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 917 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 918 printf("loader_lock %#x\n", wip->loader_lock); 919 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 920 printf("unused_0 %#x\n", wip->unused_0); 921 } 922 #endif /* MACHDEP_DEBUG */ 923 #endif /* MULTIPROCESSOR */ 924 925 void 926 consinit(void) 927 { 928 929 /* 930 * Everything related to console initialization is done 931 * in mach_init(). 932 */ 933 } 934 935 /* 936 * Allocate memory for variable-sized tables, 937 */ 938 void 939 cpu_startup() 940 { 941 vaddr_t minaddr, maxaddr; 942 char pbuf[9]; 943 944 /* 945 * Good {morning,afternoon,evening,night}. 946 */ 947 printf("%s%s", copyright, version); 948 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 949 printf("total memory = %s\n", pbuf); 950 951 /* 952 * Virtual memory is bootstrapped -- notify the bus spaces 953 * that memory allocation is now safe. 954 */ 955 rmixl_configuration.rc_mallocsafe = 1; 956 957 minaddr = 0; 958 /* 959 * Allocate a submap for physio. 960 */ 961 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 962 VM_PHYS_SIZE, 0, FALSE, NULL); 963 964 /* 965 * (No need to allocate an mbuf cluster submap. Mbuf clusters 966 * are allocated via the pool allocator, and we use XKSEG to 967 * map those pages.) 968 */ 969 970 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 971 printf("avail memory = %s\n", pbuf); 972 } 973 974 int waittime = -1; 975 976 void 977 cpu_reboot(howto, bootstr) 978 int howto; 979 char *bootstr; 980 { 981 982 /* Take a snapshot before clobbering any registers. */ 983 savectx(curlwp->l_addr); 984 985 if (cold) { 986 howto |= RB_HALT; 987 goto haltsys; 988 } 989 990 /* If "always halt" was specified as a boot flag, obey. */ 991 if (boothowto & RB_HALT) 992 howto |= RB_HALT; 993 994 boothowto = howto; 995 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 996 waittime = 0; 997 vfs_shutdown(); 998 999 /* 1000 * If we've been adjusting the clock, the todr 1001 * will be out of synch; adjust it now. 1002 */ 1003 resettodr(); 1004 } 1005 1006 splhigh(); 1007 1008 if (howto & RB_DUMP) 1009 dumpsys(); 1010 1011 haltsys: 1012 doshutdownhooks(); 1013 1014 if (howto & RB_HALT) { 1015 printf("\n"); 1016 printf("The operating system has halted.\n"); 1017 printf("Please press any key to reboot.\n\n"); 1018 cnpollc(1); /* For proper keyboard command handling */ 1019 cngetc(); 1020 cnpollc(0); 1021 } 1022 1023 printf("rebooting...\n\n"); 1024 1025 rmixl_reset(); 1026 } 1027 1028 /* 1029 * goodbye world 1030 */ 1031 void __attribute__((__noreturn__)) 1032 rmixl_reset(void) 1033 { 1034 uint32_t r; 1035 1036 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1037 r |= RMIXL_GPIO_RESET_RESET; 1038 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1039 1040 printf("soft reset failed, spinning...\n"); 1041 for (;;); 1042 } 1043
Indexes created Fri Oct 31 11:10:07 GMT 2025