machdep.c revision 1.1.2.24
1 /* $NetBSD: machdep.c,v 1.1.2.24 2010/03/09 02:04:46 matt Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74 /* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114 #include <sys/cdefs.h> 115 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.1.2.24 2010/03/09 02:04:46 matt Exp $"); 116 117 #include "opt_ddb.h" 118 #include "opt_com.h" 119 #include "opt_execfmt.h" 120 #include "opt_memsize.h" 121 122 #include <sys/param.h> 123 #include <sys/systm.h> 124 #include <sys/kernel.h> 125 #include <sys/buf.h> 126 #include <sys/reboot.h> 127 #include <sys/user.h> 128 #include <sys/mount.h> 129 #include <sys/kcore.h> 130 #include <sys/boot_flag.h> 131 #include <sys/termios.h> 132 #include <sys/ksyms.h> 133 #include <sys/bus.h> 134 #include <sys/device.h> 135 #include <sys/extent.h> 136 #include <sys/malloc.h> 137 138 #include <uvm/uvm_extern.h> 139 140 #include <dev/cons.h> 141 142 #include "ksyms.h" 143 144 #if NKSYMS || defined(DDB) || defined(LKM) 145 #include <machine/db_machdep.h> 146 #include <ddb/db_extern.h> 147 #endif 148 149 #include <machine/cpu.h> 150 #include <machine/psl.h> 151 152 #include "com.h" 153 #if NCOM == 0 154 #error no serial console 155 #endif 156 157 #include <dev/ic/comreg.h> 158 #include <dev/ic/comvar.h> 159 160 #include <mips/rmi/rmixl_comvar.h> 161 #include <mips/rmi/rmixlvar.h> 162 #include <mips/rmi/rmixl_firmware.h> 163 #include <mips/rmi/rmixlreg.h> 164 165 #ifdef MACHDEP_DEBUG 166 int machdep_debug=MACHDEP_DEBUG; 167 # define DPRINTF(x) do { if (machdep_debug) printf x ; } while(0) 168 #else 169 # define DPRINTF(x) 170 #endif 171 172 #ifndef CONSFREQ 173 # define CONSFREQ 66000000 174 #endif 175 #ifndef CONSPEED 176 # define CONSPEED 38400 177 #endif 178 #ifndef CONMODE 179 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 180 #endif 181 #ifndef CONSADDR 182 # define CONSADDR RMIXL_IO_DEV_UART_1 183 #endif 184 185 int comcnfreq = CONSFREQ; 186 int comcnspeed = CONSPEED; 187 tcflag_t comcnmode = CONMODE; 188 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 189 190 struct rmixl_config rmixl_configuration; 191 192 193 /* 194 * array of tested firmware versions 195 * if you find new ones and they work 196 * please add them 197 */ 198 typedef struct rmiclfw_psb_id { 199 uint64_t psb_version; 200 rmixlfw_psb_type_t psb_type; 201 } rmiclfw_psb_id_t; 202 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 203 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 204 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 205 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 206 }; 207 #define RMICLFW_PSB_VERSIONS_LEN \ 208 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 209 210 /* 211 * storage for fixed extent used to allocate physical address regions 212 * because extent(9) start and end values are u_long, they are only 213 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 214 * address is 40 bits wide. So the "physaddr" map stores regions 215 * in units of megabytes. 216 */ 217 static u_long rmixl_physaddr_storage[ 218 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 219 ]; 220 221 /* For sysctl_hw. */ 222 extern char cpu_model[]; 223 224 /* Our exported CPU info; we can have only one. */ 225 struct cpu_info cpu_info_store; 226 227 /* Maps for VM objects. */ 228 struct vm_map *mb_map = NULL; 229 struct vm_map *phys_map = NULL; 230 231 int physmem; /* Total physical memory */ 232 233 int netboot; /* Are we netbooting? */ 234 235 236 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 237 u_int mem_cluster_cnt; 238 239 240 void configure(void); 241 void mach_init(int, int32_t *, void *, int64_t); 242 static uint64_t rmixlfw_init(int64_t); 243 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 244 static void __attribute__((__noreturn__)) rmixl_reset(void); 245 static void rmixl_physaddr_init(void); 246 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 247 void rmixlfw_mmap_print(rmixlfw_mmap_t *); 248 249 250 #ifdef MULTIPROCESSOR 251 static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2]); 252 void rmixl_get_wakeup_info(struct rmixl_config *); 253 #ifdef MACHDEP_DEBUG 254 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 255 #endif 256 #endif 257 258 259 /* 260 * safepri is a safe priority for sleep to set for a spin-wait during 261 * autoconfiguration or after a panic. Used as an argument to splx(). 262 */ 263 int safepri = MIPS1_PSL_LOWIPL; 264 265 /* 266 * Do all the stuff that locore normally does before calling main(). 267 */ 268 void 269 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 270 { 271 struct rmixl_config *rcp = &rmixl_configuration; 272 void *kernend; 273 uint64_t memsize; 274 u_int vm_cluster_cnt; 275 uint32_t r; 276 phys_ram_seg_t vm_clusters[VM_PHYSSEG_MAX]; 277 extern char edata[], end[]; 278 279 #ifndef MULTIPROCESSOR 280 rmixl_mtcr(0, 1); /* disable all threads except #0 */ 281 rmixl_mtcr(0x400, 0); /* enable MMU clock gating */ 282 /* set single MMU Thread Mode */ 283 /* TLB is partitioned (1 partition) */ 284 #endif 285 286 r = rmixl_mfcr(0x300); 287 r &= ~__BIT(14); /* disabled Unaligned Access */ 288 rmixl_mtcr(0x300, r); 289 290 /* 291 * Clear the BSS segment. 292 */ 293 kernend = (void *)mips_round_page(end); 294 memset(edata, 0, (char *)kernend - edata); 295 296 /* 297 * Set up the exception vectors and CPU-specific function 298 * vectors early on. We need the wbflush() vector set up 299 * before comcnattach() is called (or at least before the 300 * first printf() after that is called). 301 * Also clears the I+D caches. 302 */ 303 mips_vector_init(); 304 305 /* mips_vector_init initialized mips_options */ 306 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 307 308 /* get system info from firmware */ 309 memsize = rmixlfw_init(infop); 310 311 /* set the VM page size */ 312 uvm_setpagesize(); 313 314 physmem = btoc(memsize); 315 316 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 317 318 #if NCOM > 0 319 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 320 COM_TYPE_NORMAL, comcnmode); 321 #endif 322 323 printf("\nNetBSD/rmixl\n"); 324 printf("memsize = %#"PRIx64"\n", memsize); 325 326 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 327 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 328 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 329 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 330 rcp->rc_cpu_wakeup_info, 331 rcp->rc_cpu_wakeup_end); 332 printf("userapp_cpu_map: %#"PRIx64"\n", 333 rcp->rc_psb_info.userapp_cpu_map); 334 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 335 { 336 register_t sp; 337 asm volatile ("move %0, $sp\n" : "=r"(sp)); 338 printf("sp: %#"PRIx64"\n", sp); 339 } 340 #endif 341 342 rmixl_physaddr_init(); 343 344 /* 345 * Obtain the cpu frequency 346 * Compute the number of ticks for hz. 347 * Compute the delay divisor. 348 * Double the Hz if this CPU runs at twice the 349 * external/cp0-count frequency 350 */ 351 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 352 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 353 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 354 curcpu()->ci_divisor_delay = 355 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 356 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 357 curcpu()->ci_cpu_freq *= 2; 358 359 /* 360 * Look at arguments passed to us and compute boothowto. 361 * - rmixl firmware gives us a 32 bit argv[i], so adapt 362 * by forcing sign extension in cast to (char *) 363 */ 364 boothowto = RB_AUTOBOOT; 365 for (int i = 1; i < argc; i++) { 366 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 367 int howto; 368 /* Ignore superfluous '-', if there is one */ 369 if (*cp == '-') 370 continue; 371 372 howto = 0; 373 BOOT_FLAG(*cp, howto); 374 if (howto != 0) 375 boothowto |= howto; 376 #ifdef DIAGNOSTIC 377 else 378 printf("bootflag '%c' not recognised\n", *cp); 379 #endif 380 } 381 } 382 #ifdef DIAGNOSTIC 383 printf("boothowto %#x\n", boothowto); 384 #endif 385 386 /* 387 * Reserve pages from the VM system. 388 * to maintain mem_clusters[] as a map of raw ram, 389 * copy into temporary table vm_clusters[] 390 * work on that and use it to feed vm_physload() 391 */ 392 KASSERT(sizeof(mem_clusters) == sizeof(vm_clusters)); 393 memcpy(&vm_clusters, &mem_clusters, sizeof(vm_clusters)); 394 vm_cluster_cnt = mem_cluster_cnt; 395 396 /* reserve 0..start..kernend pages */ 397 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 398 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 399 400 /* reserve reset exception vector page */ 401 /* should never be in our clusters anyway... */ 402 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 403 0x1FC00000, 0x1FC00000+NBPG); 404 405 #ifdef MULTIPROCEESOR 406 /* reserve the cpu_wakeup_info area */ 407 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 408 (u_quad_t)trunc_page(rcp->rc_cpu_wakeup_info), 409 (u_quad_t)round_page(rcp->rc_cpu_wakeup_end)); 410 #endif 411 412 #ifdef MEMLIMIT 413 /* reserve everything > MEMLIMIT */ 414 vm_cluster_cnt = ram_seg_resv(vm_clusters, vm_cluster_cnt, 415 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 416 #endif 417 418 /* 419 * Load vm_clusters[] into the VM system. 420 */ 421 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 422 vm_clusters, vm_cluster_cnt, NULL, 0); 423 424 /* 425 * Initialize error message buffer (at end of core). 426 */ 427 mips_init_msgbuf(); 428 429 pmap_bootstrap(); 430 431 /* 432 * Allocate space for proc0's USPACE. 433 */ 434 mips_init_lwp0_uarea(); 435 436 /* 437 * Initialize debuggers, and break into them, if appropriate. 438 */ 439 #if NKSYMS || defined(DDB) || defined(LKM) 440 ksyms_init(0, 0, 0); 441 #endif 442 443 #if defined(DDB) 444 if (boothowto & RB_KDB) 445 Debugger(); 446 #endif 447 #ifdef MULTIPROCESSOR 448 /* 449 * Fix up the exception vector to use COP0 OSSCRATCH0 450 */ 451 __asm __volatile("dmtc0 %0,$%1" 452 :: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH)); 453 mips_fixup_exceptions(rmixl_fixup_cop0_oscratch); 454 #endif 455 } 456 457 #ifdef MULTIPROCESSOR 458 static bool 459 rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2]) 460 { 461 size_t offset = load_addr - (intptr_t)&cpu_info_store; 462 463 KASSERT(MIPS_KSEG0_P(load_addr)); 464 KASSERT(offset < sizeof(struct cpu_info)); 465 466 /* 467 * Fixup this direct load cpu_info_store to actually get the current 468 * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be 469 * relative from the start of struct cpu_info. 470 */ 471 472 /* [0] = [d]mfc0 rX, $22 (OSScratch) */ 473 new_insns[0] = (020 << 26) 474 #ifdef _LP64 475 | (1 << 21) /* double move */ 476 #endif 477 | (new_insns[0] & 0x001f0000) 478 | (MIPS_COP_0_OSSCRATCH << 11) | (0 << 0); 479 480 /* [1] = l[dw] rX, offset(rX) */ 481 new_insns[1] = (new_insns[1] & 0xffff0000) | offset; 482 483 return true; 484 } 485 #endif /* MULTIPROCESSOR */ 486 487 /* 488 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 489 * 490 * we simply build a new table of segs, then copy it back over the given one 491 * this is inefficient but simple and called only a few times 492 * 493 * note: 'last' here means 1st addr past the end of the segment (start+size) 494 */ 495 static u_int 496 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 497 u_quad_t resv_first, u_quad_t resv_last) 498 { 499 u_quad_t first, last; 500 int new_nsegs=0; 501 int resv_flag; 502 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 503 504 for (u_int i=0; i < nsegs; i++) { 505 resv_flag = 0; 506 first = trunc_page(segs[i].start); 507 last = round_page(segs[i].start + segs[i].size); 508 509 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 510 if ((resv_first <= first) && (resv_last >= last)) { 511 /* whole segment is resverved */ 512 continue; 513 } 514 if ((resv_first > first) && (resv_first < last)) { 515 u_quad_t new_last; 516 517 /* 518 * reserved start in segment 519 * salvage the leading fragment 520 */ 521 resv_flag = 1; 522 new_last = last - (last - resv_first); 523 KASSERT (new_last > first); 524 new_segs[new_nsegs].start = first; 525 new_segs[new_nsegs].size = new_last - first; 526 new_nsegs++; 527 } 528 if ((resv_last > first) && (resv_last < last)) { 529 u_quad_t new_first; 530 531 /* 532 * reserved end in segment 533 * salvage the trailing fragment 534 */ 535 resv_flag = 1; 536 new_first = first + (resv_last - first); 537 KASSERT (last > (new_first + NBPG)); 538 new_segs[new_nsegs].start = new_first; 539 new_segs[new_nsegs].size = last - new_first; 540 new_nsegs++; 541 } 542 if (resv_flag == 0) { 543 /* 544 * nothing reserved here, take it all 545 */ 546 new_segs[new_nsegs].start = first; 547 new_segs[new_nsegs].size = last - first; 548 new_nsegs++; 549 } 550 551 } 552 553 memcpy(segs, new_segs, sizeof(new_segs)); 554 555 return new_nsegs; 556 } 557 558 /* 559 * create an extent for physical address space 560 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 561 * allocate the regions where we have known functions (DRAM, IO, etc) 562 * what remains can be allocated as needed for other stuff 563 * e.g. to configure BARs that are not already initialized and enabled. 564 */ 565 static void 566 rmixl_physaddr_init(void) 567 { 568 struct extent *ext; 569 unsigned long start = 0UL; 570 unsigned long end = (__BIT(40) / (1024 * 1024)) -1; 571 u_long base; 572 u_long size; 573 uint32_t r; 574 575 ext = extent_create("physaddr", start, end, M_DEVBUF, 576 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 577 EX_NOWAIT | EX_NOCOALESCE); 578 579 if (ext == NULL) 580 panic("%s: extent_create failed", __func__); 581 582 /* 583 * grab regions per DRAM BARs 584 */ 585 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 586 r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 587 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 588 continue; /* not enabled */ 589 base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024)); 590 size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024)); 591 592 DPRINTF(("%s: %d: %d: 0x%08x -- 0x%010lx:%lu MB\n", 593 __func__, __LINE__, i, r, base * (1024 * 1024), size)); 594 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 595 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 596 "failed", __func__, ext, base, size, EX_NOWAIT); 597 } 598 599 /* 600 * grab regions per PCIe CFG, ECFG, IO, MEM BARs 601 */ 602 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_CFG_BAR); 603 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) { 604 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r) 605 / (1024 * 1024)); 606 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024); 607 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 608 __LINE__, "CFG", r, base * 1024 * 1024, size)); 609 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 610 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 611 "failed", __func__, ext, base, size, EX_NOWAIT); 612 } 613 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_ECFG_BAR); 614 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) { 615 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r) 616 / (1024 * 1024)); 617 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024); 618 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 619 __LINE__, "ECFG", r, base * 1024 * 1024, size)); 620 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 621 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 622 "failed", __func__, ext, base, size, EX_NOWAIT); 623 } 624 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_MEM_BAR); 625 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) { 626 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r) 627 / (1024 * 1024)); 628 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r) 629 / (1024 * 1024)); 630 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 631 __LINE__, "MEM", r, base * 1024 * 1024, size)); 632 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 633 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 634 "failed", __func__, ext, base, size, EX_NOWAIT); 635 } 636 r = RMIXL_IOREG_READ(RMIXL_SBC_PCIE_IO_BAR); 637 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) { 638 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r) 639 / (1024 * 1024)); 640 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r) 641 / (1024 * 1024)); 642 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__, 643 __LINE__, "IO", r, base * 1024 * 1024, size)); 644 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 645 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 646 "failed", __func__, ext, base, size, EX_NOWAIT); 647 } 648 649 /* 650 * at this point all regions left in "physaddr" extent 651 * are unused holes in the physical adress space 652 * available for use as needed. 653 */ 654 rmixl_configuration.rc_phys_ex = ext; 655 #ifdef MACHDEP_DEBUG 656 extent_print(ext); 657 #endif 658 } 659 660 static uint64_t 661 rmixlfw_init(int64_t infop) 662 { 663 struct rmixl_config *rcp = &rmixl_configuration; 664 665 #ifdef MULTIPROCESSOR 666 rmixl_get_wakeup_info(rcp); 667 #endif 668 669 infop |= MIPS_KSEG0_START; 670 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 671 672 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 673 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 674 if (rmiclfw_psb_id[i].psb_version == 675 rcp->rc_psb_info.psb_version) { 676 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 677 goto found; 678 } 679 } 680 681 rcp->rc_io_pbase = RMIXL_IO_DEV_PBASE; 682 rmixl_putchar_init(rcp->rc_io_pbase); 683 684 #ifdef DIAGNOSTIC 685 rmixl_puts("\r\nWARNING: untested psb_version: "); 686 rmixl_puthex64(rcp->rc_psb_info.psb_version); 687 rmixl_puts("\r\n"); 688 #endif 689 690 #ifdef MEMSIZE 691 /* XXX trust and use MEMSIZE */ 692 mem_clusters[0].start = 0; 693 mem_clusters[0].size = MEMSIZE; 694 mem_cluster_cnt = 1; 695 return MEMSIZE; 696 #else 697 rmixl_puts("\r\nERROR: configure MEMSIZE\r\n"); 698 cpu_reboot(RB_HALT, NULL); 699 /* NOTREACHED */ 700 #endif 701 702 found: 703 rcp->rc_io_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 704 rmixl_putchar_init(rcp->rc_io_pbase); 705 #ifdef MACHDEP_DEBUG 706 rmixl_puts("\r\ninfop: "); 707 rmixl_puthex64((uint64_t)(intptr_t)infop); 708 #endif 709 #ifdef DIAGNOSTIC 710 rmixl_puts("\r\nrecognized psb_version="); 711 rmixl_puthex64(rcp->rc_psb_info.psb_version); 712 rmixl_puts(", psb_type="); 713 rmixl_puts(rmixlfw_psb_type_name(rcp->rc_psb_type)); 714 rmixl_puts("\r\n"); 715 #endif 716 717 return mem_clusters_init( 718 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 719 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 720 } 721 722 void 723 rmixlfw_mmap_print(rmixlfw_mmap_t *map) 724 { 725 #ifdef MACHDEP_DEBUG 726 for (uint32_t i=0; i < map->nmmaps; i++) { 727 rmixl_puthex32(i); 728 rmixl_puts(", "); 729 rmixl_puthex64(map->entry[i].start); 730 rmixl_puts(", "); 731 rmixl_puthex64(map->entry[i].size); 732 rmixl_puts(", "); 733 rmixl_puthex32(map->entry[i].type); 734 rmixl_puts("\r\n"); 735 } 736 #endif 737 } 738 739 /* 740 * mem_clusters_init 741 * 742 * initialize mem_clusters[] table based on memory address mapping 743 * provided by boot firmware. 744 * 745 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 746 * these will be limited by MEMSIZE if it is configured. 747 * if neither are available, just use MEMSIZE. 748 */ 749 static uint64_t 750 mem_clusters_init( 751 rmixlfw_mmap_t *psb_physaddr_map, 752 rmixlfw_mmap_t *avail_mem_map) 753 { 754 rmixlfw_mmap_t *map = NULL; 755 const char *mapname; 756 uint64_t sz; 757 uint64_t sum; 758 u_int cnt; 759 #ifdef MEMSIZE 760 uint64_t memsize = MEMSIZE; 761 #endif 762 763 #ifdef MACHDEP_DEBUG 764 rmixl_puts("psb_physaddr_map: "); 765 rmixl_puthex64((uint64_t)(intptr_t)psb_physaddr_map); 766 rmixl_puts("\r\n"); 767 #endif 768 if (psb_physaddr_map != NULL) { 769 map = psb_physaddr_map; 770 mapname = "psb_physaddr_map"; 771 rmixlfw_mmap_print(map); 772 } 773 #ifdef DIAGNOSTIC 774 else { 775 rmixl_puts("WARNING: no psb_physaddr_map\r\n"); 776 } 777 #endif 778 779 #ifdef MACHDEP_DEBUG 780 rmixl_puts("avail_mem_map: "); 781 rmixl_puthex64((uint64_t)(intptr_t)avail_mem_map); 782 rmixl_puts("\r\n"); 783 #endif 784 if (avail_mem_map != NULL) { 785 map = avail_mem_map; 786 mapname = "avail_mem_map"; 787 rmixlfw_mmap_print(map); 788 } 789 #ifdef DIAGNOSTIC 790 else { 791 rmixl_puts("WARNING: no avail_mem_map\r\n"); 792 } 793 #endif 794 795 if (map == NULL) { 796 #ifndef MEMSIZE 797 rmixl_puts("panic: no firmware memory map, " 798 "must configure MEMSIZE\r\n"); 799 for(;;); /* XXX */ 800 #else 801 #ifdef DIAGNOSTIC 802 rmixl_puts("WARNING: no avail_mem_map, " 803 "using MEMSIZE\r\n"); 804 #endif 805 806 mem_clusters[0].start = 0; 807 mem_clusters[0].size = MEMSIZE; 808 mem_cluster_cnt = 1; 809 return MEMSIZE; 810 #endif /* MEMSIZE */ 811 } 812 813 #ifdef DIAGNOSTIC 814 rmixl_puts("using "); 815 rmixl_puts(mapname); 816 rmixl_puts("\r\n"); 817 #endif 818 #ifdef MACHDEP_DEBUG 819 rmixl_puts("memory clusters:\r\n"); 820 #endif 821 sum = 0; 822 cnt = 0; 823 for (uint32_t i=0; i < map->nmmaps; i++) { 824 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 825 continue; 826 mem_clusters[cnt].start = map->entry[i].start; 827 sz = map->entry[i].size; 828 sum += sz; 829 mem_clusters[cnt].size = sz; 830 #ifdef MACHDEP_DEBUG 831 rmixl_puthex32(i); 832 rmixl_puts(": "); 833 rmixl_puthex64(mem_clusters[cnt].start); 834 rmixl_puts(", "); 835 rmixl_puthex64(sz); 836 rmixl_puts(": "); 837 rmixl_puthex64(sum); 838 rmixl_puts("\r\n"); 839 #endif 840 #ifdef MEMSIZE 841 /* 842 * configurably limit memsize 843 */ 844 if (sum == memsize) 845 break; 846 if (sum > memsize) { 847 uint64_t tmp; 848 849 tmp = sum - memsize; 850 sz -= tmp; 851 sum -= tmp; 852 mem_clusters[cnt].size = sz; 853 cnt++; 854 break; 855 } 856 #endif 857 cnt++; 858 } 859 mem_cluster_cnt = cnt; 860 return sum; 861 } 862 863 #ifdef MULTIPROCESSOR 864 /* 865 * firmware passes wakeup info structure in CP0 OS Scratch reg #7 866 * they do not explicitly give us the size of the wakeup area. 867 * we "know" that firmware loader sets wip->gp thusly: 868 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 869 * so 870 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 871 * Only the "master" cpu runs this function, so 872 * vcpu = wip->master_cpu 873 */ 874 void 875 rmixl_get_wakeup_info(struct rmixl_config *rcp) 876 { 877 volatile rmixlfw_cpu_wakeup_info_t *wip; 878 int32_t scratch_7; 879 intptr_t end; 880 881 __asm__ volatile( 882 ".set push" "\n" 883 ".set noreorder" "\n" 884 ".set mips64" "\n" 885 "dmfc0 %0, $22, 7" "\n" 886 ".set pop" "\n" 887 : "=r"(scratch_7)); 888 889 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 890 (intptr_t)scratch_7; 891 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 892 893 if (wip->valid == 1) { 894 rcp->rc_cpu_wakeup_end = (const void *)end; 895 rcp->rc_cpu_wakeup_info = wip; 896 } 897 }; 898 899 #ifdef MACHDEP_DEBUG 900 static void 901 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 902 { 903 int i; 904 905 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 906 907 printf("cpu_status %#x\n", wip->cpu_status); 908 printf("valid: %d\n", wip->valid); 909 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 910 wip->entry.addr, 911 wip->entry.args, 912 wip->entry.sp, 913 wip->entry.gp); 914 printf("master_cpu %d\n", wip->master_cpu); 915 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 916 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 917 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 918 printf("argc %d\n", wip->argc); 919 printf("argv:"); 920 for (i=0; i < wip->argc; i++) 921 printf(" %#x", wip->argv[i]); 922 printf("\n"); 923 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 924 printf("tlb_map:\n"); 925 for (i=0; i < wip->valid_tlb_entries; i++) { 926 volatile const struct lib_cpu_tlb_mapping *m = 927 &wip->tlb_map[i]; 928 printf(" %d", m->page_size); 929 printf(", %d", m->asid); 930 printf(", %d", m->coherency); 931 printf(", %d", m->coherency); 932 printf(", %d", m->attr); 933 printf(", %#x", m->virt); 934 printf(", %#"PRIx64"\n", m->phys); 935 } 936 printf("elf segs:\n"); 937 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 938 volatile const struct core_segment_info *e = 939 &wip->seg_info[i]; 940 printf(" %#"PRIx64"", e->vaddr); 941 printf(", %#"PRIx64"", e->memsz); 942 printf(", %#x\n", e->flags); 943 } 944 printf("envc %d\n", wip->envc); 945 for (i=0; i < wip->envc; i++) 946 printf(" %#x \"%s\"", wip->envs[i], 947 (char *)(intptr_t)(int32_t)(wip->envs[i])); 948 printf("\n"); 949 printf("app_mode %d\n", wip->app_mode); 950 printf("printk_lock %#x\n", wip->printk_lock); 951 printf("kseg_master %d\n", wip->kseg_master); 952 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 953 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 954 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 955 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 956 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 957 printf("loader_lock %#x\n", wip->loader_lock); 958 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 959 printf("unused_0 %#x\n", wip->unused_0); 960 } 961 #endif /* MACHDEP_DEBUG */ 962 #endif /* MULTIPROCESSOR */ 963 964 void 965 consinit(void) 966 { 967 968 /* 969 * Everything related to console initialization is done 970 * in mach_init(). 971 */ 972 } 973 974 /* 975 * Allocate memory for variable-sized tables, 976 */ 977 void 978 cpu_startup() 979 { 980 vaddr_t minaddr, maxaddr; 981 char pbuf[9]; 982 983 /* 984 * Good {morning,afternoon,evening,night}. 985 */ 986 printf("%s%s", copyright, version); 987 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 988 printf("total memory = %s\n", pbuf); 989 990 /* 991 * Virtual memory is bootstrapped -- notify the bus spaces 992 * that memory allocation is now safe. 993 */ 994 rmixl_configuration.rc_mallocsafe = 1; 995 996 minaddr = 0; 997 /* 998 * Allocate a submap for physio. 999 */ 1000 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 1001 VM_PHYS_SIZE, 0, FALSE, NULL); 1002 1003 /* 1004 * (No need to allocate an mbuf cluster submap. Mbuf clusters 1005 * are allocated via the pool allocator, and we use XKSEG to 1006 * map those pages.) 1007 */ 1008 1009 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 1010 printf("avail memory = %s\n", pbuf); 1011 } 1012 1013 int waittime = -1; 1014 1015 void 1016 cpu_reboot(howto, bootstr) 1017 int howto; 1018 char *bootstr; 1019 { 1020 1021 /* Take a snapshot before clobbering any registers. */ 1022 savectx(curlwp->l_addr); 1023 1024 if (cold) { 1025 howto |= RB_HALT; 1026 goto haltsys; 1027 } 1028 1029 /* If "always halt" was specified as a boot flag, obey. */ 1030 if (boothowto & RB_HALT) 1031 howto |= RB_HALT; 1032 1033 boothowto = howto; 1034 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 1035 waittime = 0; 1036 vfs_shutdown(); 1037 1038 /* 1039 * If we've been adjusting the clock, the todr 1040 * will be out of synch; adjust it now. 1041 */ 1042 resettodr(); 1043 } 1044 1045 splhigh(); 1046 1047 if (howto & RB_DUMP) 1048 dumpsys(); 1049 1050 haltsys: 1051 doshutdownhooks(); 1052 1053 if (howto & RB_HALT) { 1054 printf("\n"); 1055 printf("The operating system has halted.\n"); 1056 printf("Please press any key to reboot.\n\n"); 1057 cnpollc(1); /* For proper keyboard command handling */ 1058 cngetc(); 1059 cnpollc(0); 1060 } 1061 1062 printf("rebooting...\n\n"); 1063 1064 rmixl_reset(); 1065 } 1066 1067 /* 1068 * goodbye world 1069 */ 1070 void __attribute__((__noreturn__)) 1071 rmixl_reset(void) 1072 { 1073 uint32_t r; 1074 1075 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1076 r |= RMIXL_GPIO_RESET_RESET; 1077 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1078 1079 printf("soft reset failed, spinning...\n"); 1080 for (;;); 1081 } 1082
Indexes created Sat Nov 01 05:10:12 GMT 2025