machdep.c revision 1.1.2.38
1 /* machdep.c,v 1.1.2.34 2011/04/29 08:26:18 matt Exp */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1988 University of Utah. 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * the Systems Programming Group of the University of Utah Computer 45 * Science Department, The Mach Operating System project at 46 * Carnegie-Mellon University and Ralph Campbell. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 73 * from: Utah Hdr: machdep.c 1.63 91/04/24 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "machdep.c,v 1.1.2.34 2011/04/29 08:26:18 matt Exp"); 78 79 #define __INTR_PRIVATE 80 #define __MUTEX_PRIVATE 81 82 #include "opt_multiprocessor.h" 83 #include "opt_ddb.h" 84 #include "opt_com.h" 85 #include "opt_execfmt.h" 86 #include "opt_memsize.h" 87 #include "rmixl_pcix.h" 88 #include "rmixl_pcie.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/kernel.h> 93 #include <sys/buf.h> 94 #include <sys/reboot.h> 95 #include <sys/mount.h> 96 #include <sys/kcore.h> 97 #include <sys/boot_flag.h> 98 #include <sys/termios.h> 99 #include <sys/ksyms.h> 100 #include <sys/intr.h> 101 #include <sys/bus.h> 102 #include <sys/device.h> 103 #include <sys/extent.h> 104 #include <sys/malloc.h> 105 106 #include <uvm/uvm_extern.h> 107 108 #include <dev/cons.h> 109 110 #include "ksyms.h" 111 112 #if NKSYMS || defined(DDB) || defined(LKM) 113 #include <mips/db_machdep.h> 114 #include <ddb/db_extern.h> 115 #endif 116 117 #include <mips/cpu.h> 118 #include <mips/psl.h> 119 #include <mips/cache.h> 120 #include <mips/mips_opcode.h> 121 #include <mips/pte.h> 122 123 #include "com.h" 124 #if NCOM == 0 125 #error no serial console 126 #endif 127 128 #include <dev/ic/comreg.h> 129 #include <dev/ic/comvar.h> 130 131 #include <mips/rmi/rmixlreg.h> 132 #include <mips/rmi/rmixlvar.h> 133 #include <mips/rmi/rmixl_intr.h> 134 #include <mips/rmi/rmixl_firmware.h> 135 #include <mips/rmi/rmixl_comvar.h> 136 #include <mips/rmi/rmixl_pcievar.h> 137 #include <mips/rmi/rmixl_pcixvar.h> 138 139 #ifdef MACHDEP_DEBUG 140 int machdep_debug=MACHDEP_DEBUG; 141 # define DPRINTF(x) do { if (machdep_debug) printf x ; } while(0) 142 #else 143 # define DPRINTF(x) 144 #endif 145 146 #ifndef CONSFREQ 147 # define CONSFREQ 66000000 148 #endif 149 #ifndef CONSPEED 150 # define CONSPEED 38400 151 #endif 152 #ifndef CONMODE 153 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 154 #endif 155 #ifndef CONSADDR 156 # define CONSADDR RMIXL_IO_DEV_UART_1 157 #endif 158 159 int comcnfreq = CONSFREQ; 160 int comcnspeed = CONSPEED; 161 tcflag_t comcnmode = CONMODE; 162 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 163 164 struct rmixl_config rmixl_configuration; 165 166 #ifdef ENABLE_MIPS_KSEGX 167 pt_entry_t mips_ksegx_pte; 168 paddr_t mips_ksegx_start; 169 #endif 170 171 /* 172 * array of tested firmware versions 173 * if you find new ones and they work 174 * please add them 175 */ 176 typedef struct rmiclfw_psb_id { 177 uint64_t psb_version; 178 rmixlfw_psb_type_t psb_type; 179 } rmiclfw_psb_id_t; 180 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 181 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 182 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 183 { 0x4b67d03200000056ULL, PSB_TYPE_RMI }, 184 { 0x4c17058b00000056ULL, PSB_TYPE_RMI }, 185 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 186 { 0x4b8ead3100000056ULL, PSB_TYPE_DELL }, 187 }; 188 #define RMICLFW_PSB_VERSIONS_LEN \ 189 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 190 191 /* 192 * storage for fixed extent used to allocate physical address regions 193 * because extent(9) start and end values are u_long, they are only 194 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 195 * address is 40 bits wide. So the "physaddr" map stores regions 196 * in units of megabytes. 197 */ 198 static u_long rmixl_physaddr_storage[ 199 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 200 ]; 201 202 /* For sysctl_hw. */ 203 extern char cpu_model[]; 204 205 /* Our exported CPU info; we can have only one. */ 206 struct cpu_info cpu_info_store; 207 208 /* Maps for VM objects. */ 209 struct vm_map *mb_map = NULL; 210 struct vm_map *phys_map = NULL; 211 212 int physmem; /* Total physical memory */ 213 214 int netboot; /* Are we netbooting? */ 215 216 217 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 218 u_quad_t mem_cluster_maxaddr; 219 u_int mem_cluster_cnt; 220 221 222 void configure(void); 223 void mach_init(int, int32_t *, void *, int64_t); 224 static uint64_t rmixlfw_init(int64_t); 225 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 226 static void __attribute__((__noreturn__)) rmixl_reset(void); 227 static void rmixl_physaddr_init(void); 228 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 229 void rmixlfw_mmap_print(rmixlfw_mmap_t *); 230 231 232 #ifdef MULTIPROCESSOR 233 static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2]); 234 void rmixl_get_wakeup_info(struct rmixl_config *); 235 #ifdef MACHDEP_DEBUG 236 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 237 #endif /* MACHDEP_DEBUG */ 238 #endif /* MULTIPROCESSOR */ 239 static void rmixl_fixup_curcpu(void); 240 241 #if NCOM > 0 242 static volatile uint32_t *rmixl_com0addr; 243 static int 244 rmixl_cngetc(dev_t dv) 245 { 246 volatile uint32_t * const com0addr = rmixl_com0addr; 247 248 if ((be32toh(com0addr[com_lsr]) & LSR_RXRDY) == 0) 249 return -1; 250 251 return be32toh(com0addr[com_data]) & 0xff; 252 } 253 254 static void 255 rmixl_cnputc(dev_t dv, int c) 256 { 257 volatile uint32_t * const com0addr = rmixl_com0addr; 258 int timo = 150000; 259 260 while ((be32toh(com0addr[com_lsr]) & LSR_TXRDY) == 0 && --timo > 0) 261 ; 262 263 com0addr[com_data] = htobe32(c); 264 __asm __volatile("sync"); 265 266 while ((be32toh(com0addr[com_lsr]) & LSR_TSRE) == 0 && --timo > 0) 267 ; 268 } 269 270 struct consdev rmixl_earlycons = { 271 .cn_putc = rmixl_cnputc, 272 .cn_getc = rmixl_cngetc, 273 .cn_pollc = nullcnpollc, 274 }; 275 #endif 276 277 /* 278 * Do all the stuff that locore normally does before calling main(). 279 */ 280 void 281 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 282 { 283 struct rmixl_config *rcp = &rmixl_configuration; 284 void *kernend; 285 uint64_t memsize; 286 extern char edata[], end[]; 287 size_t fl_count = 0; 288 struct mips_vmfreelist fl[1]; 289 290 rmixl_pcr_init_core(); 291 292 #ifdef MULTIPROCESSOR 293 __asm __volatile("dmtc0 %0,$%1,2" 294 :: "r"(&pmap_tlb0_info.ti_hwlock->mtx_lock), 295 "n"(MIPS_COP_0_OSSCRATCH)); 296 #endif 297 298 /* 299 * Clear the BSS segment. 300 */ 301 kernend = (void *)mips_round_page(end); 302 memset(edata, 0, (char *)kernend - edata); 303 304 #if NCOM > 0 305 rmixl_com0addr = (void *)(vaddr_t)(RMIXL_IO_DEV_VBASE + comcnaddr); 306 cn_tab = &rmixl_earlycons; /* after clearing BSS, not before */ 307 #endif 308 309 /* 310 * Set up the exception vectors and CPU-specific function 311 * vectors early on. We need the wbflush() vector set up 312 * before comcnattach() is called (or at least before the 313 * first printf() after that is called). 314 * Also clears the I+D caches. 315 * 316 * specify chip-specific EIRR/EIMR based spl functions 317 */ 318 #ifdef MULTIPROCESSOR 319 mips_vector_init(&rmixl_splsw, true); 320 #else 321 mips_vector_init(&rmixl_splsw, false); 322 #endif 323 324 /* mips_vector_init initialized mips_options */ 325 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 326 327 /* get system info from firmware */ 328 memsize = rmixlfw_init(infop); 329 330 /* set the VM page size */ 331 uvm_setpagesize(); 332 333 physmem = btoc(memsize); 334 335 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 336 337 #if NCOM > 0 338 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 339 COM_TYPE_NORMAL, comcnmode); 340 #endif 341 342 printf("\nNetBSD/rmixl\n"); 343 printf("memsize = %#"PRIx64"\n", memsize); 344 #ifdef MEMLIMIT 345 printf("memlimit = %#"PRIx64"\n", (uint64_t)MEMLIMIT); 346 #endif 347 348 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 349 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 350 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 351 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 352 rcp->rc_cpu_wakeup_info, 353 rcp->rc_cpu_wakeup_end); 354 printf("userapp_cpu_map: %#"PRIx64"\n", 355 rcp->rc_psb_info.userapp_cpu_map); 356 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 357 { 358 register_t sp; 359 asm volatile ("move %0, $sp\n" : "=r"(sp)); 360 printf("sp: %#"PRIx64"\n", sp); 361 } 362 #endif 363 364 rmixl_physaddr_init(); 365 366 /* 367 * Obtain the cpu frequency 368 * Compute the number of ticks for hz. 369 * Compute the delay divisor. 370 * Double the Hz if this CPU runs at twice the 371 * external/cp0-count frequency 372 */ 373 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 374 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 375 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 376 curcpu()->ci_divisor_delay = 377 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 378 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 379 curcpu()->ci_cpu_freq *= 2; 380 381 /* 382 * Look at arguments passed to us and compute boothowto. 383 * - rmixl firmware gives us a 32 bit argv[i], so adapt 384 * by forcing sign extension in cast to (char *) 385 */ 386 boothowto = RB_AUTOBOOT; 387 for (int i = 1; i < argc; i++) { 388 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 389 int howto; 390 /* Ignore superfluous '-', if there is one */ 391 if (*cp == '-') 392 continue; 393 394 howto = 0; 395 BOOT_FLAG(*cp, howto); 396 if (howto != 0) 397 boothowto |= howto; 398 #ifdef DIAGNOSTIC 399 else 400 printf("bootflag '%c' not recognised\n", *cp); 401 #endif 402 } 403 } 404 #ifdef DIAGNOSTIC 405 printf("boothowto %#x\n", boothowto); 406 #endif 407 408 /* 409 * Reserve pages from the VM system. 410 */ 411 412 /* reserve 0..start..kernend pages */ 413 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 414 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 415 416 /* reserve reset exception vector page */ 417 /* should never be in our clusters anyway... */ 418 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 419 0x1FC00000, 0x1FC00000+NBPG); 420 421 #ifdef MULTIPROCESSOR 422 /* reserve the cpu_wakeup_info area */ 423 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 424 (u_quad_t)trunc_page((vaddr_t)rcp->rc_cpu_wakeup_info), 425 (u_quad_t)round_page((vaddr_t)rcp->rc_cpu_wakeup_end)); 426 #endif 427 428 #ifdef MEMLIMIT 429 /* reserve everything >= MEMLIMIT */ 430 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 431 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 432 #endif 433 434 #ifdef ENABLE_MIPS_KSEGX 435 /* 436 * Now we need to reserve an aligned block of memory for pre-init 437 * allocations so we don't deplete KSEG0. 438 */ 439 for (u_int i=0; i < mem_cluster_cnt; i++) { 440 u_quad_t finish = round_page( 441 mem_clusters[i].start + mem_clusters[i].size); 442 u_quad_t start = roundup2(mem_clusters[i].start, VM_KSEGX_SIZE); 443 if (start > MIPS_PHYS_MASK && start + VM_KSEGX_SIZE <= finish) { 444 mips_ksegx_start = start; 445 mips_ksegx_pte.pt_entry = mips_paddr_to_tlbpfn(start) 446 | MIPS3_PG_D | MIPS3_PG_CACHED 447 | MIPS3_PG_V | MIPS3_PG_G; 448 fl[0].fl_start = start; 449 fl[0].fl_end = start + VM_KSEGX_SIZE; 450 fl[0].fl_freelist = VM_FREELIST_FIRST512M; 451 fl_count++; 452 DPRINTF(("mips_ksegx_start %#"PRIxPADDR"\n", 453 fl[0].fl_start)); 454 break; 455 } 456 } 457 #endif 458 459 /* get maximum RAM address from the VM clusters */ 460 mem_cluster_maxaddr = 0; 461 for (u_int i=0; i < mem_cluster_cnt; i++) { 462 u_quad_t tmp = round_page( 463 mem_clusters[i].start + mem_clusters[i].size); 464 if (tmp > mem_cluster_maxaddr) 465 mem_cluster_maxaddr = tmp; 466 } 467 DPRINTF(("mem_cluster_maxaddr %#"PRIx64"\n", mem_cluster_maxaddr)); 468 469 /* 470 * Load mem_clusters[] into the VM system. 471 */ 472 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 473 mem_clusters, mem_cluster_cnt, fl, fl_count); 474 475 /* 476 * Initialize error message buffer (at end of core). 477 */ 478 mips_init_msgbuf(); 479 480 pmap_bootstrap(); 481 482 /* 483 * Allocate uarea page for lwp0 and set it. 484 */ 485 mips_init_lwp0_uarea(); 486 487 /* 488 * Initialize debuggers, and break into them, if appropriate. 489 */ 490 #if NKSYMS || defined(DDB) || defined(LKM) 491 ksyms_init(0, 0, 0); 492 #endif 493 494 #if defined(DDB) 495 if (boothowto & RB_KDB) 496 Debugger(); 497 #endif 498 /* 499 * store (cpu#0) curcpu in COP0 OSSCRATCH0 500 * used in exception vector 501 */ 502 __asm __volatile("dmtc0 %0,$%1" 503 :: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH)); 504 #ifdef MULTIPROCESSOR 505 mips_fixup_exceptions(rmixl_fixup_cop0_oscratch); 506 #endif 507 rmixl_fixup_curcpu(); 508 } 509 510 /* 511 * set up Processor Control Regs for this core 512 */ 513 void 514 rmixl_pcr_init_core() 515 { 516 uint32_t r; 517 518 #ifdef MULTIPROCESSOR 519 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0)); 520 /* enable MMU clock gating */ 521 /* 4 threads active -- why needed if Global? */ 522 /* enable global TLB mode */ 523 #else 524 rmixl_mtcr(RMIXL_PCR_THREADEN, 1); /* disable all threads except #0 */ 525 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, 0); /* enable MMU clock gating */ 526 /* set single MMU Thread Mode */ 527 /* TLB is partitioned (1 partition) */ 528 #endif 529 530 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 531 r &= ~__BIT(14); /* disable Unaligned Access */ 532 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 533 534 #if defined(DDB) && defined(MIPS_DDB_WATCH) 535 /* 536 * clear IEU_DEFEATURE[DBE] 537 * this enables COP0 watchpoint to trigger T_WATCH exception 538 * instead of signaling JTAG. 539 */ 540 r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE); 541 r &= ~__BIT(7); 542 rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r); 543 #endif 544 } 545 546 #ifdef MULTIPROCESSOR 547 static bool 548 rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2]) 549 { 550 size_t offset = load_addr - (intptr_t)&cpu_info_store; 551 552 KASSERT(MIPS_KSEG0_P(load_addr)); 553 KASSERT(offset < sizeof(struct cpu_info)); 554 555 /* 556 * Fixup this direct load cpu_info_store to actually get the current 557 * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be 558 * relative from the start of struct cpu_info. 559 */ 560 561 /* [0] = [d]mfc0 rX, $22 (OSScratch) */ 562 new_insns[0] = (020 << 26) 563 #ifdef _LP64 564 | (1 << 21) /* double move */ 565 #endif 566 | (new_insns[0] & 0x001f0000) 567 | (MIPS_COP_0_OSSCRATCH << 11) | (0 << 0); 568 569 /* [1] = [ls][dw] rX, offset(rX) */ 570 new_insns[1] = (new_insns[1] & 0xffff0000) | offset; 571 572 return true; 573 } 574 #endif /* MULTIPROCESSOR */ 575 576 /* 577 * The following changes all lX rN, L_CPU(MIPS_CURLWP) [curlwp->l_cpu] 578 * to [d]mfc0 rN, $22 [MIPS_COP_0_OSSCRATCH] 579 * 580 * the mfc0 is 3 cycles shorter than the load. 581 */ 582 #define LOAD_CURCPU_0 ((MIPS_CURLWP_REG << 21) | offsetof(lwp_t, l_cpu)) 583 #define MFC0_CURCPU_0 ((OP_COP0 << 26) | (MIPS_COP_0_OSSCRATCH << 11)) 584 #ifdef _LP64 585 #define LOAD_CURCPU ((uint32_t)(OP_LD << 26) | LOAD_CURCPU_0) 586 #define MFC0_CURCPU ((uint32_t)(OP_DMF << 21) | MFC0_CURCPU_0) 587 #else 588 #define LOAD_CURCPU ((uint32_t)(OP_LW << 26) | LOAD_CURCPU_0) 589 #define MFC0_CURCPU ((uint32_t)(OP_MF << 21) | MFC0_CURCPU_0) 590 #endif 591 #define LOAD_CURCPU_MASK 0xffe0ffff 592 593 static void 594 rmixl_fixup_curcpu(void) 595 { 596 extern uint32_t _ftext[]; 597 extern uint32_t _etext[]; 598 599 for (uint32_t *insnp = _ftext; insnp < _etext; insnp++) { 600 const uint32_t insn = *insnp; 601 if (__predict_false((insn & LOAD_CURCPU_MASK) == LOAD_CURCPU)) { 602 /* 603 * Since the register to loaded is located in bits 604 * 16-20 for the mfc0 and the load instruction we can 605 * just change the instruction bits around it. 606 */ 607 *insnp = insn ^ LOAD_CURCPU ^ MFC0_CURCPU; 608 mips_icache_sync_range((vaddr_t)insnp, 4); 609 } 610 } 611 } 612 613 /* 614 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 615 * 616 * we simply build a new table of segs, then copy it back over the given one 617 * this is inefficient but simple and called only a few times 618 * 619 * note: 'last' here means 1st addr past the end of the segment (start+size) 620 */ 621 static u_int 622 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 623 u_quad_t resv_first, u_quad_t resv_last) 624 { 625 u_quad_t first, last; 626 int new_nsegs=0; 627 int resv_flag; 628 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 629 630 for (u_int i=0; i < nsegs; i++) { 631 resv_flag = 0; 632 first = trunc_page(segs[i].start); 633 last = round_page(segs[i].start + segs[i].size); 634 635 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 636 if ((resv_first <= first) && (resv_last >= last)) { 637 /* whole segment is resverved */ 638 continue; 639 } 640 if ((resv_first > first) && (resv_first < last)) { 641 u_quad_t new_last; 642 643 /* 644 * reserved start in segment 645 * salvage the leading fragment 646 */ 647 resv_flag = 1; 648 new_last = last - (last - resv_first); 649 KASSERT (new_last > first); 650 new_segs[new_nsegs].start = first; 651 new_segs[new_nsegs].size = new_last - first; 652 new_nsegs++; 653 } 654 if ((resv_last > first) && (resv_last < last)) { 655 u_quad_t new_first; 656 657 /* 658 * reserved end in segment 659 * salvage the trailing fragment 660 */ 661 resv_flag = 1; 662 new_first = first + (resv_last - first); 663 KASSERT (last > (new_first + NBPG)); 664 new_segs[new_nsegs].start = new_first; 665 new_segs[new_nsegs].size = last - new_first; 666 new_nsegs++; 667 } 668 if (resv_flag == 0) { 669 /* 670 * nothing reserved here, take it all 671 */ 672 new_segs[new_nsegs].start = first; 673 new_segs[new_nsegs].size = last - first; 674 new_nsegs++; 675 } 676 677 } 678 679 memcpy(segs, new_segs, sizeof(new_segs)); 680 681 return new_nsegs; 682 } 683 684 /* 685 * create an extent for physical address space 686 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 687 * allocate the regions where we have known functions (DRAM, IO, etc) 688 * what remains can be allocated as needed for other stuff 689 * e.g. to configure BARs that are not already initialized and enabled. 690 */ 691 static void 692 rmixl_physaddr_init(void) 693 { 694 struct extent *ext; 695 unsigned long start = 0UL; 696 unsigned long end = (__BIT(40) / (1024 * 1024)) -1; 697 u_long base; 698 u_long size; 699 uint32_t r; 700 701 ext = extent_create("physaddr", start, end, M_DEVBUF, 702 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 703 EX_NOWAIT | EX_NOCOALESCE); 704 705 if (ext == NULL) 706 panic("%s: extent_create failed", __func__); 707 708 /* 709 * grab regions per DRAM BARs 710 */ 711 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 712 r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 713 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 714 continue; /* not enabled */ 715 base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024)); 716 size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024)); 717 718 DPRINTF(("%s: %d: %d: 0x%08x -- 0x%010lx:%lu MB\n", 719 __func__, __LINE__, i, r, base * (1024 * 1024), size)); 720 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 721 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 722 "failed", __func__, ext, base, size, EX_NOWAIT); 723 } 724 725 /* 726 * get chip-dependent physaddr regions 727 */ 728 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 729 case CIDFL_RMI_TYPE_XLR: 730 #if NRMIXL_PCIX 731 rmixl_physaddr_init_pcix(ext); 732 #endif 733 break; 734 case CIDFL_RMI_TYPE_XLS: 735 #if NRMIXL_PCIE 736 rmixl_physaddr_init_pcie(ext); 737 #endif 738 break; 739 case CIDFL_RMI_TYPE_XLP: 740 /* XXX TBD */ 741 panic("%s: RMI XLP not yet supported", __func__); 742 } 743 744 /* 745 * at this point all regions left in "physaddr" extent 746 * are unused holes in the physical adress space 747 * available for use as needed. 748 */ 749 rmixl_configuration.rc_phys_ex = ext; 750 #ifdef MACHDEP_DEBUG 751 extent_print(ext); 752 #endif 753 } 754 755 static uint64_t 756 rmixlfw_init(int64_t infop) 757 { 758 struct rmixl_config *rcp = &rmixl_configuration; 759 760 #ifdef MULTIPROCESSOR 761 rmixl_get_wakeup_info(rcp); 762 #endif 763 764 infop |= MIPS_KSEG0_START; 765 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 766 767 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 768 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 769 if (rmiclfw_psb_id[i].psb_version == 770 rcp->rc_psb_info.psb_version) { 771 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 772 goto found; 773 } 774 } 775 776 rcp->rc_io_pbase = RMIXL_IO_DEV_PBASE; 777 rmixl_putchar_init(rcp->rc_io_pbase); 778 779 #ifdef DIAGNOSTIC 780 rmixl_puts("\r\nWARNING: untested psb_version: "); 781 rmixl_puthex64(rcp->rc_psb_info.psb_version); 782 rmixl_puts("\r\n"); 783 #endif 784 785 #ifdef MEMSIZE 786 /* XXX trust and use MEMSIZE */ 787 mem_clusters[0].start = 0; 788 mem_clusters[0].size = MEMSIZE; 789 mem_cluster_cnt = 1; 790 return MEMSIZE; 791 #else 792 rmixl_puts("\r\nERROR: configure MEMSIZE\r\n"); 793 cpu_reboot(RB_HALT, NULL); 794 /* NOTREACHED */ 795 #endif 796 797 found: 798 rcp->rc_io_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 799 rmixl_putchar_init(rcp->rc_io_pbase); 800 #ifdef MACHDEP_DEBUG 801 rmixl_puts("\r\ninfop: "); 802 rmixl_puthex64((uint64_t)(intptr_t)infop); 803 #endif 804 #ifdef DIAGNOSTIC 805 rmixl_puts("\r\nrecognized psb_version="); 806 rmixl_puthex64(rcp->rc_psb_info.psb_version); 807 rmixl_puts(", psb_type="); 808 rmixl_puts(rmixlfw_psb_type_name(rcp->rc_psb_type)); 809 rmixl_puts("\r\n"); 810 #endif 811 812 return mem_clusters_init( 813 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 814 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 815 } 816 817 void 818 rmixlfw_mmap_print(rmixlfw_mmap_t *map) 819 { 820 #ifdef MACHDEP_DEBUG 821 for (uint32_t i=0; i < map->nmmaps; i++) { 822 rmixl_puthex32(i); 823 rmixl_puts(", "); 824 rmixl_puthex64(map->entry[i].start); 825 rmixl_puts(", "); 826 rmixl_puthex64(map->entry[i].size); 827 rmixl_puts(", "); 828 rmixl_puthex32(map->entry[i].type); 829 rmixl_puts("\r\n"); 830 } 831 #endif 832 } 833 834 /* 835 * mem_clusters_init 836 * 837 * initialize mem_clusters[] table based on memory address mapping 838 * provided by boot firmware. 839 * 840 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 841 * these will be limited by MEMSIZE if it is configured. 842 * if neither are available, just use MEMSIZE. 843 */ 844 static uint64_t 845 mem_clusters_init( 846 rmixlfw_mmap_t *psb_physaddr_map, 847 rmixlfw_mmap_t *avail_mem_map) 848 { 849 rmixlfw_mmap_t *map = NULL; 850 const char *mapname; 851 uint64_t sz; 852 uint64_t sum; 853 u_int cnt; 854 #ifdef MEMSIZE 855 uint64_t memsize = MEMSIZE; 856 #endif 857 858 #ifdef MACHDEP_DEBUG 859 rmixl_puts("psb_physaddr_map: "); 860 rmixl_puthex64((uint64_t)(intptr_t)psb_physaddr_map); 861 rmixl_puts("\r\n"); 862 #endif 863 if (psb_physaddr_map != NULL) { 864 map = psb_physaddr_map; 865 mapname = "psb_physaddr_map"; 866 rmixlfw_mmap_print(map); 867 } 868 #ifdef DIAGNOSTIC 869 else { 870 rmixl_puts("WARNING: no psb_physaddr_map\r\n"); 871 } 872 #endif 873 874 #ifdef MACHDEP_DEBUG 875 rmixl_puts("avail_mem_map: "); 876 rmixl_puthex64((uint64_t)(intptr_t)avail_mem_map); 877 rmixl_puts("\r\n"); 878 #endif 879 if (avail_mem_map != NULL) { 880 map = avail_mem_map; 881 mapname = "avail_mem_map"; 882 rmixlfw_mmap_print(map); 883 } 884 #ifdef DIAGNOSTIC 885 else { 886 rmixl_puts("WARNING: no avail_mem_map\r\n"); 887 } 888 #endif 889 890 if (map == NULL) { 891 #ifndef MEMSIZE 892 rmixl_puts("panic: no firmware memory map, " 893 "must configure MEMSIZE\r\n"); 894 for(;;); /* XXX */ 895 #else 896 #ifdef DIAGNOSTIC 897 rmixl_puts("WARNING: no avail_mem_map, " 898 "using MEMSIZE\r\n"); 899 #endif 900 901 mem_clusters[0].start = 0; 902 mem_clusters[0].size = MEMSIZE; 903 mem_cluster_cnt = 1; 904 return MEMSIZE; 905 #endif /* MEMSIZE */ 906 } 907 908 #ifdef DIAGNOSTIC 909 rmixl_puts("using "); 910 rmixl_puts(mapname); 911 rmixl_puts("\r\n"); 912 #endif 913 #ifdef MACHDEP_DEBUG 914 rmixl_puts("memory clusters:\r\n"); 915 #endif 916 sum = 0; 917 cnt = 0; 918 for (uint32_t i=0; i < map->nmmaps; i++) { 919 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 920 continue; 921 mem_clusters[cnt].start = map->entry[i].start; 922 sz = map->entry[i].size; 923 sum += sz; 924 mem_clusters[cnt].size = sz; 925 #ifdef MACHDEP_DEBUG 926 rmixl_puthex32(i); 927 rmixl_puts(": "); 928 rmixl_puthex64(mem_clusters[cnt].start); 929 rmixl_puts(", "); 930 rmixl_puthex64(sz); 931 rmixl_puts(": "); 932 rmixl_puthex64(sum); 933 rmixl_puts("\r\n"); 934 #endif 935 #ifdef MEMSIZE 936 /* 937 * configurably limit memsize 938 */ 939 if (sum == memsize) 940 break; 941 if (sum > memsize) { 942 uint64_t tmp; 943 944 tmp = sum - memsize; 945 sz -= tmp; 946 sum -= tmp; 947 mem_clusters[cnt].size = sz; 948 cnt++; 949 break; 950 } 951 #endif 952 cnt++; 953 } 954 mem_cluster_cnt = cnt; 955 return sum; 956 } 957 958 #ifdef MULTIPROCESSOR 959 /* 960 * RMI firmware passes wakeup info structure in CP0 OS Scratch reg #7 961 * they do not explicitly give us the size of the wakeup area. 962 * we "know" that firmware loader sets wip->gp thusly: 963 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 964 * so 965 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 966 * Only the "master" cpu runs this function, so 967 * vcpu = wip->master_cpu 968 */ 969 void 970 rmixl_get_wakeup_info(struct rmixl_config *rcp) 971 { 972 volatile rmixlfw_cpu_wakeup_info_t *wip; 973 int32_t scratch_7; 974 intptr_t end; 975 976 __asm__ volatile( 977 ".set push" "\n" 978 ".set noreorder" "\n" 979 ".set mips64" "\n" 980 "dmfc0 %0, $22, 7" "\n" 981 ".set pop" "\n" 982 : "=r"(scratch_7)); 983 984 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 985 (intptr_t)scratch_7; 986 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 987 988 if (wip->valid == 1) { 989 rcp->rc_cpu_wakeup_end = (const void *)end; 990 rcp->rc_cpu_wakeup_info = wip; 991 } 992 }; 993 994 #ifdef MACHDEP_DEBUG 995 static void 996 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 997 { 998 int i; 999 1000 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 1001 1002 printf("cpu_status %#x\n", wip->cpu_status); 1003 printf("valid: %d\n", wip->valid); 1004 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 1005 wip->entry.addr, 1006 wip->entry.args, 1007 wip->entry.sp, 1008 wip->entry.gp); 1009 printf("master_cpu %d\n", wip->master_cpu); 1010 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 1011 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 1012 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 1013 printf("argc %d\n", wip->argc); 1014 printf("argv:"); 1015 for (i=0; i < wip->argc; i++) 1016 printf(" %#x", wip->argv[i]); 1017 printf("\n"); 1018 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 1019 printf("tlb_map:\n"); 1020 for (i=0; i < wip->valid_tlb_entries; i++) { 1021 volatile const struct lib_cpu_tlb_mapping *m = 1022 &wip->tlb_map[i]; 1023 printf(" %d", m->page_size); 1024 printf(", %d", m->asid); 1025 printf(", %d", m->coherency); 1026 printf(", %d", m->coherency); 1027 printf(", %d", m->attr); 1028 printf(", %#x", m->virt); 1029 printf(", %#"PRIx64"\n", m->phys); 1030 } 1031 printf("elf segs:\n"); 1032 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 1033 volatile const struct core_segment_info *e = 1034 &wip->seg_info[i]; 1035 printf(" %#"PRIx64"", e->vaddr); 1036 printf(", %#"PRIx64"", e->memsz); 1037 printf(", %#x\n", e->flags); 1038 } 1039 printf("envc %d\n", wip->envc); 1040 for (i=0; i < wip->envc; i++) 1041 printf(" %#x \"%s\"", wip->envs[i], 1042 (char *)(intptr_t)(int32_t)(wip->envs[i])); 1043 printf("\n"); 1044 printf("app_mode %d\n", wip->app_mode); 1045 printf("printk_lock %#x\n", wip->printk_lock); 1046 printf("kseg_master %d\n", wip->kseg_master); 1047 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 1048 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 1049 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 1050 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 1051 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 1052 printf("loader_lock %#x\n", wip->loader_lock); 1053 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 1054 printf("unused_0 %#x\n", wip->unused_0); 1055 } 1056 #endif /* MACHDEP_DEBUG */ 1057 #endif /* MULTIPROCESSOR */ 1058 1059 void 1060 consinit(void) 1061 { 1062 1063 /* 1064 * Everything related to console initialization is done 1065 * in mach_init(). 1066 */ 1067 } 1068 1069 /* 1070 * Allocate memory for variable-sized tables, 1071 */ 1072 void 1073 cpu_startup() 1074 { 1075 vaddr_t minaddr, maxaddr; 1076 char pbuf[9]; 1077 1078 /* 1079 * Good {morning,afternoon,evening,night}. 1080 */ 1081 printf("%s%s", copyright, version); 1082 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 1083 printf("total memory = %s\n", pbuf); 1084 1085 /* 1086 * Virtual memory is bootstrapped -- notify the bus spaces 1087 * that memory allocation is now safe. 1088 */ 1089 rmixl_configuration.rc_mallocsafe = 1; 1090 1091 minaddr = 0; 1092 /* 1093 * Allocate a submap for physio. 1094 */ 1095 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 1096 VM_PHYS_SIZE, 0, FALSE, NULL); 1097 1098 /* 1099 * (No need to allocate an mbuf cluster submap. Mbuf clusters 1100 * are allocated via the pool allocator, and we use XKSEG to 1101 * map those pages.) 1102 */ 1103 1104 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 1105 printf("avail memory = %s\n", pbuf); 1106 } 1107 1108 int waittime = -1; 1109 1110 void 1111 cpu_reboot(int howto, char *bootstr) 1112 { 1113 1114 /* Take a snapshot before clobbering any registers. */ 1115 savectx(lwp_getpcb(curlwp)); 1116 1117 if (cold) { 1118 howto |= RB_HALT; 1119 goto haltsys; 1120 } 1121 1122 /* If "always halt" was specified as a boot flag, obey. */ 1123 if (boothowto & RB_HALT) 1124 howto |= RB_HALT; 1125 1126 boothowto = howto; 1127 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 1128 waittime = 0; 1129 vfs_shutdown(); 1130 1131 /* 1132 * If we've been adjusting the clock, the todr 1133 * will be out of synch; adjust it now. 1134 */ 1135 resettodr(); 1136 } 1137 1138 splhigh(); 1139 1140 if (howto & RB_DUMP) 1141 dumpsys(); 1142 1143 haltsys: 1144 doshutdownhooks(); 1145 1146 if (howto & RB_HALT) { 1147 printf("\n"); 1148 printf("The operating system has halted.\n"); 1149 printf("Please press any key to reboot.\n\n"); 1150 cnpollc(1); /* For proper keyboard command handling */ 1151 cngetc(); 1152 cnpollc(0); 1153 } 1154 1155 printf("rebooting...\n\n"); 1156 1157 rmixl_reset(); 1158 } 1159 1160 /* 1161 * goodbye world 1162 */ 1163 void __attribute__((__noreturn__)) 1164 rmixl_reset(void) 1165 { 1166 uint32_t r; 1167 1168 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1169 r |= RMIXL_GPIO_RESET_RESET; 1170 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1171 1172 printf("soft reset failed, spinning...\n"); 1173 for (;;); 1174 } 1175
Indexes created Fri Oct 31 11:10:07 GMT 2025