machdep.c revision 1.1.2.41
1 /* machdep.c,v 1.1.2.34 2011/04/29 08:26:18 matt Exp */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1988 University of Utah. 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * the Systems Programming Group of the University of Utah Computer 45 * Science Department, The Mach Operating System project at 46 * Carnegie-Mellon University and Ralph Campbell. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 73 * from: Utah Hdr: machdep.c 1.63 91/04/24 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "machdep.c,v 1.1.2.34 2011/04/29 08:26:18 matt Exp"); 78 79 #define __INTR_PRIVATE 80 #define __MUTEX_PRIVATE 81 #define _MIPS_BUS_DMA_PRIVATE 82 83 #include "opt_multiprocessor.h" 84 #include "opt_ddb.h" 85 #include "opt_com.h" 86 #include "opt_execfmt.h" 87 #include "opt_memsize.h" 88 #include "rmixl_pcix.h" 89 #include "rmixl_pcie.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/kernel.h> 94 #include <sys/buf.h> 95 #include <sys/reboot.h> 96 #include <sys/mount.h> 97 #include <sys/kcore.h> 98 #include <sys/boot_flag.h> 99 #include <sys/termios.h> 100 #include <sys/ksyms.h> 101 #include <sys/intr.h> 102 #include <sys/bus.h> 103 #include <sys/device.h> 104 #include <sys/extent.h> 105 #include <sys/malloc.h> 106 107 #include <uvm/uvm_extern.h> 108 109 #include <dev/cons.h> 110 111 #include "ksyms.h" 112 113 #if NKSYMS || defined(DDB) || defined(LKM) 114 #include <mips/db_machdep.h> 115 #include <ddb/db_extern.h> 116 #endif 117 118 #include <mips/cpu.h> 119 #include <mips/psl.h> 120 #include <mips/cache.h> 121 #include <mips/mipsNN.h> 122 #include <mips/mips_opcode.h> 123 #include <mips/pte.h> 124 125 #include "com.h" 126 #if NCOM == 0 127 #error no serial console 128 #endif 129 130 #include <dev/ic/comreg.h> 131 #include <dev/ic/comvar.h> 132 133 #include <dev/pci/pcireg.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/pciconf.h> 136 137 #include <mips/rmi/rmixlreg.h> 138 #include <mips/rmi/rmixlvar.h> 139 #include <mips/rmi/rmixl_intr.h> 140 #include <mips/rmi/rmixl_firmware.h> 141 #include <mips/rmi/rmixl_comvar.h> 142 #include <mips/rmi/rmixl_pcievar.h> 143 #include <mips/rmi/rmixl_pcixvar.h> 144 145 //#define MACHDEP_DEBUG 1 146 #ifdef MACHDEP_DEBUG 147 int machdep_debug=MACHDEP_DEBUG; 148 # define DPRINTF(x,...) do { if (machdep_debug) printf(x, ## __VA_ARGS__); } while(0) 149 #else 150 # define DPRINTF(x,...) 151 #endif 152 153 #ifdef __HAVE_PCI_CONF_HOOK 154 static int rmixl_pci_conf_hook(void *, int, int, int, pcireg_t); 155 #endif 156 157 #ifndef CONSFREQ 158 # define CONSFREQ 66000000 159 #endif 160 #ifndef CONSPEED 161 # define CONSPEED 38400 162 #endif 163 #ifndef CONMODE 164 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 165 #endif 166 #ifndef CONSADDR 167 # define CONSADDR 0 168 #endif 169 170 int comcnfreq = CONSFREQ; 171 int comcnspeed = CONSPEED; 172 tcflag_t comcnmode = CONMODE; 173 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 174 175 struct rmixl_config rmixl_configuration = { 176 .rc_io = { 177 .r_pbase = (bus_addr_t)-1, 178 }, 179 .rc_flash[0] = { 180 .r_pbase = (bus_addr_t)-1, 181 }, 182 .rc_flash[1] = { 183 .r_pbase = (bus_addr_t)-1, 184 }, 185 .rc_flash[2] = { 186 .r_pbase = (bus_addr_t)-1, 187 }, 188 .rc_flash[3] = { 189 .r_pbase = (bus_addr_t)-1, 190 }, 191 .rc_pci_cfg = { 192 .r_pbase = (bus_addr_t)-1, 193 }, 194 .rc_pci_ecfg = { 195 .r_pbase = (bus_addr_t)-1, 196 }, 197 .rc_pci_mem = { 198 .r_pbase = (bus_addr_t)-1, 199 }, 200 .rc_pci_io = { 201 .r_pbase = (bus_addr_t)-1, 202 }, 203 .rc_pci_link_mem[0] = { 204 .r_pbase = (bus_addr_t)-1, 205 }, 206 .rc_pci_link_mem[1] = { 207 .r_pbase = (bus_addr_t)-1, 208 }, 209 .rc_pci_link_mem[2] = { 210 .r_pbase = (bus_addr_t)-1, 211 }, 212 .rc_pci_link_mem[3] = { 213 .r_pbase = (bus_addr_t)-1, 214 }, 215 .rc_pci_link_io[0] = { 216 .r_pbase = (bus_addr_t)-1, 217 }, 218 .rc_pci_link_io[1] = { 219 .r_pbase = (bus_addr_t)-1, 220 }, 221 .rc_pci_link_io[2] = { 222 .r_pbase = (bus_addr_t)-1, 223 }, 224 .rc_pci_link_io[3] = { 225 .r_pbase = (bus_addr_t)-1, 226 }, 227 .rc_srio_mem = { 228 .r_pbase = (bus_addr_t)-1, 229 }, 230 /* 231 * Staticly initialize the 64-bit dmatag. 232 */ 233 .rc_dmat64 = &rmixl_configuration.rc_dma_tag, 234 .rc_dma_tag = { 235 ._cookie = &rmixl_configuration.rc_dma_tag, 236 ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER, 237 ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER, 238 ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER, 239 }, 240 #ifdef __HAVE_PCI_CONF_HOOK 241 .rc_pci_chipset = { 242 .pc_conf_hook = rmixl_pci_conf_hook, 243 } 244 #endif 245 }; 246 247 #ifdef ENABLE_MIPS_KSEGX 248 pt_entry_t mips_ksegx_pte; 249 paddr_t mips_ksegx_start; 250 #endif 251 252 /* 253 * array of tested firmware versions 254 * if you find new ones and they work 255 * please add them 256 */ 257 typedef struct rmiclfw_psb_id { 258 uint64_t psb_version; 259 rmixlfw_psb_type_t psb_type; 260 } rmiclfw_psb_id_t; 261 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 262 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 263 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 264 { 0x4b67d03200000056ULL, PSB_TYPE_RMI }, 265 { 0x4c17058b00000056ULL, PSB_TYPE_RMI }, 266 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 267 { 0x4b8ead3100000056ULL, PSB_TYPE_DELL }, 268 }; 269 #define RMICLFW_PSB_VERSIONS_LEN \ 270 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 271 272 /* 273 * storage for fixed extent used to allocate physical address regions 274 * because extent(9) start and end values are u_long, they are only 275 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 276 * address is 40 bits wide. So the "physaddr" map stores regions 277 * in units of megabytes. 278 */ 279 static u_long rmixl_physaddr_storage[ 280 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 281 ]; 282 283 /* For sysctl_hw. */ 284 extern char cpu_model[]; 285 286 /* Our exported CPU info; we can have only one. */ 287 struct cpu_info cpu_info_store; 288 289 /* Maps for VM objects. */ 290 struct vm_map *mb_map = NULL; 291 struct vm_map *phys_map = NULL; 292 293 int physmem; /* Total physical memory */ 294 295 int netboot; /* Are we netbooting? */ 296 297 298 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 299 u_quad_t mem_cluster_maxaddr; 300 u_int mem_cluster_cnt; 301 302 303 void configure(void); 304 void mach_init(int, int32_t *, void *, int64_t); 305 static uint64_t rmixlfw_init(int64_t); 306 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 307 static void __attribute__((__noreturn__)) rmixl_reset(void); 308 static uint64_t rmixl_physaddr_init(void); 309 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 310 void rmixlfw_mmap_print(const char *, rmixlfw_mmap_t *); 311 312 313 #ifdef MULTIPROCESSOR 314 static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2]); 315 void rmixl_get_wakeup_info(struct rmixl_config *); 316 #ifdef MACHDEP_DEBUG 317 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 318 #endif /* MACHDEP_DEBUG */ 319 #endif /* MULTIPROCESSOR */ 320 static void rmixl_fixup_curcpu(void); 321 322 #if NCOM > 0 323 static volatile uint32_t *rmixl_com0addr; 324 325 static int 326 rmixl_cngetc(dev_t dv) 327 { 328 volatile uint32_t * const com0addr = rmixl_com0addr; 329 330 if ((be32toh(com0addr[com_lsr]) & LSR_RXRDY) == 0) 331 return -1; 332 333 return be32toh(com0addr[com_data]) & 0xff; 334 } 335 336 static void 337 rmixl_cnputc(dev_t dv, int c) 338 { 339 volatile uint32_t * const com0addr = rmixl_com0addr; 340 int timo = 150000; 341 342 while ((be32toh(com0addr[com_lsr]) & LSR_TXRDY) == 0 && --timo > 0) 343 ; 344 345 com0addr[com_data] = htobe32(c); 346 __asm __volatile("sync"); 347 348 while ((be32toh(com0addr[com_lsr]) & LSR_TSRE) == 0 && --timo > 0) 349 ; 350 } 351 352 struct consdev rmixl_earlycons = { 353 .cn_putc = rmixl_cnputc, 354 .cn_getc = rmixl_cngetc, 355 .cn_pollc = nullcnpollc, 356 }; 357 #endif 358 359 /* 360 * Do all the stuff that locore normally does before calling main(). 361 */ 362 void 363 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 364 { 365 struct rmixl_config *rcp = &rmixl_configuration; 366 void *kernend; 367 uint64_t memsize; 368 extern char edata[], end[]; 369 size_t fl_count = 0; 370 struct mips_vmfreelist fl[1]; 371 bool uboot_p = false; 372 373 const uint32_t cfg0 = mips3_cp0_config_read(); 374 #if (MIPS64_XLR + MIPS64_XLS) > 0 && (MIPS64_XLP) == 0 375 const bool is_xlp_p = false /* make sure cfg0 is used */ 376 && MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2; 377 KASSERT(MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV1); 378 #elif (MIPS64_XLR + MIPS64_XLS) == 0 && (MIPS64_XLP) > 0 379 const bool is_xlp_p = true /* make sure cfg0 is used */ 380 || MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2; 381 KASSERT(MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2); 382 #else 383 const bool is_xlp_p = (MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2); 384 #endif 385 386 rmixl_pcr_init_core(is_xlp_p); 387 388 #ifdef MULTIPROCESSOR 389 __asm __volatile("dmtc0 %0,$%1,2" 390 :: "r"(&pmap_tlb0_info.ti_hwlock->mtx_lock), 391 "n"(MIPS_COP_0_OSSCRATCH)); 392 #endif 393 394 /* 395 * Clear the BSS segment. 396 */ 397 kernend = (void *)mips_round_page(end); 398 memset(edata, 0, (char *)kernend - edata); 399 400 #if NCOM > 0 401 /* 402 * If no comcnaddr has been set, pick an appropriate one. 403 */ 404 if (comcnaddr == 0) { 405 comcnaddr = is_xlp_p 406 ? RMIXLP_UART1_PCITAG 407 : RMIXL_IO_DEV_UART_1; 408 } 409 if (is_xlp_p) { 410 #if (MIPS64_XLP) > 0 411 rmixl_com0addr = 412 (void *)(vaddr_t)(RMIXLP_SBC_PCIE_ECFG_VBASE | comcnaddr | 0x100); 413 #endif /* MIPS64_XLP */ 414 } else { 415 #if (MIPS64_XLR + MIPS64_XLS) > 0 416 rcp->rc_io.r_pbase = RMIXL_IO_DEV_PBASE; 417 rmixl_com0addr = 418 (void *)(vaddr_t)(RMIXL_IO_DEV_VBASE | comcnaddr); 419 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 420 } 421 cn_tab = &rmixl_earlycons; 422 #endif 423 424 /* 425 * Set up the exception vectors and CPU-specific function 426 * vectors early on. We need the wbflush() vector set up 427 * before comcnattach() is called (or at least before the 428 * first printf() after that is called). 429 * Also clears the I+D caches. 430 * 431 * specify chip-specific EIRR/EIMR based spl functions 432 */ 433 #ifdef MULTIPROCESSOR 434 mips_vector_init(&rmixl_splsw, true); 435 #else 436 mips_vector_init(&rmixl_splsw, false); 437 #endif 438 439 if (argc < 0) { 440 void *bd = (void *)(intptr_t)argc; 441 void *imgaddr = argv; 442 void *consdev = envp; 443 char *bootargs = (void *)(intptr_t)infop; 444 printf("%s: u-boot: boardinfo=%p, image-addr=%p, consdev=%p, bootargs=%p <%s>\n", 445 __func__, bd, imgaddr, consdev, bootargs, bootargs); 446 uboot_p = true; 447 printf("%s: u-boot: console baudrate=%d\n", __func__, 448 *(int *)bd); 449 if (*(int *)bd % 1200 == 0) 450 comcnspeed = *(int *)bd; 451 } else { 452 DPRINTF("%s: argc=%d, argv=%p, envp=%p, info=%#"PRIx64"\n", 453 __func__, argc, argv, envp, infop); 454 } 455 456 /* mips_vector_init initialized mips_options */ 457 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 458 459 if (is_xlp_p) { 460 #if (MIPS64_XLP) > 0 461 uint32_t cfg6 = mipsNN_cp0_config6_read(); 462 printf("%s: cfg6=%#x " 463 "<ctlb=%u,vtlb=%u,elvt=%u,epw=%u,eft=%u,pwi=%u,fti=%u>\n", 464 __func__, cfg6, 465 MIPSNN_GET(RMIXLP_CFG6_CTLB_SIZE, cfg6), 466 MIPSNN_GET(RMIXLP_CFG6_VTLB_SIZE, cfg6), 467 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_ELVT), 468 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_EPW), 469 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_EFT), 470 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_PWI), 471 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_FTI)); 472 rcp->rc_pci_ecfg.r_pbase = RMIXLP_SBC_PCIE_ECFG_PBASE; 473 rcp->rc_pci_ecfg.r_size = RMIXLP_SBC_PCIE_ECFG_SIZE( 474 RMIXLP_SBC_PCIE_ECFG_PBASE, 475 RMIXLP_SBC_PCIE_ECFG_TO_PA( 476 rmixlp_read_4(RMIXLP_SBC_PCITAG, 477 RMIXLP_SBC_PCIE_ECFG_LIMIT))); 478 479 DPRINTF("%s: ecfg pbase=%#"PRIxBUSADDR" size=%#"PRIxBUSSIZE"\n", 480 __func__, rcp->rc_pci_ecfg.r_pbase, 481 rcp->rc_pci_ecfg.r_size); 482 483 rmixl_pci_ecfg_eb_bus_mem_init(&rcp->rc_pci_ecfg_eb_memt, rcp); 484 rmixl_pci_ecfg_el_bus_mem_init(&rcp->rc_pci_ecfg_el_memt, rcp); 485 rcp->rc_pci_ecfg_eb_memh = MIPS_PHYS_TO_KSEG1(rcp->rc_pci_ecfg.r_pbase); 486 rcp->rc_pci_ecfg_el_memh = rcp->rc_pci_ecfg_eb_memh; 487 DPRINTF("%s: pci ecfg bus space done!\n", __func__); 488 rmixlp_pcie_pc_init(); 489 DPRINTF("%s: pci chipset init done!\n", __func__); 490 #if NCOM > 0 491 comcnfreq = 133333333; 492 com_pci_cnattach(comcnaddr, comcnspeed, 493 comcnfreq, COM_TYPE_NORMAL, comcnmode); 494 DPRINTF("%s: com@pci console attached!\n", __func__); 495 #endif 496 #endif /* MIPS64_XLP */ 497 } 498 499 /* determine DRAM first */ 500 memsize = rmixl_physaddr_init(); 501 DPRINTF("%s: physaddr init done (memsize=%"PRIu64"MB)!\n", 502 __func__, memsize >> 20); 503 504 if (!uboot_p) { 505 /* get system info from firmware */ 506 memsize = rmixlfw_init(infop); 507 DPRINTF("%s: firmware init done (memsize=%"PRIu64"MB)!\n", 508 __func__, memsize >> 20); 509 } else { 510 rcp->rc_psb_info.userapp_cpu_map = 1; 511 } 512 513 /* set the VM page size */ 514 uvm_setpagesize(); 515 516 physmem = btoc(memsize); 517 518 if (!is_xlp_p) { 519 #if (MIPS64_XLR + MIPS64_XLS) > 0 520 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 521 #if NCOM > 0 522 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 523 COM_TYPE_NORMAL, comcnmode); 524 #endif 525 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 526 } 527 528 printf("\nNetBSD/rmixl\n"); 529 printf("memsize = %#"PRIx64"\n", memsize); 530 #ifdef MEMLIMIT 531 printf("memlimit = %#"PRIx64"\n", (uint64_t)MEMLIMIT); 532 #endif 533 534 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 535 if (!uboot_p) { 536 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 537 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 538 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 539 rcp->rc_cpu_wakeup_info, 540 rcp->rc_cpu_wakeup_end); 541 printf("userapp_cpu_map: %#"PRIx64"\n", 542 rcp->rc_psb_info.userapp_cpu_map); 543 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 544 } 545 { 546 register_t sp; 547 asm volatile ("move %0, $sp\n" : "=r"(sp)); 548 printf("sp: %#"PRIx64"\n", sp); 549 } 550 #endif 551 552 /* 553 * Obtain the cpu frequency 554 * Compute the number of ticks for hz. 555 * Compute the delay divisor. 556 * Double the Hz if this CPU runs at twice the 557 * external/cp0-count frequency 558 */ 559 if (uboot_p) { 560 /* 561 * Since u-boot doesn't tell us, we have to figure it out 562 */ 563 if (is_xlp_p) { 564 #if (MIPS64_XLP) > 0 565 uint32_t por_cfg = rmixlp_read_4(RMIXLP_SM_PCITAG, 566 RMIXLP_SM_POWER_ON_RESET_CFG); 567 u_int cdv = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDV) + 1; 568 u_int cdf = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDF) + 1; 569 u_int cdr = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDR) + 1; 570 u_int cpll_dfs = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CPLL_DFS) + 1; 571 572 uint64_t freq_in = 133333333; 573 uint64_t freq_out = (freq_in / cdr) * cdf / (cdv * cpll_dfs); 574 if (freq_out % 1000 > 900) { 575 freq_out = (freq_out + 99) / 100; 576 freq_out *= 100; 577 } 578 rcp->rc_psb_info.cpu_frequency = freq_out; 579 #endif /* MIPS64_XLP > 0 */ 580 } else { 581 #if (MIPS64_XLR + MIPS64_XLS) > 0 582 const uint32_t por_cfg = RMIXL_IOREG_READ( 583 RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 584 585 const u_int divq = __SHIFTOUT(por_cfg, 586 RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV); 587 const u_int divf = __SHIFTOUT(por_cfg, 588 RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV) + 1; 589 590 uint64_t freq_in = 66666666; 591 uint64_t freq_out = (freq_in / 4) * divf / divq; 592 593 if (freq_out % 1000 > 900) { 594 freq_out = (freq_out + 99) / 100; 595 freq_out *= 100; 596 } 597 rcp->rc_psb_info.cpu_frequency = freq_out; 598 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 599 } 600 } 601 DPRINTF("%s: cpu_freq=%"PRIu64"\n", __func__, 602 rcp->rc_psb_info.cpu_frequency); 603 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 604 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 605 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 606 curcpu()->ci_divisor_delay = 607 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 608 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 609 curcpu()->ci_cpu_freq *= 2; 610 611 /* 612 * Look at arguments passed to us and compute boothowto. 613 * - rmixl firmware gives us a 32 bit argv[i], so adapt 614 * by forcing sign extension in cast to (char *) 615 */ 616 boothowto = RB_AUTOBOOT; 617 // boothowto |= AB_VERBOSE; 618 if (!uboot_p) { 619 for (int i = 1; i < argc; i++) { 620 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 621 int howto; 622 /* Ignore superfluous '-', if there is one */ 623 if (*cp == '-') 624 continue; 625 626 howto = 0; 627 BOOT_FLAG(*cp, howto); 628 if (howto != 0) 629 boothowto |= howto; 630 #ifdef DIAGNOSTIC 631 else 632 printf("bootflag '%c' not recognised\n", 633 *cp); 634 #endif 635 } 636 } 637 } 638 #ifdef DIAGNOSTIC 639 printf("boothowto %#x\n", boothowto); 640 #endif 641 642 /* 643 * Reserve pages from the VM system. 644 */ 645 646 /* reserve 0..start..kernend pages */ 647 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 648 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 649 650 /* reserve reset exception vector page */ 651 /* should never be in our clusters anyway... */ 652 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 653 0x1FC00000, 0x1FC00000+NBPG); 654 655 /* Stop this abomination */ 656 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 657 0x18000000, 0x20000000); 658 659 #ifdef MULTIPROCESSOR 660 /* reserve the cpu_wakeup_info area */ 661 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 662 (u_quad_t)trunc_page((vaddr_t)rcp->rc_cpu_wakeup_info), 663 (u_quad_t)round_page((vaddr_t)rcp->rc_cpu_wakeup_end)); 664 #endif 665 666 #ifdef MEMLIMIT 667 /* reserve everything >= MEMLIMIT */ 668 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 669 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 670 #endif 671 672 #ifdef ENABLE_MIPS_KSEGX 673 /* 674 * Now we need to reserve an aligned block of memory for pre-init 675 * allocations so we don't deplete KSEG0. 676 */ 677 for (u_int i=0; i < mem_cluster_cnt; i++) { 678 u_quad_t finish = round_page( 679 mem_clusters[i].start + mem_clusters[i].size); 680 u_quad_t start = roundup2(mem_clusters[i].start, VM_KSEGX_SIZE); 681 if (start > MIPS_PHYS_MASK && start + VM_KSEGX_SIZE <= finish) { 682 mips_ksegx_start = start; 683 mips_ksegx_pte.pt_entry = mips_paddr_to_tlbpfn(start) 684 | MIPS3_PG_D | MIPS3_PG_CACHED 685 | MIPS3_PG_V | MIPS3_PG_G; 686 fl[0].fl_start = start; 687 fl[0].fl_end = start + VM_KSEGX_SIZE; 688 fl[0].fl_freelist = VM_FREELIST_FIRST512M; 689 fl_count++; 690 DPRINTF("mips_ksegx_start %#"PRIxPADDR"\n", 691 fl[0].fl_start); 692 break; 693 } 694 } 695 #endif 696 697 /* get maximum RAM address from the VM clusters */ 698 mem_cluster_maxaddr = 0; 699 for (u_int i=0; i < mem_cluster_cnt; i++) { 700 u_quad_t tmp = round_page( 701 mem_clusters[i].start + mem_clusters[i].size); 702 if (tmp > mem_cluster_maxaddr) 703 mem_cluster_maxaddr = tmp; 704 } 705 DPRINTF("mem_cluster_maxaddr %#"PRIx64"\n", mem_cluster_maxaddr); 706 707 /* 708 * Load mem_clusters[] into the VM system. 709 */ 710 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 711 mem_clusters, mem_cluster_cnt, fl, fl_count); 712 713 /* 714 * Initialize error message buffer (at end of core). 715 */ 716 mips_init_msgbuf(); 717 718 pmap_bootstrap(); 719 720 /* 721 * Allocate uarea page for lwp0 and set it. 722 */ 723 mips_init_lwp0_uarea(); 724 725 /* 726 * Initialize debuggers, and break into them, if appropriate. 727 */ 728 #if NKSYMS || defined(DDB) || defined(LKM) 729 ksyms_init(0, 0, 0); 730 #endif 731 732 #if defined(DDB) 733 if (boothowto & RB_KDB) 734 Debugger(); 735 #endif 736 /* 737 * store (cpu#0) curcpu in COP0 OSSCRATCH0 738 * used in exception vector 739 */ 740 __asm __volatile("dmtc0 %0,$%1" 741 :: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH)); 742 #ifdef MULTIPROCESSOR 743 mips_fixup_exceptions(rmixl_fixup_cop0_oscratch); 744 #endif 745 rmixl_fixup_curcpu(); 746 } 747 748 /* 749 * set up Processor Control Regs for this core 750 */ 751 void 752 rmixl_pcr_init_core(bool is_xlp_p) 753 { 754 uint32_t r; 755 756 757 if (is_xlp_p) { 758 #if (MIPS64_XLP) > 0 759 #ifndef MULTIPROCESSOR 760 rmixl_mtcr(RMIXLP_PCR_IFU_THREAD_EN, 1); 761 /* disable all threads except #0 */ 762 #endif 763 rmixl_mtcr(RMIXLP_PCR_MMU_SETUP, 1); 764 /* enable MMU clock gating */ 765 /* TLB is global */ 766 #ifdef MIPS_DISABLE_L1_CACHE 767 r = rmixl_mfcr(RMIXLP_PCR_L1D_CONFIG0); 768 r &= ~__BIT(0); /* disable L1D cache */ 769 rmixl_mtcr(RMIXLP_PCR_L1D_CONFIG0, r); 770 #endif 771 r = rmixl_mfcr(RMIXLP_PCR_LSU_DEFEATURE); 772 r &= ~RMIXLP_PCR_LSE_DEFEATURE_EUL; 773 rmixl_mtcr(RMIXLP_PCR_LSU_DEFEATURE, r); 774 775 /* 776 * Enable Large Variable TLB. 777 */ 778 uint32_t cfg6 = mipsNN_cp0_config6_read(); 779 cfg6 |= MIPSNN_RMIXLP_CFG6_ELVT; 780 mipsNN_cp0_config6_write(cfg6); 781 /* 782 * Force TLB Random to be rewritten. 783 */ 784 mips3_cp0_wired_write(0); 785 #endif /* MIPS64_XLP */ 786 } else { 787 #if (MIPS64_XLR + MIPS64_XLS) > 0 788 #ifdef MULTIPROCESSOR 789 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0)); 790 /* enable MMU clock gating */ 791 /* 4 threads active -- why needed if Global? */ 792 /* enable global TLB mode */ 793 #else 794 rmixl_mtcr(RMIXL_PCR_THREADEN, 1); 795 /* disable all threads except #0 */ 796 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, 0); 797 /* enable MMU clock gating */ 798 /* set single MMU Thread Mode */ 799 /* TLB is partitioned (1 partition) */ 800 #endif 801 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 802 r &= ~__BIT(14); /* disable Unaligned Access */ 803 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 804 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 805 } 806 807 #if defined(DDB) && defined(MIPS_DDB_WATCH) 808 /* 809 * clear IEU_DEFEATURE[DBE] 810 * this enables COP0 watchpoint to trigger T_WATCH exception 811 * instead of signaling JTAG. 812 */ 813 r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE); 814 r &= ~__BIT(7); 815 rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r); 816 #endif 817 } 818 819 #ifdef MULTIPROCESSOR 820 static bool 821 rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2]) 822 { 823 size_t offset = load_addr - (intptr_t)&cpu_info_store; 824 825 KASSERT(MIPS_KSEG0_P(load_addr)); 826 KASSERT(offset < sizeof(struct cpu_info)); 827 828 /* 829 * Fixup this direct load cpu_info_store to actually get the current 830 * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be 831 * relative from the start of struct cpu_info. 832 */ 833 834 /* [0] = [d]mfc0 rX, $22 (OSScratch) */ 835 new_insns[0] = (020 << 26) 836 #ifdef _LP64 837 | (1 << 21) /* double move */ 838 #endif 839 | (new_insns[0] & 0x001f0000) 840 | (MIPS_COP_0_OSSCRATCH << 11) | (0 << 0); 841 842 /* [1] = [ls][dw] rX, offset(rX) */ 843 new_insns[1] = (new_insns[1] & 0xffff0000) | offset; 844 845 return true; 846 } 847 #endif /* MULTIPROCESSOR */ 848 849 /* 850 * The following changes all lX rN, L_CPU(MIPS_CURLWP) [curlwp->l_cpu] 851 * to [d]mfc0 rN, $22 [MIPS_COP_0_OSSCRATCH] 852 * 853 * the mfc0 is 3 cycles shorter than the load. 854 */ 855 #define LOAD_CURCPU_0 ((MIPS_CURLWP_REG << 21) | offsetof(lwp_t, l_cpu)) 856 #define MFC0_CURCPU_0 ((OP_COP0 << 26) | (MIPS_COP_0_OSSCRATCH << 11)) 857 #ifdef _LP64 858 #define LOAD_CURCPU ((uint32_t)(OP_LD << 26) | LOAD_CURCPU_0) 859 #define MFC0_CURCPU ((uint32_t)(OP_DMF << 21) | MFC0_CURCPU_0) 860 #else 861 #define LOAD_CURCPU ((uint32_t)(OP_LW << 26) | LOAD_CURCPU_0) 862 #define MFC0_CURCPU ((uint32_t)(OP_MF << 21) | MFC0_CURCPU_0) 863 #endif 864 #define LOAD_CURCPU_MASK 0xffe0ffff 865 866 static void 867 rmixl_fixup_curcpu(void) 868 { 869 extern uint32_t _ftext[]; 870 extern uint32_t _etext[]; 871 872 for (uint32_t *insnp = _ftext; insnp < _etext; insnp++) { 873 const uint32_t insn = *insnp; 874 if (__predict_false((insn & LOAD_CURCPU_MASK) == LOAD_CURCPU)) { 875 /* 876 * Since the register to loaded is located in bits 877 * 16-20 for the mfc0 and the load instruction we can 878 * just change the instruction bits around it. 879 */ 880 *insnp = insn ^ LOAD_CURCPU ^ MFC0_CURCPU; 881 mips_icache_sync_range((vaddr_t)insnp, 4); 882 } 883 } 884 } 885 886 /* 887 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 888 * 889 * we simply build a new table of segs, then copy it back over the given one 890 * this is inefficient but simple and called only a few times 891 * 892 * note: 'last' here means 1st addr past the end of the segment (start+size) 893 */ 894 static u_int 895 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 896 u_quad_t resv_first, u_quad_t resv_last) 897 { 898 u_quad_t first, last; 899 int new_nsegs=0; 900 int resv_flag; 901 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 902 903 for (u_int i=0; i < nsegs; i++) { 904 resv_flag = 0; 905 first = trunc_page(segs[i].start); 906 last = round_page(segs[i].start + segs[i].size); 907 908 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 909 if ((resv_first <= first) && (resv_last >= last)) { 910 /* whole segment is resverved */ 911 continue; 912 } 913 if ((resv_first > first) && (resv_first < last)) { 914 u_quad_t new_last; 915 916 /* 917 * reserved start in segment 918 * salvage the leading fragment 919 */ 920 resv_flag = 1; 921 new_last = last - (last - resv_first); 922 KASSERT (new_last > first); 923 new_segs[new_nsegs].start = first; 924 new_segs[new_nsegs].size = new_last - first; 925 new_nsegs++; 926 } 927 if ((resv_last > first) && (resv_last < last)) { 928 u_quad_t new_first; 929 930 /* 931 * reserved end in segment 932 * salvage the trailing fragment 933 */ 934 resv_flag = 1; 935 new_first = first + (resv_last - first); 936 KASSERT (last > (new_first + NBPG)); 937 new_segs[new_nsegs].start = new_first; 938 new_segs[new_nsegs].size = last - new_first; 939 new_nsegs++; 940 } 941 if (resv_flag == 0) { 942 /* 943 * nothing reserved here, take it all 944 */ 945 new_segs[new_nsegs].start = first; 946 new_segs[new_nsegs].size = last - first; 947 new_nsegs++; 948 } 949 950 } 951 952 memcpy(segs, new_segs, sizeof(new_segs)); 953 954 return new_nsegs; 955 } 956 957 #if (MIPS64_XLP) > 0 958 static void 959 rmixlp_physaddr_pcie_cfg_init(struct extent *ext) 960 { 961 struct rmixl_config * const rcp = &rmixl_configuration; 962 963 uint64_t xbase = RMIXLP_SBC_PCIE_CFG_TO_PA( 964 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_CFG_BASE)); 965 uint64_t xlimit = RMIXLP_SBC_PCIE_CFG_TO_PA( 966 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_CFG_LIMIT)); 967 968 if (xlimit < xbase || xbase == 0) 969 return; /* not enabled */ 970 971 uint64_t xsize = RMIXLP_SBC_PCIE_CFG_SIZE(xbase, xlimit); 972 973 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 974 "pci-cfg", xbase, xsize >> 20); 975 976 rmixl_physaddr_add(ext, "pcicfg", &rcp->rc_pci_cfg, xbase, xsize); 977 } 978 979 static void 980 rmixlp_physaddr_pcie_ecfg_init(struct extent *ext) 981 { 982 struct rmixl_config * const rcp = &rmixl_configuration; 983 984 uint64_t xbase = RMIXLP_SBC_PCIE_ECFG_TO_PA( 985 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_ECFG_BASE)); 986 uint64_t xlimit = RMIXLP_SBC_PCIE_ECFG_TO_PA( 987 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_ECFG_LIMIT)); 988 989 if (xlimit < xbase || xbase == 0) 990 return; /* not enabled */ 991 992 uint64_t xsize = RMIXLP_SBC_PCIE_ECFG_SIZE(xbase, xlimit); 993 994 KASSERT(rcp->rc_pci_ecfg.r_pbase == xbase); 995 996 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 997 "pci-ecfg", xbase, xsize >> 20); 998 999 rmixl_physaddr_add(ext, "pciecfg", &rcp->rc_pci_ecfg, xbase, xsize); 1000 } 1001 1002 static void 1003 rmixlp_physaddr_pcie_mem_init(struct extent *ext) 1004 { 1005 struct rmixl_config * const rcp = &rmixl_configuration; 1006 for (size_t i = 0; i < RMIXLP_SBC_NPCIE_MEM; i++) { 1007 uint64_t xbase = RMIXLP_SBC_PCIE_MEM_TO_PA( 1008 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1009 RMIXLP_SBC_PCIE_MEM_BASEn(i))); 1010 uint64_t xlimit = RMIXLP_SBC_PCIE_MEM_TO_PA( 1011 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1012 RMIXLP_SBC_PCIE_MEM_LIMITn(i))); 1013 1014 if (xlimit < xbase || xbase == 0) 1015 continue; /* not enabled */ 1016 1017 uint64_t xsize = RMIXLP_SBC_PCIE_MEM_SIZE(xbase, xlimit); 1018 1019 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1020 "pci-mem", i, xbase, xsize >> 20); 1021 1022 rmixl_physaddr_add(ext, "pcimem", &rcp->rc_pci_link_mem[i], 1023 xbase, xsize); 1024 } 1025 } 1026 1027 static void 1028 rmixlp_physaddr_pcie_io_init(struct extent *ext) 1029 { 1030 struct rmixl_config * const rcp = &rmixl_configuration; 1031 for (size_t i = 0; i < RMIXLP_SBC_NPCIE_IO; i++) { 1032 uint64_t xbase = RMIXLP_SBC_PCIE_IO_TO_PA( 1033 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1034 RMIXLP_SBC_PCIE_IO_BASEn(i))); 1035 uint64_t xlimit = RMIXLP_SBC_PCIE_IO_TO_PA( 1036 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1037 RMIXLP_SBC_PCIE_IO_LIMITn(i))); 1038 1039 if (xlimit < xbase || xbase == 0) 1040 continue; /* not enabled */ 1041 1042 uint64_t xsize = RMIXLP_SBC_PCIE_IO_SIZE(xbase, xlimit); 1043 1044 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1045 "pci-io", i, xbase, xsize >> 20); 1046 1047 rmixl_physaddr_add(ext, "pci-io", &rcp->rc_pci_link_io[i], 1048 xbase, xsize); 1049 } 1050 } 1051 1052 static void 1053 rmixlp_physaddr_srio_mem_init(struct extent *ext) 1054 { 1055 struct rmixl_config * const rcp = &rmixl_configuration; 1056 uint64_t xbase = RMIXLP_SBC_SRIO_MEM_TO_PA( 1057 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_SRIO_MEM_BASE)); 1058 uint64_t xlimit = RMIXLP_SBC_SRIO_MEM_TO_PA( 1059 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_SRIO_MEM_LIMIT)); 1060 1061 if (xlimit < xbase || xbase == 0) 1062 return; /* not enabled */ 1063 1064 uint64_t xsize = RMIXLP_SBC_SRIO_MEM_SIZE(xbase, xlimit); 1065 1066 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 1067 "srio-mem", xbase, xsize >> 20); 1068 1069 rmixl_physaddr_add(ext, "sriomem", &rcp->rc_srio_mem, xbase, xsize); 1070 } 1071 1072 static void 1073 rmixlp_physaddr_nor_init(struct extent *ext) 1074 { 1075 struct rmixl_config * const rcp = &rmixl_configuration; 1076 for (size_t i = 0; i < RMIXLP_NOR_NCS; i++) { 1077 uint64_t xbase = RMIXLP_NOR_CS_ADDRESS_TO_PA( 1078 rmixlp_read_4(RMIXLP_NOR_PCITAG, 1079 RMIXLP_NOR_CS_BASEADDRESSn(i))); 1080 uint64_t xlimit = RMIXLP_NOR_CS_ADDRESS_TO_PA( 1081 rmixlp_read_4(RMIXLP_NOR_PCITAG, 1082 RMIXLP_NOR_CS_BASELIMITn(i))); 1083 1084 if (xlimit < xbase || xbase == 0) 1085 continue; /* not enabled */ 1086 1087 uint64_t xsize = RMIXLP_NOR_CS_SIZE(xbase, xlimit); 1088 1089 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1090 "nor", i, xbase, xsize >> 20); 1091 1092 rmixl_physaddr_add(ext, "nor", &rcp->rc_norflash[i], 1093 xbase, xsize); 1094 } 1095 } 1096 1097 static uint64_t 1098 rmixlp_physaddr_dram_init(struct extent *ext) 1099 { 1100 uint64_t memsize = 0; 1101 /* 1102 * grab regions per DRAM BARs 1103 */ 1104 phys_ram_seg_t *mp = mem_clusters; 1105 for (u_int i = 0; i < RMIXLP_SBC_NDRAM; i++) { 1106 uint64_t xbase = 1107 RMIXLP_SBC_DRAM_TO_PA( 1108 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1109 RMIXLP_SBC_DRAM_BASEn(i))); 1110 uint64_t xlimit = 1111 RMIXLP_SBC_DRAM_TO_PA( 1112 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1113 RMIXLP_SBC_DRAM_LIMITn(i))); 1114 1115 if (xlimit < xbase) 1116 continue; /* not enabled */ 1117 1118 mp->start = xbase; 1119 mp->size = RMIXLP_SBC_DRAM_SIZE(xbase, xlimit); 1120 1121 memsize += mp->size; 1122 1123 u_long base = mp->start >> 20; 1124 u_long size = mp->size >> 20; 1125 1126 mp++; 1127 1128 DPRINTF("%s: dram %u: 0x%05lx00000:%lu MB\n", 1129 __func__, i, base, size); 1130 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1131 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1132 "failed", __func__, ext, base, size, EX_NOWAIT); 1133 } 1134 1135 mem_cluster_cnt = mp - mem_clusters; 1136 return memsize; 1137 } 1138 #endif /* MIPS64_XLP */ 1139 1140 #if (MIPS64_XLR + MIPS64_XLS) > 0 1141 static uint64_t 1142 rmixl_physaddr_dram_init(struct extent *ext) 1143 { 1144 uint64_t memsize = 0; 1145 /* 1146 * grab regions per DRAM BARs 1147 */ 1148 phys_ram_seg_t *mp = mem_clusters; 1149 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 1150 uint32_t r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 1151 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 1152 continue; /* not enabled */ 1153 1154 mp->start = DRAM_BAR_TO_BASE((uint64_t)r); 1155 mp->size = DRAM_BAR_TO_SIZE((uint64_t)r); 1156 1157 u_long base = mp->start >> 20; 1158 u_long size = mp->size >> 20; 1159 1160 memsize += mp->size; 1161 1162 mp++; 1163 1164 DPRINTF("%s: dram %u: 0x%08x -- 0x%010lx:%lu MB\n", 1165 __func__, i, r, base * (1024 * 1024), size); 1166 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1167 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1168 "failed", __func__, ext, base, size, EX_NOWAIT); 1169 } 1170 1171 mem_cluster_cnt = mp - mem_clusters; 1172 1173 return memsize; 1174 } 1175 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1176 1177 /* 1178 * create an extent for physical address space 1179 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 1180 * allocate the regions where we have known functions (DRAM, IO, etc) 1181 * what remains can be allocated as needed for other stuff 1182 * e.g. to configure BARs that are not already initialized and enabled. 1183 */ 1184 static uint64_t 1185 rmixl_physaddr_init(void) 1186 { 1187 struct extent *ext; 1188 unsigned long start = 0UL; 1189 unsigned long end = (__BIT(40) / (1024 * 1024)) - 1; 1190 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1191 uint64_t memsize; 1192 1193 ext = extent_create("physaddr", start, end, M_DEVBUF, 1194 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 1195 EX_NOWAIT | EX_NOCOALESCE); 1196 1197 if (ext == NULL) 1198 panic("%s: extent_create failed", __func__); 1199 1200 if (is_xlp_p) { 1201 #if (MIPS64_XLP) > 0 1202 memsize = rmixlp_physaddr_dram_init(ext); 1203 rmixlp_physaddr_pcie_cfg_init(ext); 1204 rmixlp_physaddr_pcie_ecfg_init(ext); 1205 rmixlp_physaddr_pcie_mem_init(ext); 1206 rmixlp_physaddr_pcie_io_init(ext); 1207 rmixlp_physaddr_srio_mem_init(ext); 1208 rmixlp_physaddr_nor_init(ext); 1209 #else 1210 memsize = 0; 1211 #endif /* MIPS64_XLP */ 1212 } else { 1213 #if (MIPS64_XLR + MIPS64_XLS) > 0 1214 memsize = rmixl_physaddr_dram_init(ext); 1215 1216 /* 1217 * get chip-dependent physaddr regions 1218 */ 1219 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 1220 case CIDFL_RMI_TYPE_XLR: 1221 #if NRMIXL_PCIX 1222 rmixl_physaddr_init_pcix(ext); 1223 #endif 1224 break; 1225 case CIDFL_RMI_TYPE_XLS: 1226 #if NRMIXL_PCIE 1227 rmixl_physaddr_init_pcie(ext); 1228 #endif 1229 break; 1230 default: 1231 panic("%s: unknown chip type %d", __func__, 1232 cpu_rmixl_chip_type(mips_options.mips_cpu)); 1233 } 1234 #else 1235 memsize = 0; 1236 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1237 } 1238 1239 /* 1240 * at this point all regions left in "physaddr" extent 1241 * are unused holes in the physical adress space 1242 * available for use as needed. 1243 */ 1244 rmixl_configuration.rc_phys_ex = ext; 1245 #ifdef MACHDEP_DEBUG 1246 extent_print(ext); 1247 #endif 1248 return memsize; 1249 } 1250 1251 static uint64_t 1252 rmixlfw_init(int64_t infop) 1253 { 1254 struct rmixl_config * const rcp = &rmixl_configuration; 1255 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1256 1257 #ifdef MULTIPROCESSOR 1258 rmixl_get_wakeup_info(rcp); 1259 #endif 1260 1261 infop |= MIPS_KSEG0_START; 1262 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 1263 1264 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 1265 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 1266 if (rmiclfw_psb_id[i].psb_version == 1267 rcp->rc_psb_info.psb_version) { 1268 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 1269 goto found; 1270 } 1271 } 1272 1273 if (is_xlp_p) { 1274 #if (MIPS64_XLP) > 0 1275 rcp->rc_pci_ecfg.r_pbase = RMIXLP_SBC_PCIE_ECFG_PBASE; 1276 #endif /* MIPS64_XLP */ 1277 } else { 1278 #if (MIPS64_XLR + MIPS64_XLS) > 0 1279 rcp->rc_io.r_pbase = RMIXL_IO_DEV_PBASE; 1280 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1281 } 1282 1283 #ifdef DIAGNOSTIC 1284 printf("\nWARNING: untested psb_version: %#"PRIx64"\n", 1285 rcp->rc_psb_info.psb_version); 1286 #endif 1287 1288 #ifdef MEMSIZE 1289 /* XXX trust and use MEMSIZE */ 1290 mem_clusters[0].start = 0; 1291 mem_clusters[0].size = MEMSIZE; 1292 mem_cluster_cnt = 1; 1293 return MEMSIZE; 1294 #else 1295 uint64_t memsize = 0; 1296 for (size_t i = 0; i < mem_cluster_cnt; i++) { 1297 memsize += mem_clusters[i].size; 1298 } 1299 if (memsize) 1300 return memsize; 1301 1302 printf("\nERROR: configure MEMSIZE\n"); 1303 cpu_reboot(RB_HALT, NULL); 1304 /* NOTREACHED */ 1305 #endif 1306 1307 found: 1308 rcp->rc_io.r_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 1309 DPRINTF("\ninfop: %#"PRIx64"\n", infop); 1310 #ifdef DIAGNOSTIC 1311 printf("\nrecognized psb_version=%#"PRIx64", psb_type=%s\n", 1312 rcp->rc_psb_info.psb_version, 1313 rmixlfw_psb_type_name(rcp->rc_psb_type)); 1314 #endif 1315 1316 return mem_clusters_init( 1317 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 1318 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 1319 } 1320 1321 void 1322 rmixlfw_mmap_print(const char *mapname, rmixlfw_mmap_t *map) 1323 { 1324 #ifdef MACHDEP_DEBUG 1325 for (size_t i=0; i < map->nmmaps; i++) { 1326 printf("%s[%zu]: %#"PRIx64", %#"PRIx64", %#x\n", 1327 mapname, i, map->entry[i].start, map->entry[i].size, 1328 map->entry[i].type); 1329 } 1330 #endif 1331 } 1332 1333 /* 1334 * mem_clusters_init 1335 * 1336 * initialize mem_clusters[] table based on memory address mapping 1337 * provided by boot firmware. 1338 * 1339 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 1340 * these will be limited by MEMSIZE if it is configured. 1341 * if neither are available, just use MEMSIZE. 1342 */ 1343 static uint64_t 1344 mem_clusters_init( 1345 rmixlfw_mmap_t *psb_physaddr_map, 1346 rmixlfw_mmap_t *avail_mem_map) 1347 { 1348 rmixlfw_mmap_t *map = NULL; 1349 const char *mapname; 1350 uint64_t sz; 1351 uint64_t sum; 1352 u_int cnt; 1353 #ifdef MEMSIZE 1354 uint64_t memsize = MEMSIZE; 1355 #endif 1356 1357 #ifdef MACHDEP_DEBUG 1358 printf("psb_physaddr_map: %p\n", psb_physaddr_map); 1359 #endif 1360 if (psb_physaddr_map != NULL) { 1361 map = psb_physaddr_map; 1362 mapname = "psb_physaddr_map"; 1363 rmixlfw_mmap_print(mapname, map); 1364 } 1365 #ifdef DIAGNOSTIC 1366 else { 1367 printf("WARNING: no psb_physaddr_map\n"); 1368 } 1369 #endif 1370 1371 #ifdef MACHDEP_DEBUG 1372 printf("avail_mem_map: %p\n", avail_mem_map); 1373 #endif 1374 if (avail_mem_map != NULL) { 1375 map = avail_mem_map; 1376 mapname = "avail_mem_map"; 1377 rmixlfw_mmap_print(mapname, map); 1378 } 1379 #ifdef DIAGNOSTIC 1380 else { 1381 printf("WARNING: no avail_mem_map\n"); 1382 } 1383 #endif 1384 1385 if (map == NULL) { 1386 #ifndef MEMSIZE 1387 printf("panic: no firmware memory map, " 1388 "must configure MEMSIZE\r\n"); 1389 for(;;); /* XXX */ 1390 #else 1391 #ifdef DIAGNOSTIC 1392 printf("WARNING: no avail_mem_map, using MEMSIZE\n"); 1393 #endif 1394 1395 mem_clusters[0].start = 0; 1396 mem_clusters[0].size = MEMSIZE; 1397 mem_cluster_cnt = 1; 1398 return MEMSIZE; 1399 #endif /* MEMSIZE */ 1400 } 1401 1402 #ifdef DIAGNOSTIC 1403 printf("using %s\n", mapname); 1404 #endif 1405 #ifdef MACHDEP_DEBUG 1406 printf("memory clusters:\n"); 1407 #endif 1408 sum = 0; 1409 cnt = 0; 1410 for (uint32_t i=0; i < map->nmmaps; i++) { 1411 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 1412 continue; 1413 mem_clusters[cnt].start = map->entry[i].start; 1414 sz = map->entry[i].size; 1415 sum += sz; 1416 mem_clusters[cnt].size = sz; 1417 #ifdef MACHDEP_DEBUG 1418 printf("[%u]: %#"PRIx64", %#"PRIx64", %#"PRIx64"\n", 1419 i, mem_clusters[cnt].start, sz, sum); 1420 #endif 1421 #ifdef MEMSIZE 1422 /* 1423 * configurably limit memsize 1424 */ 1425 if (sum == memsize) 1426 break; 1427 if (sum > memsize) { 1428 uint64_t tmp; 1429 1430 tmp = sum - memsize; 1431 sz -= tmp; 1432 sum -= tmp; 1433 mem_clusters[cnt].size = sz; 1434 cnt++; 1435 break; 1436 } 1437 #endif 1438 cnt++; 1439 } 1440 mem_cluster_cnt = cnt; 1441 return sum; 1442 } 1443 1444 #ifdef MULTIPROCESSOR 1445 /* 1446 * RMI firmware passes wakeup info structure in CP0 OS Scratch reg #7 1447 * they do not explicitly give us the size of the wakeup area. 1448 * we "know" that firmware loader sets wip->gp thusly: 1449 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 1450 * so 1451 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 1452 * Only the "master" cpu runs this function, so 1453 * vcpu = wip->master_cpu 1454 */ 1455 void 1456 rmixl_get_wakeup_info(struct rmixl_config *rcp) 1457 { 1458 volatile rmixlfw_cpu_wakeup_info_t *wip; 1459 int32_t scratch_7; 1460 intptr_t end; 1461 1462 __asm__ volatile( 1463 ".set push" "\n" 1464 ".set noreorder" "\n" 1465 ".set mips64" "\n" 1466 "dmfc0 %0, $22, 7" "\n" 1467 ".set pop" "\n" 1468 : "=r"(scratch_7)); 1469 1470 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 1471 (intptr_t)scratch_7; 1472 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 1473 1474 if (wip->valid == 1) { 1475 rcp->rc_cpu_wakeup_end = (const void *)end; 1476 rcp->rc_cpu_wakeup_info = wip; 1477 } 1478 }; 1479 1480 #ifdef MACHDEP_DEBUG 1481 static void 1482 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 1483 { 1484 int i; 1485 1486 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 1487 1488 printf("cpu_status %#x\n", wip->cpu_status); 1489 printf("valid: %d\n", wip->valid); 1490 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 1491 wip->entry.addr, 1492 wip->entry.args, 1493 wip->entry.sp, 1494 wip->entry.gp); 1495 printf("master_cpu %d\n", wip->master_cpu); 1496 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 1497 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 1498 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 1499 printf("argc %d\n", wip->argc); 1500 printf("argv:"); 1501 for (i=0; i < wip->argc; i++) 1502 printf(" %#x", wip->argv[i]); 1503 printf("\n"); 1504 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 1505 printf("tlb_map:\n"); 1506 for (i=0; i < wip->valid_tlb_entries; i++) { 1507 volatile const struct lib_cpu_tlb_mapping *m = 1508 &wip->tlb_map[i]; 1509 printf(" %d", m->page_size); 1510 printf(", %d", m->asid); 1511 printf(", %d", m->coherency); 1512 printf(", %d", m->coherency); 1513 printf(", %d", m->attr); 1514 printf(", %#x", m->virt); 1515 printf(", %#"PRIx64"\n", m->phys); 1516 } 1517 printf("elf segs:\n"); 1518 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 1519 volatile const struct core_segment_info *e = 1520 &wip->seg_info[i]; 1521 printf(" %#"PRIx64"", e->vaddr); 1522 printf(", %#"PRIx64"", e->memsz); 1523 printf(", %#x\n", e->flags); 1524 } 1525 printf("envc %d\n", wip->envc); 1526 for (i=0; i < wip->envc; i++) 1527 printf(" %#x \"%s\"", wip->envs[i], 1528 (char *)(intptr_t)(int32_t)(wip->envs[i])); 1529 printf("\n"); 1530 printf("app_mode %d\n", wip->app_mode); 1531 printf("printk_lock %#x\n", wip->printk_lock); 1532 printf("kseg_master %d\n", wip->kseg_master); 1533 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 1534 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 1535 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 1536 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 1537 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 1538 printf("loader_lock %#x\n", wip->loader_lock); 1539 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 1540 printf("unused_0 %#x\n", wip->unused_0); 1541 } 1542 #endif /* MACHDEP_DEBUG */ 1543 #endif /* MULTIPROCESSOR */ 1544 1545 void 1546 consinit(void) 1547 { 1548 1549 /* 1550 * Everything related to console initialization is done 1551 * in mach_init(). 1552 */ 1553 } 1554 1555 /* 1556 * Allocate memory for variable-sized tables, 1557 */ 1558 void 1559 cpu_startup() 1560 { 1561 vaddr_t minaddr, maxaddr; 1562 char pbuf[9]; 1563 1564 /* 1565 * Good {morning,afternoon,evening,night}. 1566 */ 1567 printf("%s%s", copyright, version); 1568 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 1569 printf("total memory = %s\n", pbuf); 1570 1571 /* 1572 * Virtual memory is bootstrapped -- notify the bus spaces 1573 * that memory allocation is now safe. 1574 */ 1575 rmixl_configuration.rc_mallocsafe = 1; 1576 1577 minaddr = 0; 1578 /* 1579 * Allocate a submap for physio. 1580 */ 1581 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 1582 VM_PHYS_SIZE, 0, FALSE, NULL); 1583 1584 /* 1585 * (No need to allocate an mbuf cluster submap. Mbuf clusters 1586 * are allocated via the pool allocator, and we use XKSEG to 1587 * map those pages.) 1588 */ 1589 1590 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 1591 printf("avail memory = %s\n", pbuf); 1592 } 1593 1594 int waittime = -1; 1595 1596 void 1597 cpu_reboot(int howto, char *bootstr) 1598 { 1599 1600 /* Take a snapshot before clobbering any registers. */ 1601 savectx(lwp_getpcb(curlwp)); 1602 1603 if (cold) { 1604 howto |= RB_HALT; 1605 goto haltsys; 1606 } 1607 1608 /* If "always halt" was specified as a boot flag, obey. */ 1609 if (boothowto & RB_HALT) 1610 howto |= RB_HALT; 1611 1612 boothowto = howto; 1613 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 1614 waittime = 0; 1615 vfs_shutdown(); 1616 1617 /* 1618 * If we've been adjusting the clock, the todr 1619 * will be out of synch; adjust it now. 1620 */ 1621 resettodr(); 1622 } 1623 1624 splhigh(); 1625 1626 if (howto & RB_DUMP) 1627 dumpsys(); 1628 1629 haltsys: 1630 doshutdownhooks(); 1631 1632 if (howto & RB_HALT) { 1633 printf("\n"); 1634 printf("The operating system has halted.\n"); 1635 printf("Please press any key to reboot.\n\n"); 1636 cnpollc(1); /* For proper keyboard command handling */ 1637 cngetc(); 1638 cnpollc(0); 1639 } 1640 1641 printf("rebooting...\n\n"); 1642 1643 rmixl_reset(); 1644 } 1645 1646 /* 1647 * goodbye world 1648 */ 1649 void __attribute__((__noreturn__)) 1650 rmixl_reset(void) 1651 { 1652 uint32_t r; 1653 1654 if (MIPSNN_GET(CFG_AR, mips3_cp0_config_read()) == MIPSNN_CFG_AR_REV2) { 1655 rmixlp_write_4(RMIXLP_SM_PCITAG, RMIXLP_SM_CHIP_RESET, 1); 1656 DELAY(1000000); 1657 printf("%s: resorting to plan b!", __func__); 1658 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x18035100) = 1; 1659 __asm __volatile("sync"); 1660 } else { 1661 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1662 r |= RMIXL_GPIO_RESET_RESET; 1663 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1664 } 1665 1666 printf("soft reset failed, spinning...\n"); 1667 for (;;); 1668 } 1669 1670 #ifdef __HAVE_PCI_CONF_HOOK 1671 int 1672 rmixl_pci_conf_hook(void *v, int bus, int device, int function, pcireg_t id) 1673 { 1674 return PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM; 1675 } 1676 #endif 1677
Indexes created Fri Oct 31 11:10:07 GMT 2025