machdep.c revision 1.1.2.42
1 /* machdep.c,v 1.1.2.34 2011/04/29 08:26:18 matt Exp */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1988 University of Utah. 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * the Systems Programming Group of the University of Utah Computer 45 * Science Department, The Mach Operating System project at 46 * Carnegie-Mellon University and Ralph Campbell. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 73 * from: Utah Hdr: machdep.c 1.63 91/04/24 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "machdep.c,v 1.1.2.34 2011/04/29 08:26:18 matt Exp"); 78 79 #define __INTR_PRIVATE 80 #define __MUTEX_PRIVATE 81 #define _MIPS_BUS_DMA_PRIVATE 82 83 #include "opt_multiprocessor.h" 84 #include "opt_ddb.h" 85 #include "opt_com.h" 86 #include "opt_execfmt.h" 87 #include "opt_memsize.h" 88 #include "rmixl_pcix.h" 89 #include "rmixl_pcie.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/kernel.h> 94 #include <sys/buf.h> 95 #include <sys/reboot.h> 96 #include <sys/mount.h> 97 #include <sys/kcore.h> 98 #include <sys/boot_flag.h> 99 #include <sys/termios.h> 100 #include <sys/ksyms.h> 101 #include <sys/intr.h> 102 #include <sys/bus.h> 103 #include <sys/device.h> 104 #include <sys/extent.h> 105 #include <sys/malloc.h> 106 107 #include <uvm/uvm_extern.h> 108 109 #include <dev/cons.h> 110 111 #include "ksyms.h" 112 113 #if NKSYMS || defined(DDB) || defined(LKM) 114 #include <mips/db_machdep.h> 115 #include <ddb/db_extern.h> 116 #endif 117 118 #include <mips/cpu.h> 119 #include <mips/psl.h> 120 #include <mips/cache.h> 121 #include <mips/mipsNN.h> 122 #include <mips/mips_opcode.h> 123 #include <mips/pte.h> 124 125 #include "com.h" 126 #if NCOM == 0 127 #error no serial console 128 #endif 129 130 #include <dev/ic/comreg.h> 131 #include <dev/ic/comvar.h> 132 133 #include <dev/pci/pcireg.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/pciconf.h> 136 137 #include <mips/rmi/rmixlreg.h> 138 #include <mips/rmi/rmixlvar.h> 139 #include <mips/rmi/rmixl_intr.h> 140 #include <mips/rmi/rmixl_firmware.h> 141 #include <mips/rmi/rmixl_comvar.h> 142 #include <mips/rmi/rmixl_pcievar.h> 143 #include <mips/rmi/rmixl_pcixvar.h> 144 145 //#define MACHDEP_DEBUG 1 146 #ifdef MACHDEP_DEBUG 147 int machdep_debug=MACHDEP_DEBUG; 148 # define DPRINTF(x,...) do { if (machdep_debug) printf(x, ## __VA_ARGS__); } while(0) 149 #else 150 # define DPRINTF(x,...) 151 #endif 152 153 #ifdef __HAVE_PCI_CONF_HOOK 154 static int rmixl_pci_conf_hook(void *, int, int, int, pcireg_t); 155 #endif 156 157 #ifndef CONSFREQ 158 # define CONSFREQ 66000000 159 #endif 160 #ifndef CONSPEED 161 # define CONSPEED 38400 162 #endif 163 #ifndef CONMODE 164 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 165 #endif 166 #ifndef CONSADDR 167 # define CONSADDR 0 168 #endif 169 170 int comcnfreq = CONSFREQ; 171 int comcnspeed = CONSPEED; 172 tcflag_t comcnmode = CONMODE; 173 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 174 175 struct rmixl_config rmixl_configuration = { 176 .rc_io = { 177 .r_pbase = (bus_addr_t)-1, 178 }, 179 .rc_flash[0] = { 180 .r_pbase = (bus_addr_t)-1, 181 }, 182 .rc_flash[1] = { 183 .r_pbase = (bus_addr_t)-1, 184 }, 185 .rc_flash[2] = { 186 .r_pbase = (bus_addr_t)-1, 187 }, 188 .rc_flash[3] = { 189 .r_pbase = (bus_addr_t)-1, 190 }, 191 .rc_pci_cfg = { 192 .r_pbase = (bus_addr_t)-1, 193 }, 194 .rc_pci_ecfg = { 195 .r_pbase = (bus_addr_t)-1, 196 }, 197 .rc_pci_mem = { 198 .r_pbase = (bus_addr_t)-1, 199 }, 200 .rc_pci_io = { 201 .r_pbase = (bus_addr_t)-1, 202 }, 203 .rc_pci_link_mem[0] = { 204 .r_pbase = (bus_addr_t)-1, 205 }, 206 .rc_pci_link_mem[1] = { 207 .r_pbase = (bus_addr_t)-1, 208 }, 209 .rc_pci_link_mem[2] = { 210 .r_pbase = (bus_addr_t)-1, 211 }, 212 .rc_pci_link_mem[3] = { 213 .r_pbase = (bus_addr_t)-1, 214 }, 215 .rc_pci_link_io[0] = { 216 .r_pbase = (bus_addr_t)-1, 217 }, 218 .rc_pci_link_io[1] = { 219 .r_pbase = (bus_addr_t)-1, 220 }, 221 .rc_pci_link_io[2] = { 222 .r_pbase = (bus_addr_t)-1, 223 }, 224 .rc_pci_link_io[3] = { 225 .r_pbase = (bus_addr_t)-1, 226 }, 227 .rc_srio_mem = { 228 .r_pbase = (bus_addr_t)-1, 229 }, 230 /* 231 * Staticly initialize the 64-bit dmatag. 232 */ 233 .rc_dmat64 = &rmixl_configuration.rc_dma_tag, 234 .rc_dma_tag = { 235 ._cookie = &rmixl_configuration.rc_dma_tag, 236 ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER, 237 ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER, 238 ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER, 239 }, 240 #ifdef __HAVE_PCI_CONF_HOOK 241 .rc_pci_chipset = { 242 .pc_conf_hook = rmixl_pci_conf_hook, 243 } 244 #endif 245 }; 246 247 #ifdef ENABLE_MIPS_KSEGX 248 pt_entry_t mips_ksegx_pte; 249 paddr_t mips_ksegx_start; 250 #endif 251 252 /* 253 * array of tested firmware versions 254 * if you find new ones and they work 255 * please add them 256 */ 257 typedef struct rmiclfw_psb_id { 258 uint64_t psb_version; 259 rmixlfw_psb_type_t psb_type; 260 } rmiclfw_psb_id_t; 261 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 262 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 263 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 264 { 0x4b67d03200000056ULL, PSB_TYPE_RMI }, 265 { 0x4c17058b00000056ULL, PSB_TYPE_RMI }, 266 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 267 { 0x4b8ead3100000056ULL, PSB_TYPE_DELL }, 268 }; 269 #define RMICLFW_PSB_VERSIONS_LEN \ 270 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 271 272 /* 273 * storage for fixed extent used to allocate physical address regions 274 * because extent(9) start and end values are u_long, they are only 275 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 276 * address is 40 bits wide. So the "physaddr" map stores regions 277 * in units of megabytes. 278 */ 279 static u_long rmixl_physaddr_storage[ 280 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 281 ]; 282 283 /* For sysctl_hw. */ 284 extern char cpu_model[]; 285 286 /* Our exported CPU info; we can have only one. */ 287 struct cpu_info cpu_info_store; 288 289 /* Maps for VM objects. */ 290 struct vm_map *mb_map = NULL; 291 struct vm_map *phys_map = NULL; 292 293 int physmem; /* Total physical memory */ 294 295 int netboot; /* Are we netbooting? */ 296 297 298 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 299 u_quad_t mem_cluster_maxaddr; 300 u_int mem_cluster_cnt; 301 302 303 void configure(void); 304 void mach_init(int, int32_t *, void *, int64_t); 305 static uint64_t rmixlfw_init(int64_t); 306 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 307 static void __attribute__((__noreturn__)) rmixl_reset(void); 308 static uint64_t rmixl_physaddr_init(void); 309 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 310 void rmixlfw_mmap_print(const char *, rmixlfw_mmap_t *); 311 312 313 #ifdef MULTIPROCESSOR 314 static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2]); 315 void rmixl_get_wakeup_info(struct rmixl_config *); 316 #ifdef MACHDEP_DEBUG 317 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 318 #endif /* MACHDEP_DEBUG */ 319 #endif /* MULTIPROCESSOR */ 320 static void rmixl_fixup_curcpu(void); 321 322 #if NCOM > 0 323 static volatile uint32_t *rmixl_com0addr; 324 325 static int 326 rmixl_cngetc(dev_t dv) 327 { 328 volatile uint32_t * const com0addr = rmixl_com0addr; 329 330 if ((be32toh(com0addr[com_lsr]) & LSR_RXRDY) == 0) 331 return -1; 332 333 return be32toh(com0addr[com_data]) & 0xff; 334 } 335 336 static void 337 rmixl_cnputc(dev_t dv, int c) 338 { 339 volatile uint32_t * const com0addr = rmixl_com0addr; 340 int timo = 150000; 341 342 while ((be32toh(com0addr[com_lsr]) & LSR_TXRDY) == 0 && --timo > 0) 343 ; 344 345 com0addr[com_data] = htobe32(c); 346 __asm __volatile("sync"); 347 348 while ((be32toh(com0addr[com_lsr]) & LSR_TSRE) == 0 && --timo > 0) 349 ; 350 } 351 352 struct consdev rmixl_earlycons = { 353 .cn_putc = rmixl_cnputc, 354 .cn_getc = rmixl_cngetc, 355 .cn_pollc = nullcnpollc, 356 }; 357 #endif 358 359 /* 360 * Do all the stuff that locore normally does before calling main(). 361 */ 362 void 363 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 364 { 365 struct rmixl_config *rcp = &rmixl_configuration; 366 void *kernend; 367 uint64_t memsize; 368 extern char edata[], end[]; 369 size_t fl_count = 0; 370 struct mips_vmfreelist fl[1]; 371 bool uboot_p = false; 372 373 const uint32_t cfg0 = mips3_cp0_config_read(); 374 #if (MIPS64_XLR + MIPS64_XLS) > 0 && (MIPS64_XLP) == 0 375 const bool is_xlp_p = false /* make sure cfg0 is used */ 376 && MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2; 377 KASSERT(MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV1); 378 #elif (MIPS64_XLR + MIPS64_XLS) == 0 && (MIPS64_XLP) > 0 379 const bool is_xlp_p = true /* make sure cfg0 is used */ 380 || MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2; 381 KASSERT(MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2); 382 #else 383 const bool is_xlp_p = (MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2); 384 #endif 385 386 rmixl_pcr_init_core(is_xlp_p); 387 388 #ifdef MULTIPROCESSOR 389 __asm __volatile("dmtc0 %0,$%1,2" 390 :: "r"(&pmap_tlb0_info.ti_hwlock->mtx_lock), 391 "n"(MIPS_COP_0_OSSCRATCH)); 392 #endif 393 394 /* 395 * Clear the BSS segment. 396 */ 397 kernend = (void *)mips_round_page(end); 398 memset(edata, 0, (char *)kernend - edata); 399 400 #if NCOM > 0 401 /* 402 * If no comcnaddr has been set, pick an appropriate one. 403 */ 404 if (comcnaddr == 0) { 405 comcnaddr = is_xlp_p 406 ? RMIXLP_UART1_PCITAG 407 : RMIXL_IO_DEV_UART_1; 408 } 409 if (is_xlp_p) { 410 #if (MIPS64_XLP) > 0 411 rmixl_com0addr = 412 (void *)(vaddr_t)(RMIXLP_SBC_PCIE_ECFG_VBASE | comcnaddr | 0x100); 413 #endif /* MIPS64_XLP */ 414 } else { 415 #if (MIPS64_XLR + MIPS64_XLS) > 0 416 rcp->rc_io.r_pbase = RMIXL_IO_DEV_PBASE; 417 rmixl_com0addr = 418 (void *)(vaddr_t)(RMIXL_IO_DEV_VBASE | comcnaddr); 419 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 420 } 421 cn_tab = &rmixl_earlycons; 422 #endif 423 424 /* 425 * Set up the exception vectors and CPU-specific function 426 * vectors early on. We need the wbflush() vector set up 427 * before comcnattach() is called (or at least before the 428 * first printf() after that is called). 429 * Also clears the I+D caches. 430 * 431 * specify chip-specific EIRR/EIMR based spl functions 432 */ 433 #ifdef MULTIPROCESSOR 434 mips_vector_init(&rmixl_splsw, true); 435 #else 436 mips_vector_init(&rmixl_splsw, false); 437 #endif 438 439 if (argc < 0) { 440 void *bd = (void *)(intptr_t)argc; 441 void *imgaddr = argv; 442 void *consdev = envp; 443 char *bootargs = (void *)(intptr_t)infop; 444 printf("%s: u-boot: boardinfo=%p, image-addr=%p, consdev=%p, bootargs=%p <%s>\n", 445 __func__, bd, imgaddr, consdev, bootargs, bootargs); 446 uboot_p = true; 447 printf("%s: u-boot: console baudrate=%d\n", __func__, 448 *(int *)bd); 449 if (*(int *)bd % 1200 == 0) 450 comcnspeed = *(int *)bd; 451 } else { 452 DPRINTF("%s: argc=%d, argv=%p, envp=%p, info=%#"PRIx64"\n", 453 __func__, argc, argv, envp, infop); 454 } 455 456 /* mips_vector_init initialized mips_options */ 457 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 458 459 if (is_xlp_p) { 460 #if (MIPS64_XLP) > 0 461 uint32_t cfg6 = mipsNN_cp0_config6_read(); 462 printf("%s: cfg6=%#x " 463 "<ctlb=%u,vtlb=%u,elvt=%u,epw=%u,eft=%u,pwi=%u,fti=%u>\n", 464 __func__, cfg6, 465 MIPSNN_GET(RMIXLP_CFG6_CTLB_SIZE, cfg6), 466 MIPSNN_GET(RMIXLP_CFG6_VTLB_SIZE, cfg6), 467 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_ELVT), 468 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_EPW), 469 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_EFT), 470 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_PWI), 471 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_FTI)); 472 rcp->rc_pci_ecfg.r_pbase = RMIXLP_SBC_PCIE_ECFG_PBASE; 473 rcp->rc_pci_ecfg.r_size = RMIXLP_SBC_PCIE_ECFG_SIZE( 474 RMIXLP_SBC_PCIE_ECFG_PBASE, 475 RMIXLP_SBC_PCIE_ECFG_TO_PA( 476 rmixlp_read_4(RMIXLP_SBC_PCITAG, 477 RMIXLP_SBC_PCIE_ECFG_LIMIT))); 478 479 DPRINTF("%s: ecfg pbase=%#"PRIxBUSADDR" size=%#"PRIxBUSSIZE"\n", 480 __func__, rcp->rc_pci_ecfg.r_pbase, 481 rcp->rc_pci_ecfg.r_size); 482 483 rmixl_pci_ecfg_eb_bus_mem_init(&rcp->rc_pci_ecfg_eb_memt, rcp); 484 rmixl_pci_ecfg_el_bus_mem_init(&rcp->rc_pci_ecfg_el_memt, rcp); 485 rcp->rc_pci_ecfg_eb_memh = MIPS_PHYS_TO_KSEG1(rcp->rc_pci_ecfg.r_pbase); 486 rcp->rc_pci_ecfg_el_memh = rcp->rc_pci_ecfg_eb_memh; 487 DPRINTF("%s: pci ecfg bus space done!\n", __func__); 488 rmixlp_pcie_pc_init(); 489 DPRINTF("%s: pci chipset init done!\n", __func__); 490 #if NCOM > 0 491 comcnfreq = 133333333; 492 com_pci_cnattach(comcnaddr, comcnspeed, 493 comcnfreq, COM_TYPE_NORMAL, comcnmode); 494 DPRINTF("%s: com@pci console attached!\n", __func__); 495 #endif 496 #endif /* MIPS64_XLP */ 497 } 498 499 /* determine DRAM first */ 500 memsize = rmixl_physaddr_init(); 501 DPRINTF("%s: physaddr init done (memsize=%"PRIu64"MB)!\n", 502 __func__, memsize >> 20); 503 504 if (!uboot_p) { 505 /* get system info from firmware */ 506 memsize = rmixlfw_init(infop); 507 DPRINTF("%s: firmware init done (memsize=%"PRIu64"MB)!\n", 508 __func__, memsize >> 20); 509 } else { 510 rcp->rc_psb_info.userapp_cpu_map = 1; 511 } 512 513 /* set the VM page size */ 514 uvm_setpagesize(); 515 516 physmem = btoc(memsize); 517 518 if (!is_xlp_p) { 519 #if (MIPS64_XLR + MIPS64_XLS) > 0 520 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 521 #if NCOM > 0 522 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 523 COM_TYPE_NORMAL, comcnmode); 524 #endif 525 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 526 } 527 528 printf("\nNetBSD/rmixl\n"); 529 printf("memsize = %#"PRIx64"\n", memsize); 530 #ifdef MEMLIMIT 531 printf("memlimit = %#"PRIx64"\n", (uint64_t)MEMLIMIT); 532 #endif 533 534 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 535 if (!uboot_p) { 536 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 537 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 538 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 539 rcp->rc_cpu_wakeup_info, 540 rcp->rc_cpu_wakeup_end); 541 printf("userapp_cpu_map: %#"PRIx64"\n", 542 rcp->rc_psb_info.userapp_cpu_map); 543 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 544 } 545 { 546 register_t sp; 547 asm volatile ("move %0, $sp\n" : "=r"(sp)); 548 printf("sp: %#"PRIx64"\n", sp); 549 } 550 #endif 551 552 /* 553 * Obtain the cpu frequency 554 * Compute the number of ticks for hz. 555 * Compute the delay divisor. 556 * Double the Hz if this CPU runs at twice the 557 * external/cp0-count frequency 558 */ 559 if (uboot_p) { 560 /* 561 * Since u-boot doesn't tell us, we have to figure it out 562 */ 563 if (is_xlp_p) { 564 #if (MIPS64_XLP) > 0 565 uint32_t por_cfg = rmixlp_read_4(RMIXLP_SM_PCITAG, 566 RMIXLP_SM_POWER_ON_RESET_CFG); 567 u_int cdv = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDV) + 1; 568 u_int cdf = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDF) + 1; 569 u_int cdr = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDR) + 1; 570 u_int cpll_dfs = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CPLL_DFS) + 1; 571 572 uint64_t freq_in = 133333333; 573 uint64_t freq_out = (freq_in / cdr) * cdf / (cdv * cpll_dfs); 574 if (freq_out % 1000 > 900) { 575 freq_out = (freq_out + 99) / 100; 576 freq_out *= 100; 577 } 578 rcp->rc_psb_info.cpu_frequency = freq_out; 579 #endif /* MIPS64_XLP > 0 */ 580 } else { 581 #if (MIPS64_XLR + MIPS64_XLS) > 0 582 const uint32_t por_cfg = RMIXL_IOREG_READ( 583 RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 584 585 const u_int divq = __SHIFTOUT(por_cfg, 586 RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV); 587 const u_int divf = __SHIFTOUT(por_cfg, 588 RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV) + 1; 589 590 uint64_t freq_in = 66666666; 591 uint64_t freq_out = (freq_in / 4) * divf / divq; 592 593 if (freq_out % 1000 > 900) { 594 freq_out = (freq_out + 99) / 100; 595 freq_out *= 100; 596 } 597 rcp->rc_psb_info.cpu_frequency = freq_out; 598 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 599 } 600 } 601 DPRINTF("%s: cpu_freq=%"PRIu64"\n", __func__, 602 rcp->rc_psb_info.cpu_frequency); 603 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 604 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 605 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 606 curcpu()->ci_divisor_delay = 607 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 608 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 609 curcpu()->ci_cpu_freq *= 2; 610 611 /* 612 * Look at arguments passed to us and compute boothowto. 613 * - rmixl firmware gives us a 32 bit argv[i], so adapt 614 * by forcing sign extension in cast to (char *) 615 */ 616 boothowto = RB_AUTOBOOT; 617 // boothowto |= AB_VERBOSE; 618 // boothowto |= AB_DEBUG; 619 if (!uboot_p) { 620 for (int i = 1; i < argc; i++) { 621 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 622 int howto; 623 /* Ignore superfluous '-', if there is one */ 624 if (*cp == '-') 625 continue; 626 627 howto = 0; 628 BOOT_FLAG(*cp, howto); 629 if (howto != 0) 630 boothowto |= howto; 631 #ifdef DIAGNOSTIC 632 else 633 printf("bootflag '%c' not recognised\n", 634 *cp); 635 #endif 636 } 637 } 638 } 639 #ifdef DIAGNOSTIC 640 printf("boothowto %#x\n", boothowto); 641 #endif 642 643 /* 644 * Reserve pages from the VM system. 645 */ 646 647 /* reserve 0..start..kernend pages */ 648 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 649 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 650 651 /* reserve reset exception vector page */ 652 /* should never be in our clusters anyway... */ 653 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 654 0x1FC00000, 0x1FC00000+NBPG); 655 656 /* Stop this abomination */ 657 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 658 0x18000000, 0x20000000); 659 660 #ifdef MULTIPROCESSOR 661 /* reserve the cpu_wakeup_info area */ 662 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 663 (u_quad_t)trunc_page((vaddr_t)rcp->rc_cpu_wakeup_info), 664 (u_quad_t)round_page((vaddr_t)rcp->rc_cpu_wakeup_end)); 665 #endif 666 667 #ifdef MEMLIMIT 668 /* reserve everything >= MEMLIMIT */ 669 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 670 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 671 #endif 672 673 #ifdef ENABLE_MIPS_KSEGX 674 /* 675 * Now we need to reserve an aligned block of memory for pre-init 676 * allocations so we don't deplete KSEG0. 677 */ 678 for (u_int i=0; i < mem_cluster_cnt; i++) { 679 u_quad_t finish = round_page( 680 mem_clusters[i].start + mem_clusters[i].size); 681 u_quad_t start = roundup2(mem_clusters[i].start, VM_KSEGX_SIZE); 682 if (start > MIPS_PHYS_MASK && start + VM_KSEGX_SIZE <= finish) { 683 mips_ksegx_start = start; 684 mips_ksegx_pte.pt_entry = mips_paddr_to_tlbpfn(start) 685 | MIPS3_PG_D | MIPS3_PG_CACHED 686 | MIPS3_PG_V | MIPS3_PG_G; 687 fl[0].fl_start = start; 688 fl[0].fl_end = start + VM_KSEGX_SIZE; 689 fl[0].fl_freelist = VM_FREELIST_FIRST512M; 690 fl_count++; 691 DPRINTF("mips_ksegx_start %#"PRIxPADDR"\n", 692 fl[0].fl_start); 693 break; 694 } 695 } 696 #endif 697 698 /* get maximum RAM address from the VM clusters */ 699 mem_cluster_maxaddr = 0; 700 for (u_int i=0; i < mem_cluster_cnt; i++) { 701 u_quad_t tmp = round_page( 702 mem_clusters[i].start + mem_clusters[i].size); 703 if (tmp > mem_cluster_maxaddr) 704 mem_cluster_maxaddr = tmp; 705 } 706 DPRINTF("mem_cluster_maxaddr %#"PRIx64"\n", mem_cluster_maxaddr); 707 708 /* 709 * Load mem_clusters[] into the VM system. 710 */ 711 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 712 mem_clusters, mem_cluster_cnt, fl, fl_count); 713 714 /* 715 * Initialize error message buffer (at end of core). 716 */ 717 mips_init_msgbuf(); 718 719 pmap_bootstrap(); 720 721 /* 722 * Allocate uarea page for lwp0 and set it. 723 */ 724 mips_init_lwp0_uarea(); 725 726 /* 727 * Initialize debuggers, and break into them, if appropriate. 728 */ 729 #if NKSYMS || defined(DDB) || defined(LKM) 730 ksyms_init(0, 0, 0); 731 #endif 732 733 #if defined(DDB) 734 if (boothowto & RB_KDB) 735 Debugger(); 736 #endif 737 /* 738 * store (cpu#0) curcpu in COP0 OSSCRATCH0 739 * used in exception vector 740 */ 741 __asm __volatile("dmtc0 %0,$%1" 742 :: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH)); 743 #ifdef MULTIPROCESSOR 744 mips_fixup_exceptions(rmixl_fixup_cop0_oscratch); 745 #endif 746 rmixl_fixup_curcpu(); 747 } 748 749 /* 750 * set up Processor Control Regs for this core 751 */ 752 void 753 rmixl_pcr_init_core(bool is_xlp_p) 754 { 755 uint32_t r; 756 757 758 if (is_xlp_p) { 759 #if (MIPS64_XLP) > 0 760 #ifndef MULTIPROCESSOR 761 rmixl_mtcr(RMIXLP_PCR_IFU_THREAD_EN, 1); 762 /* disable all threads except #0 */ 763 #endif 764 rmixl_mtcr(RMIXLP_PCR_MMU_SETUP, 1); 765 /* enable MMU clock gating */ 766 /* TLB is global */ 767 #ifdef MIPS_DISABLE_L1_CACHE 768 r = rmixl_mfcr(RMIXLP_PCR_L1D_CONFIG0); 769 r &= ~__BIT(0); /* disable L1D cache */ 770 rmixl_mtcr(RMIXLP_PCR_L1D_CONFIG0, r); 771 #endif 772 r = rmixl_mfcr(RMIXLP_PCR_LSU_DEFEATURE); 773 r &= ~RMIXLP_PCR_LSE_DEFEATURE_EUL; 774 rmixl_mtcr(RMIXLP_PCR_LSU_DEFEATURE, r); 775 776 /* 777 * Enable Large Variable TLB. 778 */ 779 uint32_t cfg6 = mipsNN_cp0_config6_read(); 780 cfg6 |= MIPSNN_RMIXLP_CFG6_ELVT; 781 mipsNN_cp0_config6_write(cfg6); 782 /* 783 * Force TLB Random to be rewritten. 784 */ 785 mips3_cp0_wired_write(0); 786 #endif /* MIPS64_XLP */ 787 } else { 788 #if (MIPS64_XLR + MIPS64_XLS) > 0 789 #ifdef MULTIPROCESSOR 790 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0)); 791 /* enable MMU clock gating */ 792 /* 4 threads active -- why needed if Global? */ 793 /* enable global TLB mode */ 794 #else 795 rmixl_mtcr(RMIXL_PCR_THREADEN, 1); 796 /* disable all threads except #0 */ 797 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, 0); 798 /* enable MMU clock gating */ 799 /* set single MMU Thread Mode */ 800 /* TLB is partitioned (1 partition) */ 801 #endif 802 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 803 r &= ~__BIT(14); /* disable Unaligned Access */ 804 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 805 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 806 } 807 808 #if defined(DDB) && defined(MIPS_DDB_WATCH) 809 /* 810 * clear IEU_DEFEATURE[DBE] 811 * this enables COP0 watchpoint to trigger T_WATCH exception 812 * instead of signaling JTAG. 813 */ 814 r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE); 815 r &= ~__BIT(7); 816 rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r); 817 #endif 818 } 819 820 #ifdef MULTIPROCESSOR 821 static bool 822 rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2]) 823 { 824 size_t offset = load_addr - (intptr_t)&cpu_info_store; 825 826 KASSERT(MIPS_KSEG0_P(load_addr)); 827 KASSERT(offset < sizeof(struct cpu_info)); 828 829 /* 830 * Fixup this direct load cpu_info_store to actually get the current 831 * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be 832 * relative from the start of struct cpu_info. 833 */ 834 835 /* [0] = [d]mfc0 rX, $22 (OSScratch) */ 836 new_insns[0] = (020 << 26) 837 #ifdef _LP64 838 | (1 << 21) /* double move */ 839 #endif 840 | (new_insns[0] & 0x001f0000) 841 | (MIPS_COP_0_OSSCRATCH << 11) | (0 << 0); 842 843 /* [1] = [ls][dw] rX, offset(rX) */ 844 new_insns[1] = (new_insns[1] & 0xffff0000) | offset; 845 846 return true; 847 } 848 #endif /* MULTIPROCESSOR */ 849 850 /* 851 * The following changes all lX rN, L_CPU(MIPS_CURLWP) [curlwp->l_cpu] 852 * to [d]mfc0 rN, $22 [MIPS_COP_0_OSSCRATCH] 853 * 854 * the mfc0 is 3 cycles shorter than the load. 855 */ 856 #define LOAD_CURCPU_0 ((MIPS_CURLWP_REG << 21) | offsetof(lwp_t, l_cpu)) 857 #define MFC0_CURCPU_0 ((OP_COP0 << 26) | (MIPS_COP_0_OSSCRATCH << 11)) 858 #ifdef _LP64 859 #define LOAD_CURCPU ((uint32_t)(OP_LD << 26) | LOAD_CURCPU_0) 860 #define MFC0_CURCPU ((uint32_t)(OP_DMF << 21) | MFC0_CURCPU_0) 861 #else 862 #define LOAD_CURCPU ((uint32_t)(OP_LW << 26) | LOAD_CURCPU_0) 863 #define MFC0_CURCPU ((uint32_t)(OP_MF << 21) | MFC0_CURCPU_0) 864 #endif 865 #define LOAD_CURCPU_MASK 0xffe0ffff 866 867 static void 868 rmixl_fixup_curcpu(void) 869 { 870 extern uint32_t _ftext[]; 871 extern uint32_t _etext[]; 872 873 for (uint32_t *insnp = _ftext; insnp < _etext; insnp++) { 874 const uint32_t insn = *insnp; 875 if (__predict_false((insn & LOAD_CURCPU_MASK) == LOAD_CURCPU)) { 876 /* 877 * Since the register to loaded is located in bits 878 * 16-20 for the mfc0 and the load instruction we can 879 * just change the instruction bits around it. 880 */ 881 *insnp = insn ^ LOAD_CURCPU ^ MFC0_CURCPU; 882 mips_icache_sync_range((vaddr_t)insnp, 4); 883 } 884 } 885 } 886 887 /* 888 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 889 * 890 * we simply build a new table of segs, then copy it back over the given one 891 * this is inefficient but simple and called only a few times 892 * 893 * note: 'last' here means 1st addr past the end of the segment (start+size) 894 */ 895 static u_int 896 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 897 u_quad_t resv_first, u_quad_t resv_last) 898 { 899 u_quad_t first, last; 900 int new_nsegs=0; 901 int resv_flag; 902 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 903 904 for (u_int i=0; i < nsegs; i++) { 905 resv_flag = 0; 906 first = trunc_page(segs[i].start); 907 last = round_page(segs[i].start + segs[i].size); 908 909 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 910 if ((resv_first <= first) && (resv_last >= last)) { 911 /* whole segment is resverved */ 912 continue; 913 } 914 if ((resv_first > first) && (resv_first < last)) { 915 u_quad_t new_last; 916 917 /* 918 * reserved start in segment 919 * salvage the leading fragment 920 */ 921 resv_flag = 1; 922 new_last = last - (last - resv_first); 923 KASSERT (new_last > first); 924 new_segs[new_nsegs].start = first; 925 new_segs[new_nsegs].size = new_last - first; 926 new_nsegs++; 927 } 928 if ((resv_last > first) && (resv_last < last)) { 929 u_quad_t new_first; 930 931 /* 932 * reserved end in segment 933 * salvage the trailing fragment 934 */ 935 resv_flag = 1; 936 new_first = first + (resv_last - first); 937 KASSERT (last > (new_first + NBPG)); 938 new_segs[new_nsegs].start = new_first; 939 new_segs[new_nsegs].size = last - new_first; 940 new_nsegs++; 941 } 942 if (resv_flag == 0) { 943 /* 944 * nothing reserved here, take it all 945 */ 946 new_segs[new_nsegs].start = first; 947 new_segs[new_nsegs].size = last - first; 948 new_nsegs++; 949 } 950 951 } 952 953 memcpy(segs, new_segs, sizeof(new_segs)); 954 955 return new_nsegs; 956 } 957 958 #if (MIPS64_XLP) > 0 959 static void 960 rmixlp_physaddr_pcie_cfg_init(struct extent *ext) 961 { 962 struct rmixl_config * const rcp = &rmixl_configuration; 963 964 uint64_t xbase = RMIXLP_SBC_PCIE_CFG_TO_PA( 965 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_CFG_BASE)); 966 uint64_t xlimit = RMIXLP_SBC_PCIE_CFG_TO_PA( 967 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_CFG_LIMIT)); 968 969 if (xlimit < xbase || xbase == 0) 970 return; /* not enabled */ 971 972 uint64_t xsize = RMIXLP_SBC_PCIE_CFG_SIZE(xbase, xlimit); 973 974 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 975 "pci-cfg", xbase, xsize >> 20); 976 977 rmixl_physaddr_add(ext, "pcicfg", &rcp->rc_pci_cfg, xbase, xsize); 978 } 979 980 static void 981 rmixlp_physaddr_pcie_ecfg_init(struct extent *ext) 982 { 983 struct rmixl_config * const rcp = &rmixl_configuration; 984 985 uint64_t xbase = RMIXLP_SBC_PCIE_ECFG_TO_PA( 986 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_ECFG_BASE)); 987 uint64_t xlimit = RMIXLP_SBC_PCIE_ECFG_TO_PA( 988 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_ECFG_LIMIT)); 989 990 if (xlimit < xbase || xbase == 0) 991 return; /* not enabled */ 992 993 uint64_t xsize = RMIXLP_SBC_PCIE_ECFG_SIZE(xbase, xlimit); 994 995 KASSERT(rcp->rc_pci_ecfg.r_pbase == xbase); 996 997 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 998 "pci-ecfg", xbase, xsize >> 20); 999 1000 rmixl_physaddr_add(ext, "pciecfg", &rcp->rc_pci_ecfg, xbase, xsize); 1001 } 1002 1003 static void 1004 rmixlp_physaddr_pcie_mem_init(struct extent *ext) 1005 { 1006 struct rmixl_config * const rcp = &rmixl_configuration; 1007 for (size_t i = 0; i < RMIXLP_SBC_NPCIE_MEM; i++) { 1008 uint64_t xbase = RMIXLP_SBC_PCIE_MEM_TO_PA( 1009 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1010 RMIXLP_SBC_PCIE_MEM_BASEn(i))); 1011 uint64_t xlimit = RMIXLP_SBC_PCIE_MEM_TO_PA( 1012 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1013 RMIXLP_SBC_PCIE_MEM_LIMITn(i))); 1014 1015 if (xlimit < xbase || xbase == 0) 1016 continue; /* not enabled */ 1017 1018 uint64_t xsize = RMIXLP_SBC_PCIE_MEM_SIZE(xbase, xlimit); 1019 1020 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1021 "pci-mem", i, xbase, xsize >> 20); 1022 1023 rmixl_physaddr_add(ext, "pcimem", &rcp->rc_pci_link_mem[i], 1024 xbase, xsize); 1025 } 1026 } 1027 1028 static void 1029 rmixlp_physaddr_pcie_io_init(struct extent *ext) 1030 { 1031 struct rmixl_config * const rcp = &rmixl_configuration; 1032 for (size_t i = 0; i < RMIXLP_SBC_NPCIE_IO; i++) { 1033 uint64_t xbase = RMIXLP_SBC_PCIE_IO_TO_PA( 1034 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1035 RMIXLP_SBC_PCIE_IO_BASEn(i))); 1036 uint64_t xlimit = RMIXLP_SBC_PCIE_IO_TO_PA( 1037 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1038 RMIXLP_SBC_PCIE_IO_LIMITn(i))); 1039 1040 if (xlimit < xbase || xbase == 0) 1041 continue; /* not enabled */ 1042 1043 uint64_t xsize = RMIXLP_SBC_PCIE_IO_SIZE(xbase, xlimit); 1044 1045 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1046 "pci-io", i, xbase, xsize >> 20); 1047 1048 rmixl_physaddr_add(ext, "pci-io", &rcp->rc_pci_link_io[i], 1049 xbase, xsize); 1050 } 1051 } 1052 1053 static void 1054 rmixlp_physaddr_srio_mem_init(struct extent *ext) 1055 { 1056 struct rmixl_config * const rcp = &rmixl_configuration; 1057 uint64_t xbase = RMIXLP_SBC_SRIO_MEM_TO_PA( 1058 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_SRIO_MEM_BASE)); 1059 uint64_t xlimit = RMIXLP_SBC_SRIO_MEM_TO_PA( 1060 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_SRIO_MEM_LIMIT)); 1061 1062 if (xlimit < xbase || xbase == 0) 1063 return; /* not enabled */ 1064 1065 uint64_t xsize = RMIXLP_SBC_SRIO_MEM_SIZE(xbase, xlimit); 1066 1067 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 1068 "srio-mem", xbase, xsize >> 20); 1069 1070 rmixl_physaddr_add(ext, "sriomem", &rcp->rc_srio_mem, xbase, xsize); 1071 } 1072 1073 static void 1074 rmixlp_physaddr_nor_init(struct extent *ext) 1075 { 1076 struct rmixl_config * const rcp = &rmixl_configuration; 1077 for (size_t i = 0; i < RMIXLP_NOR_NCS; i++) { 1078 uint64_t xbase = RMIXLP_NOR_CS_ADDRESS_TO_PA( 1079 rmixlp_read_4(RMIXLP_NOR_PCITAG, 1080 RMIXLP_NOR_CS_BASEADDRESSn(i))); 1081 uint64_t xlimit = RMIXLP_NOR_CS_ADDRESS_TO_PA( 1082 rmixlp_read_4(RMIXLP_NOR_PCITAG, 1083 RMIXLP_NOR_CS_BASELIMITn(i))); 1084 1085 if (xlimit < xbase || xbase == 0) 1086 continue; /* not enabled */ 1087 1088 uint64_t xsize = RMIXLP_NOR_CS_SIZE(xbase, xlimit); 1089 1090 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1091 "nor", i, xbase, xsize >> 20); 1092 1093 rmixl_physaddr_add(ext, "nor", &rcp->rc_norflash[i], 1094 xbase, xsize); 1095 } 1096 } 1097 1098 static uint64_t 1099 rmixlp_physaddr_dram_init(struct extent *ext) 1100 { 1101 uint64_t memsize = 0; 1102 /* 1103 * grab regions per DRAM BARs 1104 */ 1105 phys_ram_seg_t *mp = mem_clusters; 1106 for (u_int i = 0; i < RMIXLP_SBC_NDRAM; i++) { 1107 uint64_t xbase = 1108 RMIXLP_SBC_DRAM_TO_PA( 1109 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1110 RMIXLP_SBC_DRAM_BASEn(i))); 1111 uint64_t xlimit = 1112 RMIXLP_SBC_DRAM_TO_PA( 1113 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1114 RMIXLP_SBC_DRAM_LIMITn(i))); 1115 1116 if (xlimit < xbase) 1117 continue; /* not enabled */ 1118 1119 mp->start = xbase; 1120 mp->size = RMIXLP_SBC_DRAM_SIZE(xbase, xlimit); 1121 1122 memsize += mp->size; 1123 1124 u_long base = mp->start >> 20; 1125 u_long size = mp->size >> 20; 1126 1127 mp++; 1128 1129 DPRINTF("%s: dram %u: 0x%05lx00000:%lu MB\n", 1130 __func__, i, base, size); 1131 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1132 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1133 "failed", __func__, ext, base, size, EX_NOWAIT); 1134 } 1135 1136 mem_cluster_cnt = mp - mem_clusters; 1137 return memsize; 1138 } 1139 #endif /* MIPS64_XLP */ 1140 1141 #if (MIPS64_XLR + MIPS64_XLS) > 0 1142 static uint64_t 1143 rmixl_physaddr_dram_init(struct extent *ext) 1144 { 1145 uint64_t memsize = 0; 1146 /* 1147 * grab regions per DRAM BARs 1148 */ 1149 phys_ram_seg_t *mp = mem_clusters; 1150 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 1151 uint32_t r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 1152 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 1153 continue; /* not enabled */ 1154 1155 mp->start = DRAM_BAR_TO_BASE((uint64_t)r); 1156 mp->size = DRAM_BAR_TO_SIZE((uint64_t)r); 1157 1158 u_long base = mp->start >> 20; 1159 u_long size = mp->size >> 20; 1160 1161 memsize += mp->size; 1162 1163 mp++; 1164 1165 DPRINTF("%s: dram %u: 0x%08x -- 0x%010lx:%lu MB\n", 1166 __func__, i, r, base * (1024 * 1024), size); 1167 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1168 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1169 "failed", __func__, ext, base, size, EX_NOWAIT); 1170 } 1171 1172 mem_cluster_cnt = mp - mem_clusters; 1173 1174 return memsize; 1175 } 1176 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1177 1178 /* 1179 * create an extent for physical address space 1180 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 1181 * allocate the regions where we have known functions (DRAM, IO, etc) 1182 * what remains can be allocated as needed for other stuff 1183 * e.g. to configure BARs that are not already initialized and enabled. 1184 */ 1185 static uint64_t 1186 rmixl_physaddr_init(void) 1187 { 1188 struct extent *ext; 1189 unsigned long start = 0UL; 1190 unsigned long end = (__BIT(40) / (1024 * 1024)) - 1; 1191 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1192 uint64_t memsize; 1193 1194 ext = extent_create("physaddr", start, end, M_DEVBUF, 1195 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 1196 EX_NOWAIT | EX_NOCOALESCE); 1197 1198 if (ext == NULL) 1199 panic("%s: extent_create failed", __func__); 1200 1201 if (is_xlp_p) { 1202 #if (MIPS64_XLP) > 0 1203 memsize = rmixlp_physaddr_dram_init(ext); 1204 rmixlp_physaddr_pcie_cfg_init(ext); 1205 rmixlp_physaddr_pcie_ecfg_init(ext); 1206 rmixlp_physaddr_pcie_mem_init(ext); 1207 rmixlp_physaddr_pcie_io_init(ext); 1208 rmixlp_physaddr_srio_mem_init(ext); 1209 rmixlp_physaddr_nor_init(ext); 1210 #else 1211 memsize = 0; 1212 #endif /* MIPS64_XLP */ 1213 } else { 1214 #if (MIPS64_XLR + MIPS64_XLS) > 0 1215 memsize = rmixl_physaddr_dram_init(ext); 1216 1217 /* 1218 * get chip-dependent physaddr regions 1219 */ 1220 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 1221 case CIDFL_RMI_TYPE_XLR: 1222 #if NRMIXL_PCIX 1223 rmixl_physaddr_init_pcix(ext); 1224 #endif 1225 break; 1226 case CIDFL_RMI_TYPE_XLS: 1227 #if NRMIXL_PCIE 1228 rmixl_physaddr_init_pcie(ext); 1229 #endif 1230 break; 1231 default: 1232 panic("%s: unknown chip type %d", __func__, 1233 cpu_rmixl_chip_type(mips_options.mips_cpu)); 1234 } 1235 #else 1236 memsize = 0; 1237 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1238 } 1239 1240 /* 1241 * at this point all regions left in "physaddr" extent 1242 * are unused holes in the physical adress space 1243 * available for use as needed. 1244 */ 1245 rmixl_configuration.rc_phys_ex = ext; 1246 #ifdef MACHDEP_DEBUG 1247 extent_print(ext); 1248 #endif 1249 return memsize; 1250 } 1251 1252 static uint64_t 1253 rmixlfw_init(int64_t infop) 1254 { 1255 struct rmixl_config * const rcp = &rmixl_configuration; 1256 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1257 1258 #ifdef MULTIPROCESSOR 1259 rmixl_get_wakeup_info(rcp); 1260 #endif 1261 1262 infop |= MIPS_KSEG0_START; 1263 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 1264 1265 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 1266 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 1267 if (rmiclfw_psb_id[i].psb_version == 1268 rcp->rc_psb_info.psb_version) { 1269 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 1270 goto found; 1271 } 1272 } 1273 1274 if (is_xlp_p) { 1275 #if (MIPS64_XLP) > 0 1276 rcp->rc_pci_ecfg.r_pbase = RMIXLP_SBC_PCIE_ECFG_PBASE; 1277 #endif /* MIPS64_XLP */ 1278 } else { 1279 #if (MIPS64_XLR + MIPS64_XLS) > 0 1280 rcp->rc_io.r_pbase = RMIXL_IO_DEV_PBASE; 1281 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1282 } 1283 1284 #ifdef DIAGNOSTIC 1285 printf("\nWARNING: untested psb_version: %#"PRIx64"\n", 1286 rcp->rc_psb_info.psb_version); 1287 #endif 1288 1289 #ifdef MEMSIZE 1290 /* XXX trust and use MEMSIZE */ 1291 mem_clusters[0].start = 0; 1292 mem_clusters[0].size = MEMSIZE; 1293 mem_cluster_cnt = 1; 1294 return MEMSIZE; 1295 #else 1296 uint64_t memsize = 0; 1297 for (size_t i = 0; i < mem_cluster_cnt; i++) { 1298 memsize += mem_clusters[i].size; 1299 } 1300 if (memsize) 1301 return memsize; 1302 1303 printf("\nERROR: configure MEMSIZE\n"); 1304 cpu_reboot(RB_HALT, NULL); 1305 /* NOTREACHED */ 1306 #endif 1307 1308 found: 1309 rcp->rc_io.r_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 1310 DPRINTF("\ninfop: %#"PRIx64"\n", infop); 1311 #ifdef DIAGNOSTIC 1312 printf("\nrecognized psb_version=%#"PRIx64", psb_type=%s\n", 1313 rcp->rc_psb_info.psb_version, 1314 rmixlfw_psb_type_name(rcp->rc_psb_type)); 1315 #endif 1316 1317 return mem_clusters_init( 1318 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 1319 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 1320 } 1321 1322 void 1323 rmixlfw_mmap_print(const char *mapname, rmixlfw_mmap_t *map) 1324 { 1325 #ifdef MACHDEP_DEBUG 1326 for (size_t i=0; i < map->nmmaps; i++) { 1327 printf("%s[%zu]: %#"PRIx64", %#"PRIx64", %#x\n", 1328 mapname, i, map->entry[i].start, map->entry[i].size, 1329 map->entry[i].type); 1330 } 1331 #endif 1332 } 1333 1334 /* 1335 * mem_clusters_init 1336 * 1337 * initialize mem_clusters[] table based on memory address mapping 1338 * provided by boot firmware. 1339 * 1340 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 1341 * these will be limited by MEMSIZE if it is configured. 1342 * if neither are available, just use MEMSIZE. 1343 */ 1344 static uint64_t 1345 mem_clusters_init( 1346 rmixlfw_mmap_t *psb_physaddr_map, 1347 rmixlfw_mmap_t *avail_mem_map) 1348 { 1349 rmixlfw_mmap_t *map = NULL; 1350 const char *mapname; 1351 uint64_t sz; 1352 uint64_t sum; 1353 u_int cnt; 1354 #ifdef MEMSIZE 1355 uint64_t memsize = MEMSIZE; 1356 #endif 1357 1358 #ifdef MACHDEP_DEBUG 1359 printf("psb_physaddr_map: %p\n", psb_physaddr_map); 1360 #endif 1361 if (psb_physaddr_map != NULL) { 1362 map = psb_physaddr_map; 1363 mapname = "psb_physaddr_map"; 1364 rmixlfw_mmap_print(mapname, map); 1365 } 1366 #ifdef DIAGNOSTIC 1367 else { 1368 printf("WARNING: no psb_physaddr_map\n"); 1369 } 1370 #endif 1371 1372 #ifdef MACHDEP_DEBUG 1373 printf("avail_mem_map: %p\n", avail_mem_map); 1374 #endif 1375 if (avail_mem_map != NULL) { 1376 map = avail_mem_map; 1377 mapname = "avail_mem_map"; 1378 rmixlfw_mmap_print(mapname, map); 1379 } 1380 #ifdef DIAGNOSTIC 1381 else { 1382 printf("WARNING: no avail_mem_map\n"); 1383 } 1384 #endif 1385 1386 if (map == NULL) { 1387 #ifndef MEMSIZE 1388 printf("panic: no firmware memory map, " 1389 "must configure MEMSIZE\r\n"); 1390 for(;;); /* XXX */ 1391 #else 1392 #ifdef DIAGNOSTIC 1393 printf("WARNING: no avail_mem_map, using MEMSIZE\n"); 1394 #endif 1395 1396 mem_clusters[0].start = 0; 1397 mem_clusters[0].size = MEMSIZE; 1398 mem_cluster_cnt = 1; 1399 return MEMSIZE; 1400 #endif /* MEMSIZE */ 1401 } 1402 1403 #ifdef DIAGNOSTIC 1404 printf("using %s\n", mapname); 1405 #endif 1406 #ifdef MACHDEP_DEBUG 1407 printf("memory clusters:\n"); 1408 #endif 1409 sum = 0; 1410 cnt = 0; 1411 for (uint32_t i=0; i < map->nmmaps; i++) { 1412 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 1413 continue; 1414 mem_clusters[cnt].start = map->entry[i].start; 1415 sz = map->entry[i].size; 1416 sum += sz; 1417 mem_clusters[cnt].size = sz; 1418 #ifdef MACHDEP_DEBUG 1419 printf("[%u]: %#"PRIx64", %#"PRIx64", %#"PRIx64"\n", 1420 i, mem_clusters[cnt].start, sz, sum); 1421 #endif 1422 #ifdef MEMSIZE 1423 /* 1424 * configurably limit memsize 1425 */ 1426 if (sum == memsize) 1427 break; 1428 if (sum > memsize) { 1429 uint64_t tmp; 1430 1431 tmp = sum - memsize; 1432 sz -= tmp; 1433 sum -= tmp; 1434 mem_clusters[cnt].size = sz; 1435 cnt++; 1436 break; 1437 } 1438 #endif 1439 cnt++; 1440 } 1441 mem_cluster_cnt = cnt; 1442 return sum; 1443 } 1444 1445 #ifdef MULTIPROCESSOR 1446 /* 1447 * RMI firmware passes wakeup info structure in CP0 OS Scratch reg #7 1448 * they do not explicitly give us the size of the wakeup area. 1449 * we "know" that firmware loader sets wip->gp thusly: 1450 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 1451 * so 1452 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 1453 * Only the "master" cpu runs this function, so 1454 * vcpu = wip->master_cpu 1455 */ 1456 void 1457 rmixl_get_wakeup_info(struct rmixl_config *rcp) 1458 { 1459 volatile rmixlfw_cpu_wakeup_info_t *wip; 1460 int32_t scratch_7; 1461 intptr_t end; 1462 1463 __asm__ volatile( 1464 ".set push" "\n" 1465 ".set noreorder" "\n" 1466 ".set mips64" "\n" 1467 "dmfc0 %0, $22, 7" "\n" 1468 ".set pop" "\n" 1469 : "=r"(scratch_7)); 1470 1471 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 1472 (intptr_t)scratch_7; 1473 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 1474 1475 if (wip->valid == 1) { 1476 rcp->rc_cpu_wakeup_end = (const void *)end; 1477 rcp->rc_cpu_wakeup_info = wip; 1478 } 1479 }; 1480 1481 #ifdef MACHDEP_DEBUG 1482 static void 1483 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 1484 { 1485 int i; 1486 1487 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 1488 1489 printf("cpu_status %#x\n", wip->cpu_status); 1490 printf("valid: %d\n", wip->valid); 1491 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 1492 wip->entry.addr, 1493 wip->entry.args, 1494 wip->entry.sp, 1495 wip->entry.gp); 1496 printf("master_cpu %d\n", wip->master_cpu); 1497 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 1498 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 1499 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 1500 printf("argc %d\n", wip->argc); 1501 printf("argv:"); 1502 for (i=0; i < wip->argc; i++) 1503 printf(" %#x", wip->argv[i]); 1504 printf("\n"); 1505 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 1506 printf("tlb_map:\n"); 1507 for (i=0; i < wip->valid_tlb_entries; i++) { 1508 volatile const struct lib_cpu_tlb_mapping *m = 1509 &wip->tlb_map[i]; 1510 printf(" %d", m->page_size); 1511 printf(", %d", m->asid); 1512 printf(", %d", m->coherency); 1513 printf(", %d", m->coherency); 1514 printf(", %d", m->attr); 1515 printf(", %#x", m->virt); 1516 printf(", %#"PRIx64"\n", m->phys); 1517 } 1518 printf("elf segs:\n"); 1519 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 1520 volatile const struct core_segment_info *e = 1521 &wip->seg_info[i]; 1522 printf(" %#"PRIx64"", e->vaddr); 1523 printf(", %#"PRIx64"", e->memsz); 1524 printf(", %#x\n", e->flags); 1525 } 1526 printf("envc %d\n", wip->envc); 1527 for (i=0; i < wip->envc; i++) 1528 printf(" %#x \"%s\"", wip->envs[i], 1529 (char *)(intptr_t)(int32_t)(wip->envs[i])); 1530 printf("\n"); 1531 printf("app_mode %d\n", wip->app_mode); 1532 printf("printk_lock %#x\n", wip->printk_lock); 1533 printf("kseg_master %d\n", wip->kseg_master); 1534 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 1535 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 1536 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 1537 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 1538 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 1539 printf("loader_lock %#x\n", wip->loader_lock); 1540 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 1541 printf("unused_0 %#x\n", wip->unused_0); 1542 } 1543 #endif /* MACHDEP_DEBUG */ 1544 #endif /* MULTIPROCESSOR */ 1545 1546 void 1547 consinit(void) 1548 { 1549 1550 /* 1551 * Everything related to console initialization is done 1552 * in mach_init(). 1553 */ 1554 } 1555 1556 /* 1557 * Allocate memory for variable-sized tables, 1558 */ 1559 void 1560 cpu_startup() 1561 { 1562 vaddr_t minaddr, maxaddr; 1563 char pbuf[9]; 1564 1565 /* 1566 * Good {morning,afternoon,evening,night}. 1567 */ 1568 printf("%s%s", copyright, version); 1569 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 1570 printf("total memory = %s\n", pbuf); 1571 1572 /* 1573 * Virtual memory is bootstrapped -- notify the bus spaces 1574 * that memory allocation is now safe. 1575 */ 1576 rmixl_configuration.rc_mallocsafe = 1; 1577 1578 minaddr = 0; 1579 /* 1580 * Allocate a submap for physio. 1581 */ 1582 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 1583 VM_PHYS_SIZE, 0, FALSE, NULL); 1584 1585 /* 1586 * (No need to allocate an mbuf cluster submap. Mbuf clusters 1587 * are allocated via the pool allocator, and we use XKSEG to 1588 * map those pages.) 1589 */ 1590 1591 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 1592 printf("avail memory = %s\n", pbuf); 1593 } 1594 1595 int waittime = -1; 1596 1597 void 1598 cpu_reboot(int howto, char *bootstr) 1599 { 1600 1601 /* Take a snapshot before clobbering any registers. */ 1602 savectx(lwp_getpcb(curlwp)); 1603 1604 if (cold) { 1605 howto |= RB_HALT; 1606 goto haltsys; 1607 } 1608 1609 /* If "always halt" was specified as a boot flag, obey. */ 1610 if (boothowto & RB_HALT) 1611 howto |= RB_HALT; 1612 1613 boothowto = howto; 1614 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 1615 waittime = 0; 1616 vfs_shutdown(); 1617 1618 /* 1619 * If we've been adjusting the clock, the todr 1620 * will be out of synch; adjust it now. 1621 */ 1622 resettodr(); 1623 } 1624 1625 splhigh(); 1626 1627 if (howto & RB_DUMP) 1628 dumpsys(); 1629 1630 haltsys: 1631 doshutdownhooks(); 1632 1633 if (howto & RB_HALT) { 1634 printf("\n"); 1635 printf("The operating system has halted.\n"); 1636 printf("Please press any key to reboot.\n\n"); 1637 cnpollc(1); /* For proper keyboard command handling */ 1638 cngetc(); 1639 cnpollc(0); 1640 } 1641 1642 printf("rebooting...\n\n"); 1643 1644 rmixl_reset(); 1645 } 1646 1647 /* 1648 * goodbye world 1649 */ 1650 void __attribute__((__noreturn__)) 1651 rmixl_reset(void) 1652 { 1653 uint32_t r; 1654 1655 if (MIPSNN_GET(CFG_AR, mips3_cp0_config_read()) == MIPSNN_CFG_AR_REV2) { 1656 rmixlp_write_4(RMIXLP_SM_PCITAG, RMIXLP_SM_CHIP_RESET, 1); 1657 DELAY(1000000); 1658 printf("%s: resorting to plan b!", __func__); 1659 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x18035100) = 1; 1660 __asm __volatile("sync"); 1661 } else { 1662 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1663 r |= RMIXL_GPIO_RESET_RESET; 1664 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1665 } 1666 1667 printf("soft reset failed, spinning...\n"); 1668 for (;;); 1669 } 1670 1671 #ifdef __HAVE_PCI_CONF_HOOK 1672 int 1673 rmixl_pci_conf_hook(void *v, int bus, int device, int function, pcireg_t id) 1674 { 1675 return PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM; 1676 } 1677 #endif 1678
Indexes created Fri Oct 31 11:10:07 GMT 2025