machdep.c revision 1.1.2.43
1 /* machdep.c,v 1.1.2.34 2011/04/29 08:26:18 matt Exp */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1988 University of Utah. 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * the Systems Programming Group of the University of Utah Computer 45 * Science Department, The Mach Operating System project at 46 * Carnegie-Mellon University and Ralph Campbell. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 73 * from: Utah Hdr: machdep.c 1.63 91/04/24 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "machdep.c,v 1.1.2.34 2011/04/29 08:26:18 matt Exp"); 78 79 #define __INTR_PRIVATE 80 #define __MUTEX_PRIVATE 81 #define _MIPS_BUS_DMA_PRIVATE 82 83 #include "opt_multiprocessor.h" 84 #include "opt_ddb.h" 85 #include "opt_com.h" 86 #include "opt_execfmt.h" 87 #include "opt_memsize.h" 88 #include "rmixl_pcix.h" 89 #include "rmixl_pcie.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/kernel.h> 94 #include <sys/buf.h> 95 #include <sys/reboot.h> 96 #include <sys/mount.h> 97 #include <sys/kcore.h> 98 #include <sys/boot_flag.h> 99 #include <sys/termios.h> 100 #include <sys/ksyms.h> 101 #include <sys/intr.h> 102 #include <sys/bus.h> 103 #include <sys/device.h> 104 #include <sys/extent.h> 105 #include <sys/malloc.h> 106 107 #include <uvm/uvm_extern.h> 108 109 #include <dev/cons.h> 110 111 #include "ksyms.h" 112 113 #if NKSYMS || defined(DDB) || defined(LKM) 114 #include <mips/db_machdep.h> 115 #include <ddb/db_extern.h> 116 #endif 117 118 #include <mips/cpu.h> 119 #include <mips/psl.h> 120 #include <mips/cache.h> 121 #include <mips/mipsNN.h> 122 #include <mips/mips_opcode.h> 123 #include <mips/pte.h> 124 125 #include "com.h" 126 #if NCOM == 0 127 #error no serial console 128 #endif 129 130 #include <dev/ic/comreg.h> 131 #include <dev/ic/comvar.h> 132 133 #include <dev/pci/pcireg.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/pciconf.h> 136 137 #include <mips/rmi/rmixlreg.h> 138 #include <mips/rmi/rmixlvar.h> 139 #include <mips/rmi/rmixl_intr.h> 140 #include <mips/rmi/rmixl_firmware.h> 141 #include <mips/rmi/rmixl_comvar.h> 142 #include <mips/rmi/rmixl_pcievar.h> 143 #include <mips/rmi/rmixl_pcixvar.h> 144 145 //#define MACHDEP_DEBUG 1 146 #ifdef MACHDEP_DEBUG 147 int machdep_debug=MACHDEP_DEBUG; 148 # define DPRINTF(x,...) do { if (machdep_debug) printf(x, ## __VA_ARGS__); } while(0) 149 #else 150 # define DPRINTF(x,...) 151 #endif 152 153 #ifdef __HAVE_PCI_CONF_HOOK 154 static int rmixl_pci_conf_hook(void *, int, int, int, pcireg_t); 155 #endif 156 157 #ifndef CONSFREQ 158 # define CONSFREQ 66000000 159 #endif 160 #ifndef CONSPEED 161 # define CONSPEED 38400 162 #endif 163 #ifndef CONMODE 164 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 165 #endif 166 #ifndef CONSADDR 167 # define CONSADDR 0 168 #endif 169 170 int comcnfreq = CONSFREQ; 171 int comcnspeed = CONSPEED; 172 tcflag_t comcnmode = CONMODE; 173 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 174 175 struct rmixl_config rmixl_configuration = { 176 .rc_io = { 177 .r_pbase = (bus_addr_t)-1, 178 }, 179 .rc_flash[0] = { 180 .r_pbase = (bus_addr_t)-1, 181 }, 182 .rc_flash[1] = { 183 .r_pbase = (bus_addr_t)-1, 184 }, 185 .rc_flash[2] = { 186 .r_pbase = (bus_addr_t)-1, 187 }, 188 .rc_flash[3] = { 189 .r_pbase = (bus_addr_t)-1, 190 }, 191 .rc_pci_cfg = { 192 .r_pbase = (bus_addr_t)-1, 193 }, 194 .rc_pci_ecfg = { 195 .r_pbase = (bus_addr_t)-1, 196 }, 197 .rc_pci_mem = { 198 .r_pbase = (bus_addr_t)-1, 199 }, 200 .rc_pci_io = { 201 .r_pbase = (bus_addr_t)-1, 202 }, 203 .rc_pci_link_mem[0] = { 204 .r_pbase = (bus_addr_t)-1, 205 }, 206 .rc_pci_link_mem[1] = { 207 .r_pbase = (bus_addr_t)-1, 208 }, 209 .rc_pci_link_mem[2] = { 210 .r_pbase = (bus_addr_t)-1, 211 }, 212 .rc_pci_link_mem[3] = { 213 .r_pbase = (bus_addr_t)-1, 214 }, 215 .rc_pci_link_io[0] = { 216 .r_pbase = (bus_addr_t)-1, 217 }, 218 .rc_pci_link_io[1] = { 219 .r_pbase = (bus_addr_t)-1, 220 }, 221 .rc_pci_link_io[2] = { 222 .r_pbase = (bus_addr_t)-1, 223 }, 224 .rc_pci_link_io[3] = { 225 .r_pbase = (bus_addr_t)-1, 226 }, 227 .rc_srio_mem = { 228 .r_pbase = (bus_addr_t)-1, 229 }, 230 /* 231 * Staticly initialize the 64-bit dmatag. 232 */ 233 .rc_dmat64 = &rmixl_configuration.rc_dma_tag, 234 .rc_dma_tag = { 235 ._cookie = &rmixl_configuration.rc_dma_tag, 236 ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER, 237 ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER, 238 ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER, 239 }, 240 .rc_gpio_available = ~(uint64_t)0, /* all pins by default */ 241 #ifdef __HAVE_PCI_CONF_HOOK 242 .rc_pci_chipset = { 243 .pc_conf_hook = rmixl_pci_conf_hook, 244 } 245 #endif 246 }; 247 248 #ifdef ENABLE_MIPS_KSEGX 249 pt_entry_t mips_ksegx_pte; 250 paddr_t mips_ksegx_start; 251 #endif 252 253 /* 254 * array of tested firmware versions 255 * if you find new ones and they work 256 * please add them 257 */ 258 typedef struct rmiclfw_psb_id { 259 uint64_t psb_version; 260 rmixlfw_psb_type_t psb_type; 261 } rmiclfw_psb_id_t; 262 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 263 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 264 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 265 { 0x4b67d03200000056ULL, PSB_TYPE_RMI }, 266 { 0x4c17058b00000056ULL, PSB_TYPE_RMI }, 267 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 268 { 0x4b8ead3100000056ULL, PSB_TYPE_DELL }, 269 }; 270 #define RMICLFW_PSB_VERSIONS_LEN \ 271 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 272 273 /* 274 * storage for fixed extent used to allocate physical address regions 275 * because extent(9) start and end values are u_long, they are only 276 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 277 * address is 40 bits wide. So the "physaddr" map stores regions 278 * in units of megabytes. 279 */ 280 static u_long rmixl_physaddr_storage[ 281 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 282 ]; 283 284 /* For sysctl_hw. */ 285 extern char cpu_model[]; 286 287 /* Our exported CPU info; we can have only one. */ 288 struct cpu_info cpu_info_store; 289 290 /* Maps for VM objects. */ 291 struct vm_map *mb_map = NULL; 292 struct vm_map *phys_map = NULL; 293 294 int physmem; /* Total physical memory */ 295 296 int netboot; /* Are we netbooting? */ 297 298 299 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 300 u_quad_t mem_cluster_maxaddr; 301 u_int mem_cluster_cnt; 302 303 304 void configure(void); 305 void mach_init(int, int32_t *, void *, int64_t); 306 static uint64_t rmixlfw_init(int64_t); 307 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 308 static void __attribute__((__noreturn__)) rmixl_reset(void); 309 static uint64_t rmixl_physaddr_init(void); 310 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 311 void rmixlfw_mmap_print(const char *, rmixlfw_mmap_t *); 312 313 314 #ifdef MULTIPROCESSOR 315 static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2]); 316 void rmixl_get_wakeup_info(struct rmixl_config *); 317 #ifdef MACHDEP_DEBUG 318 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 319 #endif /* MACHDEP_DEBUG */ 320 #endif /* MULTIPROCESSOR */ 321 static void rmixl_fixup_curcpu(void); 322 323 #if NCOM > 0 324 static volatile uint32_t *rmixl_com0addr; 325 326 static int 327 rmixl_cngetc(dev_t dv) 328 { 329 volatile uint32_t * const com0addr = rmixl_com0addr; 330 331 if ((be32toh(com0addr[com_lsr]) & LSR_RXRDY) == 0) 332 return -1; 333 334 return be32toh(com0addr[com_data]) & 0xff; 335 } 336 337 static void 338 rmixl_cnputc(dev_t dv, int c) 339 { 340 volatile uint32_t * const com0addr = rmixl_com0addr; 341 int timo = 150000; 342 343 while ((be32toh(com0addr[com_lsr]) & LSR_TXRDY) == 0 && --timo > 0) 344 ; 345 346 com0addr[com_data] = htobe32(c); 347 __asm __volatile("sync"); 348 349 while ((be32toh(com0addr[com_lsr]) & LSR_TSRE) == 0 && --timo > 0) 350 ; 351 } 352 353 struct consdev rmixl_earlycons = { 354 .cn_putc = rmixl_cnputc, 355 .cn_getc = rmixl_cngetc, 356 .cn_pollc = nullcnpollc, 357 }; 358 #endif 359 360 /* 361 * Do all the stuff that locore normally does before calling main(). 362 */ 363 void 364 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 365 { 366 struct rmixl_config *rcp = &rmixl_configuration; 367 void *kernend; 368 uint64_t memsize; 369 extern char edata[], end[]; 370 size_t fl_count = 0; 371 struct mips_vmfreelist fl[1]; 372 bool uboot_p = false; 373 374 const uint32_t cfg0 = mips3_cp0_config_read(); 375 #if (MIPS64_XLR + MIPS64_XLS) > 0 && (MIPS64_XLP) == 0 376 const bool is_xlp_p = false /* make sure cfg0 is used */ 377 && MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2; 378 KASSERT(MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV1); 379 #elif (MIPS64_XLR + MIPS64_XLS) == 0 && (MIPS64_XLP) > 0 380 const bool is_xlp_p = true /* make sure cfg0 is used */ 381 || MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2; 382 KASSERT(MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2); 383 #else 384 const bool is_xlp_p = (MIPSNN_GET(CFG_AR, cfg0) == MIPSNN_CFG_AR_REV2); 385 #endif 386 387 rmixl_pcr_init_core(is_xlp_p); 388 389 #ifdef MULTIPROCESSOR 390 __asm __volatile("dmtc0 %0,$%1,2" 391 :: "r"(&pmap_tlb0_info.ti_hwlock->mtx_lock), 392 "n"(MIPS_COP_0_OSSCRATCH)); 393 #endif 394 395 /* 396 * Clear the BSS segment. 397 */ 398 kernend = (void *)mips_round_page(end); 399 memset(edata, 0, (char *)kernend - edata); 400 401 #if NCOM > 0 402 /* 403 * If no comcnaddr has been set, pick an appropriate one. 404 */ 405 if (comcnaddr == 0) { 406 comcnaddr = is_xlp_p 407 ? RMIXLP_UART1_PCITAG 408 : RMIXL_IO_DEV_UART_1; 409 } 410 if (is_xlp_p) { 411 #if (MIPS64_XLP) > 0 412 rmixl_com0addr = 413 (void *)(vaddr_t)(RMIXLP_SBC_PCIE_ECFG_VBASE | comcnaddr | 0x100); 414 #endif /* MIPS64_XLP */ 415 } else { 416 #if (MIPS64_XLR + MIPS64_XLS) > 0 417 rcp->rc_io.r_pbase = RMIXL_IO_DEV_PBASE; 418 rmixl_com0addr = 419 (void *)(vaddr_t)(RMIXL_IO_DEV_VBASE | comcnaddr); 420 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 421 } 422 cn_tab = &rmixl_earlycons; 423 #endif 424 425 /* 426 * Set up the exception vectors and CPU-specific function 427 * vectors early on. We need the wbflush() vector set up 428 * before comcnattach() is called (or at least before the 429 * first printf() after that is called). 430 * Also clears the I+D caches. 431 * 432 * specify chip-specific EIRR/EIMR based spl functions 433 */ 434 #ifdef MULTIPROCESSOR 435 mips_vector_init(&rmixl_splsw, true); 436 #else 437 mips_vector_init(&rmixl_splsw, false); 438 #endif 439 440 if (argc < 0) { 441 void *bd = (void *)(intptr_t)argc; 442 void *imgaddr = argv; 443 void *consdev = envp; 444 char *bootargs = (void *)(intptr_t)infop; 445 printf("%s: u-boot: boardinfo=%p, image-addr=%p, consdev=%p, bootargs=%p <%s>\n", 446 __func__, bd, imgaddr, consdev, bootargs, bootargs); 447 uboot_p = true; 448 printf("%s: u-boot: console baudrate=%d\n", __func__, 449 *(int *)bd); 450 if (*(int *)bd % 1200 == 0) 451 comcnspeed = *(int *)bd; 452 } else { 453 DPRINTF("%s: argc=%d, argv=%p, envp=%p, info=%#"PRIx64"\n", 454 __func__, argc, argv, envp, infop); 455 } 456 457 /* mips_vector_init initialized mips_options */ 458 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 459 460 if (is_xlp_p) { 461 #if (MIPS64_XLP) > 0 462 uint32_t cfg6 = mipsNN_cp0_config6_read(); 463 printf("%s: cfg6=%#x " 464 "<ctlb=%u,vtlb=%u,elvt=%u,epw=%u,eft=%u,pwi=%u,fti=%u>\n", 465 __func__, cfg6, 466 MIPSNN_GET(RMIXLP_CFG6_CTLB_SIZE, cfg6), 467 MIPSNN_GET(RMIXLP_CFG6_VTLB_SIZE, cfg6), 468 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_ELVT), 469 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_EPW), 470 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_EFT), 471 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_PWI), 472 __SHIFTOUT(cfg6, MIPSNN_RMIXLP_CFG6_FTI)); 473 rcp->rc_pci_ecfg.r_pbase = RMIXLP_SBC_PCIE_ECFG_PBASE; 474 rcp->rc_pci_ecfg.r_size = RMIXLP_SBC_PCIE_ECFG_SIZE( 475 RMIXLP_SBC_PCIE_ECFG_PBASE, 476 RMIXLP_SBC_PCIE_ECFG_TO_PA( 477 rmixlp_read_4(RMIXLP_SBC_PCITAG, 478 RMIXLP_SBC_PCIE_ECFG_LIMIT))); 479 480 DPRINTF("%s: ecfg pbase=%#"PRIxBUSADDR" size=%#"PRIxBUSSIZE"\n", 481 __func__, rcp->rc_pci_ecfg.r_pbase, 482 rcp->rc_pci_ecfg.r_size); 483 484 rmixl_pci_ecfg_eb_bus_mem_init(&rcp->rc_pci_ecfg_eb_memt, rcp); 485 rmixl_pci_ecfg_el_bus_mem_init(&rcp->rc_pci_ecfg_el_memt, rcp); 486 rcp->rc_pci_ecfg_eb_memh = MIPS_PHYS_TO_KSEG1(rcp->rc_pci_ecfg.r_pbase); 487 rcp->rc_pci_ecfg_el_memh = rcp->rc_pci_ecfg_eb_memh; 488 DPRINTF("%s: pci ecfg bus space done!\n", __func__); 489 rmixlp_pcie_pc_init(); 490 DPRINTF("%s: pci chipset init done!\n", __func__); 491 #if NCOM > 0 492 comcnfreq = 133333333; 493 com_pci_cnattach(comcnaddr, comcnspeed, 494 comcnfreq, COM_TYPE_NORMAL, comcnmode); 495 DPRINTF("%s: com@pci console attached!\n", __func__); 496 #endif 497 #endif /* MIPS64_XLP */ 498 } 499 500 /* determine DRAM first */ 501 memsize = rmixl_physaddr_init(); 502 DPRINTF("%s: physaddr init done (memsize=%"PRIu64"MB)!\n", 503 __func__, memsize >> 20); 504 505 if (!uboot_p) { 506 /* get system info from firmware */ 507 memsize = rmixlfw_init(infop); 508 DPRINTF("%s: firmware init done (memsize=%"PRIu64"MB)!\n", 509 __func__, memsize >> 20); 510 } else { 511 rcp->rc_psb_info.userapp_cpu_map = 1; 512 } 513 514 /* set the VM page size */ 515 uvm_setpagesize(); 516 517 physmem = btoc(memsize); 518 519 if (!is_xlp_p) { 520 #if (MIPS64_XLR + MIPS64_XLS) > 0 521 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 522 #if NCOM > 0 523 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 524 COM_TYPE_NORMAL, comcnmode); 525 #endif 526 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 527 } 528 529 printf("\nNetBSD/rmixl\n"); 530 printf("memsize = %#"PRIx64"\n", memsize); 531 #ifdef MEMLIMIT 532 printf("memlimit = %#"PRIx64"\n", (uint64_t)MEMLIMIT); 533 #endif 534 535 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 536 if (!uboot_p) { 537 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 538 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 539 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 540 rcp->rc_cpu_wakeup_info, 541 rcp->rc_cpu_wakeup_end); 542 printf("userapp_cpu_map: %#"PRIx64"\n", 543 rcp->rc_psb_info.userapp_cpu_map); 544 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 545 } 546 { 547 register_t sp; 548 asm volatile ("move %0, $sp\n" : "=r"(sp)); 549 printf("sp: %#"PRIx64"\n", sp); 550 } 551 #endif 552 553 /* 554 * Obtain the cpu frequency 555 * Compute the number of ticks for hz. 556 * Compute the delay divisor. 557 * Double the Hz if this CPU runs at twice the 558 * external/cp0-count frequency 559 */ 560 if (uboot_p) { 561 /* 562 * Since u-boot doesn't tell us, we have to figure it out 563 */ 564 if (is_xlp_p) { 565 #if (MIPS64_XLP) > 0 566 uint32_t por_cfg = rmixlp_read_4(RMIXLP_SM_PCITAG, 567 RMIXLP_SM_POWER_ON_RESET_CFG); 568 u_int cdv = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDV) + 1; 569 u_int cdf = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDF) + 1; 570 u_int cdr = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CDR) + 1; 571 u_int cpll_dfs = __SHIFTOUT(por_cfg, RMIXLP_SM_POWER_ON_RESET_CFG_CPLL_DFS) + 1; 572 573 uint64_t freq_in = 133333333; 574 uint64_t freq_out = (freq_in / cdr) * cdf / (cdv * cpll_dfs); 575 if (freq_out % 1000 > 900) { 576 freq_out = (freq_out + 99) / 100; 577 freq_out *= 100; 578 } 579 rcp->rc_psb_info.cpu_frequency = freq_out; 580 #endif /* MIPS64_XLP > 0 */ 581 } else { 582 #if (MIPS64_XLR + MIPS64_XLS) > 0 583 const uint32_t por_cfg = RMIXL_IOREG_READ( 584 RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG); 585 586 const u_int divq = __SHIFTOUT(por_cfg, 587 RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV); 588 const u_int divf = __SHIFTOUT(por_cfg, 589 RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV) + 1; 590 591 uint64_t freq_in = 66666666; 592 uint64_t freq_out = (freq_in / 4) * divf / divq; 593 594 if (freq_out % 1000 > 900) { 595 freq_out = (freq_out + 99) / 100; 596 freq_out *= 100; 597 } 598 rcp->rc_psb_info.cpu_frequency = freq_out; 599 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 600 } 601 } 602 DPRINTF("%s: cpu_freq=%"PRIu64"\n", __func__, 603 rcp->rc_psb_info.cpu_frequency); 604 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 605 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 606 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 607 curcpu()->ci_divisor_delay = 608 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 609 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 610 curcpu()->ci_cpu_freq *= 2; 611 612 /* 613 * Look at arguments passed to us and compute boothowto. 614 * - rmixl firmware gives us a 32 bit argv[i], so adapt 615 * by forcing sign extension in cast to (char *) 616 */ 617 boothowto = RB_AUTOBOOT; 618 // boothowto |= AB_VERBOSE; 619 // boothowto |= AB_DEBUG; 620 if (!uboot_p) { 621 for (int i = 1; i < argc; i++) { 622 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 623 int howto; 624 /* Ignore superfluous '-', if there is one */ 625 if (*cp == '-') 626 continue; 627 628 howto = 0; 629 BOOT_FLAG(*cp, howto); 630 if (howto != 0) 631 boothowto |= howto; 632 #ifdef DIAGNOSTIC 633 else 634 printf("bootflag '%c' not recognised\n", 635 *cp); 636 #endif 637 } 638 } 639 } 640 #ifdef DIAGNOSTIC 641 printf("boothowto %#x\n", boothowto); 642 #endif 643 644 /* 645 * Reserve pages from the VM system. 646 */ 647 648 /* reserve 0..start..kernend pages */ 649 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 650 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 651 652 /* reserve reset exception vector page */ 653 /* should never be in our clusters anyway... */ 654 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 655 0x1FC00000, 0x1FC00000+NBPG); 656 657 /* Stop this abomination */ 658 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 659 0x18000000, 0x20000000); 660 661 #ifdef MULTIPROCESSOR 662 /* reserve the cpu_wakeup_info area */ 663 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 664 (u_quad_t)trunc_page((vaddr_t)rcp->rc_cpu_wakeup_info), 665 (u_quad_t)round_page((vaddr_t)rcp->rc_cpu_wakeup_end)); 666 #endif 667 668 #ifdef MEMLIMIT 669 /* reserve everything >= MEMLIMIT */ 670 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 671 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 672 #endif 673 674 #ifdef ENABLE_MIPS_KSEGX 675 /* 676 * Now we need to reserve an aligned block of memory for pre-init 677 * allocations so we don't deplete KSEG0. 678 */ 679 for (u_int i=0; i < mem_cluster_cnt; i++) { 680 u_quad_t finish = round_page( 681 mem_clusters[i].start + mem_clusters[i].size); 682 u_quad_t start = roundup2(mem_clusters[i].start, VM_KSEGX_SIZE); 683 if (start > MIPS_PHYS_MASK && start + VM_KSEGX_SIZE <= finish) { 684 mips_ksegx_start = start; 685 mips_ksegx_pte.pt_entry = mips_paddr_to_tlbpfn(start) 686 | MIPS3_PG_D | MIPS3_PG_CACHED 687 | MIPS3_PG_V | MIPS3_PG_G; 688 fl[0].fl_start = start; 689 fl[0].fl_end = start + VM_KSEGX_SIZE; 690 fl[0].fl_freelist = VM_FREELIST_FIRST512M; 691 fl_count++; 692 DPRINTF("mips_ksegx_start %#"PRIxPADDR"\n", 693 fl[0].fl_start); 694 break; 695 } 696 } 697 #endif 698 699 /* get maximum RAM address from the VM clusters */ 700 mem_cluster_maxaddr = 0; 701 for (u_int i=0; i < mem_cluster_cnt; i++) { 702 u_quad_t tmp = round_page( 703 mem_clusters[i].start + mem_clusters[i].size); 704 if (tmp > mem_cluster_maxaddr) 705 mem_cluster_maxaddr = tmp; 706 } 707 DPRINTF("mem_cluster_maxaddr %#"PRIx64"\n", mem_cluster_maxaddr); 708 709 /* 710 * Load mem_clusters[] into the VM system. 711 */ 712 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 713 mem_clusters, mem_cluster_cnt, fl, fl_count); 714 715 /* 716 * Initialize error message buffer (at end of core). 717 */ 718 mips_init_msgbuf(); 719 720 pmap_bootstrap(); 721 722 /* 723 * Allocate uarea page for lwp0 and set it. 724 */ 725 mips_init_lwp0_uarea(); 726 727 /* 728 * Initialize debuggers, and break into them, if appropriate. 729 */ 730 #if NKSYMS || defined(DDB) || defined(LKM) 731 ksyms_init(0, 0, 0); 732 #endif 733 734 #if defined(DDB) 735 if (boothowto & RB_KDB) 736 Debugger(); 737 #endif 738 /* 739 * store (cpu#0) curcpu in COP0 OSSCRATCH0 740 * used in exception vector 741 */ 742 __asm __volatile("dmtc0 %0,$%1" 743 :: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH)); 744 #ifdef MULTIPROCESSOR 745 mips_fixup_exceptions(rmixl_fixup_cop0_oscratch); 746 #endif 747 rmixl_fixup_curcpu(); 748 } 749 750 /* 751 * set up Processor Control Regs for this core 752 */ 753 void 754 rmixl_pcr_init_core(bool is_xlp_p) 755 { 756 uint32_t r; 757 758 759 if (is_xlp_p) { 760 #if (MIPS64_XLP) > 0 761 #ifndef MULTIPROCESSOR 762 rmixl_mtcr(RMIXLP_PCR_IFU_THREAD_EN, 1); 763 /* disable all threads except #0 */ 764 #endif 765 rmixl_mtcr(RMIXLP_PCR_MMU_SETUP, 1); 766 /* enable MMU clock gating */ 767 /* TLB is global */ 768 #ifdef MIPS_DISABLE_L1_CACHE 769 r = rmixl_mfcr(RMIXLP_PCR_L1D_CONFIG0); 770 r &= ~__BIT(0); /* disable L1D cache */ 771 rmixl_mtcr(RMIXLP_PCR_L1D_CONFIG0, r); 772 #endif 773 r = rmixl_mfcr(RMIXLP_PCR_LSU_DEFEATURE); 774 r &= ~RMIXLP_PCR_LSE_DEFEATURE_EUL; 775 rmixl_mtcr(RMIXLP_PCR_LSU_DEFEATURE, r); 776 777 /* 778 * Enable Large Variable TLB. 779 */ 780 uint32_t cfg6 = mipsNN_cp0_config6_read(); 781 cfg6 |= MIPSNN_RMIXLP_CFG6_ELVT; 782 mipsNN_cp0_config6_write(cfg6); 783 /* 784 * Force TLB Random to be rewritten. 785 */ 786 mips3_cp0_wired_write(0); 787 #endif /* MIPS64_XLP */ 788 } else { 789 #if (MIPS64_XLR + MIPS64_XLS) > 0 790 #ifdef MULTIPROCESSOR 791 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0)); 792 /* enable MMU clock gating */ 793 /* 4 threads active -- why needed if Global? */ 794 /* enable global TLB mode */ 795 #else 796 rmixl_mtcr(RMIXL_PCR_THREADEN, 1); 797 /* disable all threads except #0 */ 798 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, 0); 799 /* enable MMU clock gating */ 800 /* set single MMU Thread Mode */ 801 /* TLB is partitioned (1 partition) */ 802 #endif 803 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 804 r &= ~__BIT(14); /* disable Unaligned Access */ 805 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 806 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 807 } 808 809 #if defined(DDB) && defined(MIPS_DDB_WATCH) 810 /* 811 * clear IEU_DEFEATURE[DBE] 812 * this enables COP0 watchpoint to trigger T_WATCH exception 813 * instead of signaling JTAG. 814 */ 815 r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE); 816 r &= ~__BIT(7); 817 rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r); 818 #endif 819 } 820 821 #ifdef MULTIPROCESSOR 822 static bool 823 rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2]) 824 { 825 size_t offset = load_addr - (intptr_t)&cpu_info_store; 826 827 KASSERT(MIPS_KSEG0_P(load_addr)); 828 KASSERT(offset < sizeof(struct cpu_info)); 829 830 /* 831 * Fixup this direct load cpu_info_store to actually get the current 832 * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be 833 * relative from the start of struct cpu_info. 834 */ 835 836 /* [0] = [d]mfc0 rX, $22 (OSScratch) */ 837 new_insns[0] = (020 << 26) 838 #ifdef _LP64 839 | (1 << 21) /* double move */ 840 #endif 841 | (new_insns[0] & 0x001f0000) 842 | (MIPS_COP_0_OSSCRATCH << 11) | (0 << 0); 843 844 /* [1] = [ls][dw] rX, offset(rX) */ 845 new_insns[1] = (new_insns[1] & 0xffff0000) | offset; 846 847 return true; 848 } 849 #endif /* MULTIPROCESSOR */ 850 851 /* 852 * The following changes all lX rN, L_CPU(MIPS_CURLWP) [curlwp->l_cpu] 853 * to [d]mfc0 rN, $22 [MIPS_COP_0_OSSCRATCH] 854 * 855 * the mfc0 is 3 cycles shorter than the load. 856 */ 857 #define LOAD_CURCPU_0 ((MIPS_CURLWP_REG << 21) | offsetof(lwp_t, l_cpu)) 858 #define MFC0_CURCPU_0 ((OP_COP0 << 26) | (MIPS_COP_0_OSSCRATCH << 11)) 859 #ifdef _LP64 860 #define LOAD_CURCPU ((uint32_t)(OP_LD << 26) | LOAD_CURCPU_0) 861 #define MFC0_CURCPU ((uint32_t)(OP_DMF << 21) | MFC0_CURCPU_0) 862 #else 863 #define LOAD_CURCPU ((uint32_t)(OP_LW << 26) | LOAD_CURCPU_0) 864 #define MFC0_CURCPU ((uint32_t)(OP_MF << 21) | MFC0_CURCPU_0) 865 #endif 866 #define LOAD_CURCPU_MASK 0xffe0ffff 867 868 static void 869 rmixl_fixup_curcpu(void) 870 { 871 extern uint32_t _ftext[]; 872 extern uint32_t _etext[]; 873 874 for (uint32_t *insnp = _ftext; insnp < _etext; insnp++) { 875 const uint32_t insn = *insnp; 876 if (__predict_false((insn & LOAD_CURCPU_MASK) == LOAD_CURCPU)) { 877 /* 878 * Since the register to loaded is located in bits 879 * 16-20 for the mfc0 and the load instruction we can 880 * just change the instruction bits around it. 881 */ 882 *insnp = insn ^ LOAD_CURCPU ^ MFC0_CURCPU; 883 mips_icache_sync_range((vaddr_t)insnp, 4); 884 } 885 } 886 } 887 888 /* 889 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 890 * 891 * we simply build a new table of segs, then copy it back over the given one 892 * this is inefficient but simple and called only a few times 893 * 894 * note: 'last' here means 1st addr past the end of the segment (start+size) 895 */ 896 static u_int 897 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 898 u_quad_t resv_first, u_quad_t resv_last) 899 { 900 u_quad_t first, last; 901 int new_nsegs=0; 902 int resv_flag; 903 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 904 905 for (u_int i=0; i < nsegs; i++) { 906 resv_flag = 0; 907 first = trunc_page(segs[i].start); 908 last = round_page(segs[i].start + segs[i].size); 909 910 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 911 if ((resv_first <= first) && (resv_last >= last)) { 912 /* whole segment is resverved */ 913 continue; 914 } 915 if ((resv_first > first) && (resv_first < last)) { 916 u_quad_t new_last; 917 918 /* 919 * reserved start in segment 920 * salvage the leading fragment 921 */ 922 resv_flag = 1; 923 new_last = last - (last - resv_first); 924 KASSERT (new_last > first); 925 new_segs[new_nsegs].start = first; 926 new_segs[new_nsegs].size = new_last - first; 927 new_nsegs++; 928 } 929 if ((resv_last > first) && (resv_last < last)) { 930 u_quad_t new_first; 931 932 /* 933 * reserved end in segment 934 * salvage the trailing fragment 935 */ 936 resv_flag = 1; 937 new_first = first + (resv_last - first); 938 KASSERT (last > (new_first + NBPG)); 939 new_segs[new_nsegs].start = new_first; 940 new_segs[new_nsegs].size = last - new_first; 941 new_nsegs++; 942 } 943 if (resv_flag == 0) { 944 /* 945 * nothing reserved here, take it all 946 */ 947 new_segs[new_nsegs].start = first; 948 new_segs[new_nsegs].size = last - first; 949 new_nsegs++; 950 } 951 952 } 953 954 memcpy(segs, new_segs, sizeof(new_segs)); 955 956 return new_nsegs; 957 } 958 959 #if (MIPS64_XLP) > 0 960 static void 961 rmixlp_physaddr_pcie_cfg_init(struct extent *ext) 962 { 963 struct rmixl_config * const rcp = &rmixl_configuration; 964 965 uint64_t xbase = RMIXLP_SBC_PCIE_CFG_TO_PA( 966 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_CFG_BASE)); 967 uint64_t xlimit = RMIXLP_SBC_PCIE_CFG_TO_PA( 968 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_CFG_LIMIT)); 969 970 if (xlimit < xbase || xbase == 0) 971 return; /* not enabled */ 972 973 uint64_t xsize = RMIXLP_SBC_PCIE_CFG_SIZE(xbase, xlimit); 974 975 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 976 "pci-cfg", xbase, xsize >> 20); 977 978 rmixl_physaddr_add(ext, "pcicfg", &rcp->rc_pci_cfg, xbase, xsize); 979 } 980 981 static void 982 rmixlp_physaddr_pcie_ecfg_init(struct extent *ext) 983 { 984 struct rmixl_config * const rcp = &rmixl_configuration; 985 986 uint64_t xbase = RMIXLP_SBC_PCIE_ECFG_TO_PA( 987 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_ECFG_BASE)); 988 uint64_t xlimit = RMIXLP_SBC_PCIE_ECFG_TO_PA( 989 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_PCIE_ECFG_LIMIT)); 990 991 if (xlimit < xbase || xbase == 0) 992 return; /* not enabled */ 993 994 uint64_t xsize = RMIXLP_SBC_PCIE_ECFG_SIZE(xbase, xlimit); 995 996 KASSERT(rcp->rc_pci_ecfg.r_pbase == xbase); 997 998 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 999 "pci-ecfg", xbase, xsize >> 20); 1000 1001 rmixl_physaddr_add(ext, "pciecfg", &rcp->rc_pci_ecfg, xbase, xsize); 1002 } 1003 1004 static void 1005 rmixlp_physaddr_pcie_mem_init(struct extent *ext) 1006 { 1007 struct rmixl_config * const rcp = &rmixl_configuration; 1008 for (size_t i = 0; i < RMIXLP_SBC_NPCIE_MEM; i++) { 1009 uint64_t xbase = RMIXLP_SBC_PCIE_MEM_TO_PA( 1010 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1011 RMIXLP_SBC_PCIE_MEM_BASEn(i))); 1012 uint64_t xlimit = RMIXLP_SBC_PCIE_MEM_TO_PA( 1013 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1014 RMIXLP_SBC_PCIE_MEM_LIMITn(i))); 1015 1016 if (xlimit < xbase || xbase == 0) 1017 continue; /* not enabled */ 1018 1019 uint64_t xsize = RMIXLP_SBC_PCIE_MEM_SIZE(xbase, xlimit); 1020 1021 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1022 "pci-mem", i, xbase, xsize >> 20); 1023 1024 rmixl_physaddr_add(ext, "pcimem", &rcp->rc_pci_link_mem[i], 1025 xbase, xsize); 1026 } 1027 } 1028 1029 static void 1030 rmixlp_physaddr_pcie_io_init(struct extent *ext) 1031 { 1032 struct rmixl_config * const rcp = &rmixl_configuration; 1033 for (size_t i = 0; i < RMIXLP_SBC_NPCIE_IO; i++) { 1034 uint64_t xbase = RMIXLP_SBC_PCIE_IO_TO_PA( 1035 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1036 RMIXLP_SBC_PCIE_IO_BASEn(i))); 1037 uint64_t xlimit = RMIXLP_SBC_PCIE_IO_TO_PA( 1038 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1039 RMIXLP_SBC_PCIE_IO_LIMITn(i))); 1040 1041 if (xlimit < xbase || xbase == 0) 1042 continue; /* not enabled */ 1043 1044 uint64_t xsize = RMIXLP_SBC_PCIE_IO_SIZE(xbase, xlimit); 1045 1046 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1047 "pci-io", i, xbase, xsize >> 20); 1048 1049 rmixl_physaddr_add(ext, "pci-io", &rcp->rc_pci_link_io[i], 1050 xbase, xsize); 1051 } 1052 } 1053 1054 static void 1055 rmixlp_physaddr_srio_mem_init(struct extent *ext) 1056 { 1057 struct rmixl_config * const rcp = &rmixl_configuration; 1058 uint64_t xbase = RMIXLP_SBC_SRIO_MEM_TO_PA( 1059 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_SRIO_MEM_BASE)); 1060 uint64_t xlimit = RMIXLP_SBC_SRIO_MEM_TO_PA( 1061 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_SRIO_MEM_LIMIT)); 1062 1063 if (xlimit < xbase || xbase == 0) 1064 return; /* not enabled */ 1065 1066 uint64_t xsize = RMIXLP_SBC_SRIO_MEM_SIZE(xbase, xlimit); 1067 1068 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 1069 "srio-mem", xbase, xsize >> 20); 1070 1071 rmixl_physaddr_add(ext, "sriomem", &rcp->rc_srio_mem, xbase, xsize); 1072 } 1073 1074 static void 1075 rmixlp_physaddr_nor_init(struct extent *ext) 1076 { 1077 struct rmixl_config * const rcp = &rmixl_configuration; 1078 for (size_t i = 0; i < RMIXLP_NOR_NCS; i++) { 1079 uint64_t xbase = RMIXLP_NOR_CS_ADDRESS_TO_PA( 1080 rmixlp_read_4(RMIXLP_NOR_PCITAG, 1081 RMIXLP_NOR_CS_BASEADDRESSn(i))); 1082 uint64_t xlimit = RMIXLP_NOR_CS_ADDRESS_TO_PA( 1083 rmixlp_read_4(RMIXLP_NOR_PCITAG, 1084 RMIXLP_NOR_CS_BASELIMITn(i))); 1085 1086 if (xlimit < xbase || xbase == 0) 1087 continue; /* not enabled */ 1088 1089 uint64_t xsize = RMIXLP_NOR_CS_SIZE(xbase, xlimit); 1090 1091 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__, 1092 "nor", i, xbase, xsize >> 20); 1093 1094 rmixl_physaddr_add(ext, "nor", &rcp->rc_norflash[i], 1095 xbase, xsize); 1096 } 1097 } 1098 1099 static uint64_t 1100 rmixlp_physaddr_dram_init(struct extent *ext) 1101 { 1102 uint64_t memsize = 0; 1103 /* 1104 * grab regions per DRAM BARs 1105 */ 1106 phys_ram_seg_t *mp = mem_clusters; 1107 for (u_int i = 0; i < RMIXLP_SBC_NDRAM; i++) { 1108 uint64_t xbase = 1109 RMIXLP_SBC_DRAM_TO_PA( 1110 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1111 RMIXLP_SBC_DRAM_BASEn(i))); 1112 uint64_t xlimit = 1113 RMIXLP_SBC_DRAM_TO_PA( 1114 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1115 RMIXLP_SBC_DRAM_LIMITn(i))); 1116 1117 if (xlimit < xbase) 1118 continue; /* not enabled */ 1119 1120 mp->start = xbase; 1121 mp->size = RMIXLP_SBC_DRAM_SIZE(xbase, xlimit); 1122 1123 memsize += mp->size; 1124 1125 u_long base = mp->start >> 20; 1126 u_long size = mp->size >> 20; 1127 1128 mp++; 1129 1130 DPRINTF("%s: dram %u: 0x%05lx00000:%lu MB\n", 1131 __func__, i, base, size); 1132 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1133 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1134 "failed", __func__, ext, base, size, EX_NOWAIT); 1135 } 1136 1137 mem_cluster_cnt = mp - mem_clusters; 1138 return memsize; 1139 } 1140 #endif /* MIPS64_XLP */ 1141 1142 #if (MIPS64_XLR + MIPS64_XLS) > 0 1143 static uint64_t 1144 rmixl_physaddr_dram_init(struct extent *ext) 1145 { 1146 uint64_t memsize = 0; 1147 /* 1148 * grab regions per DRAM BARs 1149 */ 1150 phys_ram_seg_t *mp = mem_clusters; 1151 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 1152 uint32_t r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 1153 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 1154 continue; /* not enabled */ 1155 1156 mp->start = DRAM_BAR_TO_BASE((uint64_t)r); 1157 mp->size = DRAM_BAR_TO_SIZE((uint64_t)r); 1158 1159 u_long base = mp->start >> 20; 1160 u_long size = mp->size >> 20; 1161 1162 memsize += mp->size; 1163 1164 mp++; 1165 1166 DPRINTF("%s: dram %u: 0x%08x -- 0x%010lx:%lu MB\n", 1167 __func__, i, r, base * (1024 * 1024), size); 1168 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 1169 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 1170 "failed", __func__, ext, base, size, EX_NOWAIT); 1171 } 1172 1173 mem_cluster_cnt = mp - mem_clusters; 1174 1175 return memsize; 1176 } 1177 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1178 1179 /* 1180 * create an extent for physical address space 1181 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 1182 * allocate the regions where we have known functions (DRAM, IO, etc) 1183 * what remains can be allocated as needed for other stuff 1184 * e.g. to configure BARs that are not already initialized and enabled. 1185 */ 1186 static uint64_t 1187 rmixl_physaddr_init(void) 1188 { 1189 struct extent *ext; 1190 unsigned long start = 0UL; 1191 unsigned long end = (__BIT(40) / (1024 * 1024)) - 1; 1192 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1193 uint64_t memsize; 1194 1195 ext = extent_create("physaddr", start, end, M_DEVBUF, 1196 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 1197 EX_NOWAIT | EX_NOCOALESCE); 1198 1199 if (ext == NULL) 1200 panic("%s: extent_create failed", __func__); 1201 1202 if (is_xlp_p) { 1203 #if (MIPS64_XLP) > 0 1204 memsize = rmixlp_physaddr_dram_init(ext); 1205 rmixlp_physaddr_pcie_cfg_init(ext); 1206 rmixlp_physaddr_pcie_ecfg_init(ext); 1207 rmixlp_physaddr_pcie_mem_init(ext); 1208 rmixlp_physaddr_pcie_io_init(ext); 1209 rmixlp_physaddr_srio_mem_init(ext); 1210 rmixlp_physaddr_nor_init(ext); 1211 #else 1212 memsize = 0; 1213 #endif /* MIPS64_XLP */ 1214 } else { 1215 #if (MIPS64_XLR + MIPS64_XLS) > 0 1216 memsize = rmixl_physaddr_dram_init(ext); 1217 1218 /* 1219 * get chip-dependent physaddr regions 1220 */ 1221 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 1222 case CIDFL_RMI_TYPE_XLR: 1223 #if NRMIXL_PCIX 1224 rmixl_physaddr_init_pcix(ext); 1225 #endif 1226 break; 1227 case CIDFL_RMI_TYPE_XLS: 1228 #if NRMIXL_PCIE 1229 rmixl_physaddr_init_pcie(ext); 1230 #endif 1231 break; 1232 default: 1233 panic("%s: unknown chip type %d", __func__, 1234 cpu_rmixl_chip_type(mips_options.mips_cpu)); 1235 } 1236 #else 1237 memsize = 0; 1238 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1239 } 1240 1241 /* 1242 * at this point all regions left in "physaddr" extent 1243 * are unused holes in the physical adress space 1244 * available for use as needed. 1245 */ 1246 rmixl_configuration.rc_phys_ex = ext; 1247 #ifdef MACHDEP_DEBUG 1248 extent_print(ext); 1249 #endif 1250 return memsize; 1251 } 1252 1253 static uint64_t 1254 rmixlfw_init(int64_t infop) 1255 { 1256 struct rmixl_config * const rcp = &rmixl_configuration; 1257 const bool is_xlp_p = cpu_rmixlp(mips_options.mips_cpu); 1258 1259 #ifdef MULTIPROCESSOR 1260 rmixl_get_wakeup_info(rcp); 1261 #endif 1262 1263 infop |= MIPS_KSEG0_START; 1264 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 1265 1266 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 1267 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 1268 if (rmiclfw_psb_id[i].psb_version == 1269 rcp->rc_psb_info.psb_version) { 1270 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 1271 goto found; 1272 } 1273 } 1274 1275 if (is_xlp_p) { 1276 #if (MIPS64_XLP) > 0 1277 rcp->rc_pci_ecfg.r_pbase = RMIXLP_SBC_PCIE_ECFG_PBASE; 1278 #endif /* MIPS64_XLP */ 1279 } else { 1280 #if (MIPS64_XLR + MIPS64_XLS) > 0 1281 rcp->rc_io.r_pbase = RMIXL_IO_DEV_PBASE; 1282 #endif /* (MIPS64_XLR + MIPS64_XLS) > 0 */ 1283 } 1284 1285 #ifdef DIAGNOSTIC 1286 printf("\nWARNING: untested psb_version: %#"PRIx64"\n", 1287 rcp->rc_psb_info.psb_version); 1288 #endif 1289 1290 #ifdef MEMSIZE 1291 /* XXX trust and use MEMSIZE */ 1292 mem_clusters[0].start = 0; 1293 mem_clusters[0].size = MEMSIZE; 1294 mem_cluster_cnt = 1; 1295 return MEMSIZE; 1296 #else 1297 uint64_t memsize = 0; 1298 for (size_t i = 0; i < mem_cluster_cnt; i++) { 1299 memsize += mem_clusters[i].size; 1300 } 1301 if (memsize) 1302 return memsize; 1303 1304 printf("\nERROR: configure MEMSIZE\n"); 1305 cpu_reboot(RB_HALT, NULL); 1306 /* NOTREACHED */ 1307 #endif 1308 1309 found: 1310 rcp->rc_io.r_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 1311 DPRINTF("\ninfop: %#"PRIx64"\n", infop); 1312 #ifdef DIAGNOSTIC 1313 printf("\nrecognized psb_version=%#"PRIx64", psb_type=%s\n", 1314 rcp->rc_psb_info.psb_version, 1315 rmixlfw_psb_type_name(rcp->rc_psb_type)); 1316 #endif 1317 1318 return mem_clusters_init( 1319 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 1320 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 1321 } 1322 1323 void 1324 rmixlfw_mmap_print(const char *mapname, rmixlfw_mmap_t *map) 1325 { 1326 #ifdef MACHDEP_DEBUG 1327 for (size_t i=0; i < map->nmmaps; i++) { 1328 printf("%s[%zu]: %#"PRIx64", %#"PRIx64", %#x\n", 1329 mapname, i, map->entry[i].start, map->entry[i].size, 1330 map->entry[i].type); 1331 } 1332 #endif 1333 } 1334 1335 /* 1336 * mem_clusters_init 1337 * 1338 * initialize mem_clusters[] table based on memory address mapping 1339 * provided by boot firmware. 1340 * 1341 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 1342 * these will be limited by MEMSIZE if it is configured. 1343 * if neither are available, just use MEMSIZE. 1344 */ 1345 static uint64_t 1346 mem_clusters_init( 1347 rmixlfw_mmap_t *psb_physaddr_map, 1348 rmixlfw_mmap_t *avail_mem_map) 1349 { 1350 rmixlfw_mmap_t *map = NULL; 1351 const char *mapname; 1352 uint64_t sz; 1353 uint64_t sum; 1354 u_int cnt; 1355 #ifdef MEMSIZE 1356 uint64_t memsize = MEMSIZE; 1357 #endif 1358 1359 #ifdef MACHDEP_DEBUG 1360 printf("psb_physaddr_map: %p\n", psb_physaddr_map); 1361 #endif 1362 if (psb_physaddr_map != NULL) { 1363 map = psb_physaddr_map; 1364 mapname = "psb_physaddr_map"; 1365 rmixlfw_mmap_print(mapname, map); 1366 } 1367 #ifdef DIAGNOSTIC 1368 else { 1369 printf("WARNING: no psb_physaddr_map\n"); 1370 } 1371 #endif 1372 1373 #ifdef MACHDEP_DEBUG 1374 printf("avail_mem_map: %p\n", avail_mem_map); 1375 #endif 1376 if (avail_mem_map != NULL) { 1377 map = avail_mem_map; 1378 mapname = "avail_mem_map"; 1379 rmixlfw_mmap_print(mapname, map); 1380 } 1381 #ifdef DIAGNOSTIC 1382 else { 1383 printf("WARNING: no avail_mem_map\n"); 1384 } 1385 #endif 1386 1387 if (map == NULL) { 1388 #ifndef MEMSIZE 1389 printf("panic: no firmware memory map, " 1390 "must configure MEMSIZE\r\n"); 1391 for(;;); /* XXX */ 1392 #else 1393 #ifdef DIAGNOSTIC 1394 printf("WARNING: no avail_mem_map, using MEMSIZE\n"); 1395 #endif 1396 1397 mem_clusters[0].start = 0; 1398 mem_clusters[0].size = MEMSIZE; 1399 mem_cluster_cnt = 1; 1400 return MEMSIZE; 1401 #endif /* MEMSIZE */ 1402 } 1403 1404 #ifdef DIAGNOSTIC 1405 printf("using %s\n", mapname); 1406 #endif 1407 #ifdef MACHDEP_DEBUG 1408 printf("memory clusters:\n"); 1409 #endif 1410 sum = 0; 1411 cnt = 0; 1412 for (uint32_t i=0; i < map->nmmaps; i++) { 1413 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 1414 continue; 1415 mem_clusters[cnt].start = map->entry[i].start; 1416 sz = map->entry[i].size; 1417 sum += sz; 1418 mem_clusters[cnt].size = sz; 1419 #ifdef MACHDEP_DEBUG 1420 printf("[%u]: %#"PRIx64", %#"PRIx64", %#"PRIx64"\n", 1421 i, mem_clusters[cnt].start, sz, sum); 1422 #endif 1423 #ifdef MEMSIZE 1424 /* 1425 * configurably limit memsize 1426 */ 1427 if (sum == memsize) 1428 break; 1429 if (sum > memsize) { 1430 uint64_t tmp; 1431 1432 tmp = sum - memsize; 1433 sz -= tmp; 1434 sum -= tmp; 1435 mem_clusters[cnt].size = sz; 1436 cnt++; 1437 break; 1438 } 1439 #endif 1440 cnt++; 1441 } 1442 mem_cluster_cnt = cnt; 1443 return sum; 1444 } 1445 1446 #ifdef MULTIPROCESSOR 1447 /* 1448 * RMI firmware passes wakeup info structure in CP0 OS Scratch reg #7 1449 * they do not explicitly give us the size of the wakeup area. 1450 * we "know" that firmware loader sets wip->gp thusly: 1451 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 1452 * so 1453 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 1454 * Only the "master" cpu runs this function, so 1455 * vcpu = wip->master_cpu 1456 */ 1457 void 1458 rmixl_get_wakeup_info(struct rmixl_config *rcp) 1459 { 1460 volatile rmixlfw_cpu_wakeup_info_t *wip; 1461 int32_t scratch_7; 1462 intptr_t end; 1463 1464 __asm__ volatile( 1465 ".set push" "\n" 1466 ".set noreorder" "\n" 1467 ".set mips64" "\n" 1468 "dmfc0 %0, $22, 7" "\n" 1469 ".set pop" "\n" 1470 : "=r"(scratch_7)); 1471 1472 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 1473 (intptr_t)scratch_7; 1474 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 1475 1476 if (wip->valid == 1) { 1477 rcp->rc_cpu_wakeup_end = (const void *)end; 1478 rcp->rc_cpu_wakeup_info = wip; 1479 } 1480 }; 1481 1482 #ifdef MACHDEP_DEBUG 1483 static void 1484 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 1485 { 1486 int i; 1487 1488 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 1489 1490 printf("cpu_status %#x\n", wip->cpu_status); 1491 printf("valid: %d\n", wip->valid); 1492 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 1493 wip->entry.addr, 1494 wip->entry.args, 1495 wip->entry.sp, 1496 wip->entry.gp); 1497 printf("master_cpu %d\n", wip->master_cpu); 1498 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 1499 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 1500 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 1501 printf("argc %d\n", wip->argc); 1502 printf("argv:"); 1503 for (i=0; i < wip->argc; i++) 1504 printf(" %#x", wip->argv[i]); 1505 printf("\n"); 1506 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 1507 printf("tlb_map:\n"); 1508 for (i=0; i < wip->valid_tlb_entries; i++) { 1509 volatile const struct lib_cpu_tlb_mapping *m = 1510 &wip->tlb_map[i]; 1511 printf(" %d", m->page_size); 1512 printf(", %d", m->asid); 1513 printf(", %d", m->coherency); 1514 printf(", %d", m->coherency); 1515 printf(", %d", m->attr); 1516 printf(", %#x", m->virt); 1517 printf(", %#"PRIx64"\n", m->phys); 1518 } 1519 printf("elf segs:\n"); 1520 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 1521 volatile const struct core_segment_info *e = 1522 &wip->seg_info[i]; 1523 printf(" %#"PRIx64"", e->vaddr); 1524 printf(", %#"PRIx64"", e->memsz); 1525 printf(", %#x\n", e->flags); 1526 } 1527 printf("envc %d\n", wip->envc); 1528 for (i=0; i < wip->envc; i++) 1529 printf(" %#x \"%s\"", wip->envs[i], 1530 (char *)(intptr_t)(int32_t)(wip->envs[i])); 1531 printf("\n"); 1532 printf("app_mode %d\n", wip->app_mode); 1533 printf("printk_lock %#x\n", wip->printk_lock); 1534 printf("kseg_master %d\n", wip->kseg_master); 1535 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 1536 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 1537 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 1538 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 1539 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 1540 printf("loader_lock %#x\n", wip->loader_lock); 1541 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 1542 printf("unused_0 %#x\n", wip->unused_0); 1543 } 1544 #endif /* MACHDEP_DEBUG */ 1545 #endif /* MULTIPROCESSOR */ 1546 1547 void 1548 consinit(void) 1549 { 1550 1551 /* 1552 * Everything related to console initialization is done 1553 * in mach_init(). 1554 */ 1555 } 1556 1557 /* 1558 * Allocate memory for variable-sized tables, 1559 */ 1560 void 1561 cpu_startup() 1562 { 1563 vaddr_t minaddr, maxaddr; 1564 char pbuf[9]; 1565 1566 /* 1567 * Good {morning,afternoon,evening,night}. 1568 */ 1569 printf("%s%s", copyright, version); 1570 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 1571 printf("total memory = %s\n", pbuf); 1572 1573 /* 1574 * Virtual memory is bootstrapped -- notify the bus spaces 1575 * that memory allocation is now safe. 1576 */ 1577 rmixl_configuration.rc_mallocsafe = 1; 1578 1579 minaddr = 0; 1580 /* 1581 * Allocate a submap for physio. 1582 */ 1583 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 1584 VM_PHYS_SIZE, 0, FALSE, NULL); 1585 1586 /* 1587 * (No need to allocate an mbuf cluster submap. Mbuf clusters 1588 * are allocated via the pool allocator, and we use XKSEG to 1589 * map those pages.) 1590 */ 1591 1592 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 1593 printf("avail memory = %s\n", pbuf); 1594 } 1595 1596 int waittime = -1; 1597 1598 void 1599 cpu_reboot(int howto, char *bootstr) 1600 { 1601 1602 /* Take a snapshot before clobbering any registers. */ 1603 savectx(lwp_getpcb(curlwp)); 1604 1605 if (cold) { 1606 howto |= RB_HALT; 1607 goto haltsys; 1608 } 1609 1610 /* If "always halt" was specified as a boot flag, obey. */ 1611 if (boothowto & RB_HALT) 1612 howto |= RB_HALT; 1613 1614 boothowto = howto; 1615 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 1616 waittime = 0; 1617 vfs_shutdown(); 1618 1619 /* 1620 * If we've been adjusting the clock, the todr 1621 * will be out of synch; adjust it now. 1622 */ 1623 resettodr(); 1624 } 1625 1626 splhigh(); 1627 1628 if (howto & RB_DUMP) 1629 dumpsys(); 1630 1631 haltsys: 1632 doshutdownhooks(); 1633 1634 if (howto & RB_HALT) { 1635 printf("\n"); 1636 printf("The operating system has halted.\n"); 1637 printf("Please press any key to reboot.\n\n"); 1638 cnpollc(1); /* For proper keyboard command handling */ 1639 cngetc(); 1640 cnpollc(0); 1641 } 1642 1643 printf("rebooting...\n\n"); 1644 1645 rmixl_reset(); 1646 } 1647 1648 /* 1649 * goodbye world 1650 */ 1651 void __attribute__((__noreturn__)) 1652 rmixl_reset(void) 1653 { 1654 uint32_t r; 1655 1656 if (MIPSNN_GET(CFG_AR, mips3_cp0_config_read()) == MIPSNN_CFG_AR_REV2) { 1657 rmixlp_write_4(RMIXLP_SM_PCITAG, RMIXLP_SM_CHIP_RESET, 1); 1658 DELAY(1000000); 1659 printf("%s: resorting to plan b!", __func__); 1660 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x18035100) = 1; 1661 __asm __volatile("sync"); 1662 } else { 1663 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1664 r |= RMIXL_GPIO_RESET_RESET; 1665 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1666 } 1667 1668 printf("soft reset failed, spinning...\n"); 1669 for (;;); 1670 } 1671 1672 #ifdef __HAVE_PCI_CONF_HOOK 1673 int 1674 rmixl_pci_conf_hook(void *v, int bus, int device, int function, pcireg_t id) 1675 { 1676 return PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM; 1677 } 1678 #endif 1679
Indexes created Sat Nov 01 20:09:51 GMT 2025