machdep.c revision 1.7
1 /* $NetBSD: machdep.c,v 1.7 2011/02/20 07:48:35 matt Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1988 University of Utah. 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * the Systems Programming Group of the University of Utah Computer 45 * Science Department, The Mach Operating System project at 46 * Carnegie-Mellon University and Ralph Campbell. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 73 * from: Utah Hdr: machdep.c 1.63 91/04/24 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.7 2011/02/20 07:48:35 matt Exp $"); 78 79 #define __INTR_PRIVATE 80 81 #include "opt_multiprocessor.h" 82 #include "opt_ddb.h" 83 #include "opt_com.h" 84 #include "opt_execfmt.h" 85 #include "opt_memsize.h" 86 #include "rmixl_pcix.h" 87 #include "rmixl_pcie.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/kernel.h> 92 #include <sys/buf.h> 93 #include <sys/reboot.h> 94 #include <sys/mount.h> 95 #include <sys/kcore.h> 96 #include <sys/boot_flag.h> 97 #include <sys/termios.h> 98 #include <sys/ksyms.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/extent.h> 102 #include <sys/malloc.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <dev/cons.h> 107 108 #include "ksyms.h" 109 110 #if NKSYMS || defined(DDB) || defined(LKM) 111 #include <machine/db_machdep.h> 112 #include <ddb/db_extern.h> 113 #endif 114 115 #include <machine/cpu.h> 116 #include <machine/psl.h> 117 118 #include "com.h" 119 #if NCOM == 0 120 #error no serial console 121 #endif 122 123 #include <dev/ic/comreg.h> 124 #include <dev/ic/comvar.h> 125 126 #include <mips/include/intr.h> 127 128 #include <mips/rmi/rmixlreg.h> 129 #include <mips/rmi/rmixlvar.h> 130 #include <mips/rmi/rmixl_intr.h> 131 #include <mips/rmi/rmixl_firmware.h> 132 #include <mips/rmi/rmixl_comvar.h> 133 #include <mips/rmi/rmixl_pcievar.h> 134 #include <mips/rmi/rmixl_pcixvar.h> 135 136 #ifdef MACHDEP_DEBUG 137 int machdep_debug=MACHDEP_DEBUG; 138 # define DPRINTF(x) do { if (machdep_debug) printf x ; } while(0) 139 #else 140 # define DPRINTF(x) 141 #endif 142 143 #ifndef CONSFREQ 144 # define CONSFREQ 66000000 145 #endif 146 #ifndef CONSPEED 147 # define CONSPEED 38400 148 #endif 149 #ifndef CONMODE 150 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 151 #endif 152 #ifndef CONSADDR 153 # define CONSADDR RMIXL_IO_DEV_UART_1 154 #endif 155 156 int comcnfreq = CONSFREQ; 157 int comcnspeed = CONSPEED; 158 tcflag_t comcnmode = CONMODE; 159 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 160 161 struct rmixl_config rmixl_configuration; 162 163 164 /* 165 * array of tested firmware versions 166 * if you find new ones and they work 167 * please add them 168 */ 169 typedef struct rmiclfw_psb_id { 170 uint64_t psb_version; 171 rmixlfw_psb_type_t psb_type; 172 } rmiclfw_psb_id_t; 173 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 174 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 175 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 176 { 0x4b67d03200000056ULL, PSB_TYPE_RMI }, 177 { 0x4c17058b00000056ULL, PSB_TYPE_RMI }, 178 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 179 { 0x4b8ead3100000056ULL, PSB_TYPE_DELL }, 180 }; 181 #define RMICLFW_PSB_VERSIONS_LEN \ 182 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 183 184 /* 185 * storage for fixed extent used to allocate physical address regions 186 * because extent(9) start and end values are u_long, they are only 187 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 188 * address is 40 bits wide. So the "physaddr" map stores regions 189 * in units of megabytes. 190 */ 191 static u_long rmixl_physaddr_storage[ 192 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 193 ]; 194 195 /* For sysctl_hw. */ 196 extern char cpu_model[]; 197 198 /* Our exported CPU info; we can have only one. */ 199 struct cpu_info cpu_info_store; 200 201 /* Maps for VM objects. */ 202 struct vm_map *phys_map = NULL; 203 204 int physmem; /* Total physical memory */ 205 206 int netboot; /* Are we netbooting? */ 207 208 209 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 210 u_quad_t mem_cluster_maxaddr; 211 u_int mem_cluster_cnt; 212 213 214 void configure(void); 215 void mach_init(int, int32_t *, void *, int64_t); 216 static uint64_t rmixlfw_init(int64_t); 217 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 218 static void __attribute__((__noreturn__)) rmixl_reset(void); 219 static void rmixl_physaddr_init(void); 220 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 221 void rmixlfw_mmap_print(rmixlfw_mmap_t *); 222 223 224 #ifdef MULTIPROCESSOR 225 static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2]); 226 void rmixl_get_wakeup_info(struct rmixl_config *); 227 #ifdef MACHDEP_DEBUG 228 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 229 #endif /* MACHDEP_DEBUG */ 230 #endif /* MULTIPROCESSOR */ 231 232 /* 233 * Do all the stuff that locore normally does before calling main(). 234 */ 235 void 236 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 237 { 238 struct rmixl_config *rcp = &rmixl_configuration; 239 void *kernend; 240 uint64_t memsize; 241 extern char edata[], end[]; 242 243 rmixl_pcr_init_core(); 244 245 /* 246 * Clear the BSS segment. 247 */ 248 kernend = (void *)mips_round_page(end); 249 memset(edata, 0, (char *)kernend - edata); 250 251 /* 252 * Set up the exception vectors and CPU-specific function 253 * vectors early on. We need the wbflush() vector set up 254 * before comcnattach() is called (or at least before the 255 * first printf() after that is called). 256 * Also clears the I+D caches. 257 * 258 * specify chip-specific EIRR/EIMR based spl functions 259 */ 260 #ifdef MULTIPROCESSOR 261 mips_vector_init(&rmixl_splsw, true); 262 #else 263 mips_vector_init(&rmixl_splsw, false); 264 #endif 265 266 /* mips_vector_init initialized mips_options */ 267 strcpy(cpu_model, mips_options.mips_cpu->cpu_name); 268 269 /* get system info from firmware */ 270 memsize = rmixlfw_init(infop); 271 272 /* set the VM page size */ 273 uvm_setpagesize(); 274 275 physmem = btoc(memsize); 276 277 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 278 279 #if NCOM > 0 280 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 281 COM_TYPE_NORMAL, comcnmode); 282 #endif 283 284 printf("\nNetBSD/rmixl\n"); 285 printf("memsize = %#"PRIx64"\n", memsize); 286 #ifdef MEMLIMIT 287 printf("memlimit = %#"PRIx64"\n", (uint64_t)MEMLIMIT); 288 #endif 289 290 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 291 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 292 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 293 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 294 rcp->rc_cpu_wakeup_info, 295 rcp->rc_cpu_wakeup_end); 296 printf("userapp_cpu_map: %#"PRIx64"\n", 297 rcp->rc_psb_info.userapp_cpu_map); 298 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 299 { 300 register_t sp; 301 asm volatile ("move %0, $sp\n" : "=r"(sp)); 302 printf("sp: %#"PRIx64"\n", sp); 303 } 304 #endif 305 306 rmixl_physaddr_init(); 307 308 /* 309 * Obtain the cpu frequency 310 * Compute the number of ticks for hz. 311 * Compute the delay divisor. 312 * Double the Hz if this CPU runs at twice the 313 * external/cp0-count frequency 314 */ 315 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 316 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 317 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 318 curcpu()->ci_divisor_delay = 319 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 320 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 321 curcpu()->ci_cpu_freq *= 2; 322 323 /* 324 * Look at arguments passed to us and compute boothowto. 325 * - rmixl firmware gives us a 32 bit argv[i], so adapt 326 * by forcing sign extension in cast to (char *) 327 */ 328 boothowto = RB_AUTOBOOT; 329 for (int i = 1; i < argc; i++) { 330 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 331 int howto; 332 /* Ignore superfluous '-', if there is one */ 333 if (*cp == '-') 334 continue; 335 336 howto = 0; 337 BOOT_FLAG(*cp, howto); 338 if (howto != 0) 339 boothowto |= howto; 340 #ifdef DIAGNOSTIC 341 else 342 printf("bootflag '%c' not recognised\n", *cp); 343 #endif 344 } 345 } 346 #ifdef DIAGNOSTIC 347 printf("boothowto %#x\n", boothowto); 348 #endif 349 350 /* 351 * Reserve pages from the VM system. 352 */ 353 354 /* reserve 0..start..kernend pages */ 355 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 356 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 357 358 /* reserve reset exception vector page */ 359 /* should never be in our clusters anyway... */ 360 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 361 0x1FC00000, 0x1FC00000+NBPG); 362 363 #ifdef MULTIPROCEESOR 364 /* reserve the cpu_wakeup_info area */ 365 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 366 (u_quad_t)trunc_page(rcp->rc_cpu_wakeup_info), 367 (u_quad_t)round_page(rcp->rc_cpu_wakeup_end)); 368 #endif 369 370 #ifdef MEMLIMIT 371 /* reserve everything >= MEMLIMIT */ 372 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 373 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 374 #endif 375 376 /* get maximum RAM address from the VM clusters */ 377 mem_cluster_maxaddr = 0; 378 for (u_int i=0; i < mem_cluster_cnt; i++) { 379 u_quad_t tmp = round_page( 380 mem_clusters[i].start + mem_clusters[i].size); 381 if (tmp > mem_cluster_maxaddr) 382 mem_cluster_maxaddr = tmp; 383 } 384 DPRINTF(("mem_cluster_maxaddr %#"PRIx64"\n", mem_cluster_maxaddr)); 385 386 /* 387 * Load mem_clusters[] into the VM system. 388 */ 389 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 390 mem_clusters, mem_cluster_cnt, NULL, 0); 391 392 /* 393 * Initialize error message buffer (at end of core). 394 */ 395 mips_init_msgbuf(); 396 397 pmap_bootstrap(); 398 399 /* 400 * Allocate uarea page for lwp0 and set it. 401 */ 402 mips_init_lwp0_uarea(); 403 404 #if defined(DDB) 405 if (boothowto & RB_KDB) 406 Debugger(); 407 #endif 408 #ifdef MULTIPROCESSOR 409 /* 410 * store (cpu#0) curcpu in COP0 OSSCRATCH0 411 * used in exception vector 412 */ 413 __asm __volatile("dmtc0 %0,$%1" 414 :: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH)); 415 mips_fixup_exceptions(rmixl_fixup_cop0_oscratch); 416 #endif 417 } 418 419 /* 420 * set up Processor Control Regs for this core 421 */ 422 void 423 rmixl_pcr_init_core() 424 { 425 uint32_t r; 426 427 #ifdef MULTIPROCESSOR 428 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0)); 429 /* enable MMU clock gating */ 430 /* 4 threads active -- why needed if Global? */ 431 /* enable global TLB mode */ 432 #else 433 rmixl_mtcr(RMIXL_PCR_THREADEN, 1); /* disable all threads except #0 */ 434 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, 0); /* enable MMU clock gating */ 435 /* set single MMU Thread Mode */ 436 /* TLB is partitioned (1 partition) */ 437 #endif 438 439 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 440 r &= ~__BIT(14); /* disable Unaligned Access */ 441 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 442 443 #if defined(DDB) && defined(MIPS_DDB_WATCH) 444 /* 445 * clear IEU_DEFEATURE[DBE] 446 * this enables COP0 watchpoint to trigger T_WATCH exception 447 * instead of signaling JTAG. 448 */ 449 r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE); 450 r &= ~__BIT(7); 451 rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r); 452 #endif 453 } 454 455 #ifdef MULTIPROCESSOR 456 static bool 457 rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2]) 458 { 459 size_t offset = load_addr - (intptr_t)&cpu_info_store; 460 461 KASSERT(MIPS_KSEG0_P(load_addr)); 462 KASSERT(offset < sizeof(struct cpu_info)); 463 464 /* 465 * Fixup this direct load cpu_info_store to actually get the current 466 * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be 467 * relative from the start of struct cpu_info. 468 */ 469 470 /* [0] = [d]mfc0 rX, $22 (OSScratch) */ 471 new_insns[0] = (020 << 26) 472 #ifdef _LP64 473 | (1 << 21) /* double move */ 474 #endif 475 | (new_insns[0] & 0x001f0000) 476 | (MIPS_COP_0_OSSCRATCH << 11) | (0 << 0); 477 478 /* [1] = [ls][dw] rX, offset(rX) */ 479 new_insns[1] = (new_insns[1] & 0xffff0000) | offset; 480 481 return true; 482 } 483 #endif /* MULTIPROCESSOR */ 484 485 /* 486 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 487 * 488 * we simply build a new table of segs, then copy it back over the given one 489 * this is inefficient but simple and called only a few times 490 * 491 * note: 'last' here means 1st addr past the end of the segment (start+size) 492 */ 493 static u_int 494 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 495 u_quad_t resv_first, u_quad_t resv_last) 496 { 497 u_quad_t first, last; 498 int new_nsegs=0; 499 int resv_flag; 500 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 501 502 for (u_int i=0; i < nsegs; i++) { 503 resv_flag = 0; 504 first = trunc_page(segs[i].start); 505 last = round_page(segs[i].start + segs[i].size); 506 507 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 508 if ((resv_first <= first) && (resv_last >= last)) { 509 /* whole segment is resverved */ 510 continue; 511 } 512 if ((resv_first > first) && (resv_first < last)) { 513 u_quad_t new_last; 514 515 /* 516 * reserved start in segment 517 * salvage the leading fragment 518 */ 519 resv_flag = 1; 520 new_last = last - (last - resv_first); 521 KASSERT (new_last > first); 522 new_segs[new_nsegs].start = first; 523 new_segs[new_nsegs].size = new_last - first; 524 new_nsegs++; 525 } 526 if ((resv_last > first) && (resv_last < last)) { 527 u_quad_t new_first; 528 529 /* 530 * reserved end in segment 531 * salvage the trailing fragment 532 */ 533 resv_flag = 1; 534 new_first = first + (resv_last - first); 535 KASSERT (last > (new_first + NBPG)); 536 new_segs[new_nsegs].start = new_first; 537 new_segs[new_nsegs].size = last - new_first; 538 new_nsegs++; 539 } 540 if (resv_flag == 0) { 541 /* 542 * nothing reserved here, take it all 543 */ 544 new_segs[new_nsegs].start = first; 545 new_segs[new_nsegs].size = last - first; 546 new_nsegs++; 547 } 548 549 } 550 551 memcpy(segs, new_segs, sizeof(new_segs)); 552 553 return new_nsegs; 554 } 555 556 /* 557 * create an extent for physical address space 558 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 559 * allocate the regions where we have known functions (DRAM, IO, etc) 560 * what remains can be allocated as needed for other stuff 561 * e.g. to configure BARs that are not already initialized and enabled. 562 */ 563 static void 564 rmixl_physaddr_init(void) 565 { 566 struct extent *ext; 567 unsigned long start = 0UL; 568 unsigned long end = (__BIT(40) / (1024 * 1024)) -1; 569 u_long base; 570 u_long size; 571 uint32_t r; 572 573 ext = extent_create("physaddr", start, end, M_DEVBUF, 574 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 575 EX_NOWAIT | EX_NOCOALESCE); 576 577 if (ext == NULL) 578 panic("%s: extent_create failed", __func__); 579 580 /* 581 * grab regions per DRAM BARs 582 */ 583 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 584 r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 585 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 586 continue; /* not enabled */ 587 base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024)); 588 size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024)); 589 590 DPRINTF(("%s: %d: %d: 0x%08x -- 0x%010lx:%lu MB\n", 591 __func__, __LINE__, i, r, base * (1024 * 1024), size)); 592 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 593 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 594 "failed", __func__, ext, base, size, EX_NOWAIT); 595 } 596 597 /* 598 * get chip-dependent physaddr regions 599 */ 600 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 601 case CIDFL_RMI_TYPE_XLR: 602 #if NRMIXL_PCIX 603 rmixl_physaddr_init_pcix(ext); 604 #endif 605 break; 606 case CIDFL_RMI_TYPE_XLS: 607 #if NRMIXL_PCIE 608 rmixl_physaddr_init_pcie(ext); 609 #endif 610 break; 611 case CIDFL_RMI_TYPE_XLP: 612 /* XXX TBD */ 613 panic("%s: RMI XLP not yet supported", __func__); 614 } 615 616 /* 617 * at this point all regions left in "physaddr" extent 618 * are unused holes in the physical adress space 619 * available for use as needed. 620 */ 621 rmixl_configuration.rc_phys_ex = ext; 622 #ifdef MACHDEP_DEBUG 623 extent_print(ext); 624 #endif 625 } 626 627 static uint64_t 628 rmixlfw_init(int64_t infop) 629 { 630 struct rmixl_config *rcp = &rmixl_configuration; 631 632 #ifdef MULTIPROCESSOR 633 rmixl_get_wakeup_info(rcp); 634 #endif 635 636 infop |= MIPS_KSEG0_START; 637 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 638 639 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 640 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 641 if (rmiclfw_psb_id[i].psb_version == 642 rcp->rc_psb_info.psb_version) { 643 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 644 goto found; 645 } 646 } 647 648 rcp->rc_io_pbase = RMIXL_IO_DEV_PBASE; 649 rmixl_putchar_init(rcp->rc_io_pbase); 650 651 #ifdef DIAGNOSTIC 652 rmixl_puts("\r\nWARNING: untested psb_version: "); 653 rmixl_puthex64(rcp->rc_psb_info.psb_version); 654 rmixl_puts("\r\n"); 655 #endif 656 657 #ifdef MEMSIZE 658 /* XXX trust and use MEMSIZE */ 659 mem_clusters[0].start = 0; 660 mem_clusters[0].size = MEMSIZE; 661 mem_cluster_cnt = 1; 662 return MEMSIZE; 663 #else 664 rmixl_puts("\r\nERROR: configure MEMSIZE\r\n"); 665 cpu_reboot(RB_HALT, NULL); 666 /* NOTREACHED */ 667 #endif 668 669 found: 670 rcp->rc_io_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 671 rmixl_putchar_init(rcp->rc_io_pbase); 672 #ifdef MACHDEP_DEBUG 673 rmixl_puts("\r\ninfop: "); 674 rmixl_puthex64((uint64_t)(intptr_t)infop); 675 #endif 676 #ifdef DIAGNOSTIC 677 rmixl_puts("\r\nrecognized psb_version="); 678 rmixl_puthex64(rcp->rc_psb_info.psb_version); 679 rmixl_puts(", psb_type="); 680 rmixl_puts(rmixlfw_psb_type_name(rcp->rc_psb_type)); 681 rmixl_puts("\r\n"); 682 #endif 683 684 return mem_clusters_init( 685 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 686 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 687 } 688 689 void 690 rmixlfw_mmap_print(rmixlfw_mmap_t *map) 691 { 692 #ifdef MACHDEP_DEBUG 693 for (uint32_t i=0; i < map->nmmaps; i++) { 694 rmixl_puthex32(i); 695 rmixl_puts(", "); 696 rmixl_puthex64(map->entry[i].start); 697 rmixl_puts(", "); 698 rmixl_puthex64(map->entry[i].size); 699 rmixl_puts(", "); 700 rmixl_puthex32(map->entry[i].type); 701 rmixl_puts("\r\n"); 702 } 703 #endif 704 } 705 706 /* 707 * mem_clusters_init 708 * 709 * initialize mem_clusters[] table based on memory address mapping 710 * provided by boot firmware. 711 * 712 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 713 * these will be limited by MEMSIZE if it is configured. 714 * if neither are available, just use MEMSIZE. 715 */ 716 static uint64_t 717 mem_clusters_init( 718 rmixlfw_mmap_t *psb_physaddr_map, 719 rmixlfw_mmap_t *avail_mem_map) 720 { 721 rmixlfw_mmap_t *map = NULL; 722 const char *mapname; 723 uint64_t sz; 724 uint64_t sum; 725 u_int cnt; 726 #ifdef MEMSIZE 727 uint64_t memsize = MEMSIZE; 728 #endif 729 730 #ifdef MACHDEP_DEBUG 731 rmixl_puts("psb_physaddr_map: "); 732 rmixl_puthex64((uint64_t)(intptr_t)psb_physaddr_map); 733 rmixl_puts("\r\n"); 734 #endif 735 if (psb_physaddr_map != NULL) { 736 map = psb_physaddr_map; 737 mapname = "psb_physaddr_map"; 738 rmixlfw_mmap_print(map); 739 } 740 #ifdef DIAGNOSTIC 741 else { 742 rmixl_puts("WARNING: no psb_physaddr_map\r\n"); 743 } 744 #endif 745 746 #ifdef MACHDEP_DEBUG 747 rmixl_puts("avail_mem_map: "); 748 rmixl_puthex64((uint64_t)(intptr_t)avail_mem_map); 749 rmixl_puts("\r\n"); 750 #endif 751 if (avail_mem_map != NULL) { 752 map = avail_mem_map; 753 mapname = "avail_mem_map"; 754 rmixlfw_mmap_print(map); 755 } 756 #ifdef DIAGNOSTIC 757 else { 758 rmixl_puts("WARNING: no avail_mem_map\r\n"); 759 } 760 #endif 761 762 if (map == NULL) { 763 #ifndef MEMSIZE 764 rmixl_puts("panic: no firmware memory map, " 765 "must configure MEMSIZE\r\n"); 766 for(;;); /* XXX */ 767 #else 768 #ifdef DIAGNOSTIC 769 rmixl_puts("WARNING: no avail_mem_map, " 770 "using MEMSIZE\r\n"); 771 #endif 772 773 mem_clusters[0].start = 0; 774 mem_clusters[0].size = MEMSIZE; 775 mem_cluster_cnt = 1; 776 return MEMSIZE; 777 #endif /* MEMSIZE */ 778 } 779 780 #ifdef DIAGNOSTIC 781 rmixl_puts("using "); 782 rmixl_puts(mapname); 783 rmixl_puts("\r\n"); 784 #endif 785 #ifdef MACHDEP_DEBUG 786 rmixl_puts("memory clusters:\r\n"); 787 #endif 788 sum = 0; 789 cnt = 0; 790 for (uint32_t i=0; i < map->nmmaps; i++) { 791 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 792 continue; 793 mem_clusters[cnt].start = map->entry[i].start; 794 sz = map->entry[i].size; 795 sum += sz; 796 mem_clusters[cnt].size = sz; 797 #ifdef MACHDEP_DEBUG 798 rmixl_puthex32(i); 799 rmixl_puts(": "); 800 rmixl_puthex64(mem_clusters[cnt].start); 801 rmixl_puts(", "); 802 rmixl_puthex64(sz); 803 rmixl_puts(": "); 804 rmixl_puthex64(sum); 805 rmixl_puts("\r\n"); 806 #endif 807 #ifdef MEMSIZE 808 /* 809 * configurably limit memsize 810 */ 811 if (sum == memsize) 812 break; 813 if (sum > memsize) { 814 uint64_t tmp; 815 816 tmp = sum - memsize; 817 sz -= tmp; 818 sum -= tmp; 819 mem_clusters[cnt].size = sz; 820 cnt++; 821 break; 822 } 823 #endif 824 cnt++; 825 } 826 mem_cluster_cnt = cnt; 827 return sum; 828 } 829 830 #ifdef MULTIPROCESSOR 831 /* 832 * RMI firmware passes wakeup info structure in CP0 OS Scratch reg #7 833 * they do not explicitly give us the size of the wakeup area. 834 * we "know" that firmware loader sets wip->gp thusly: 835 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 836 * so 837 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 838 * Only the "master" cpu runs this function, so 839 * vcpu = wip->master_cpu 840 */ 841 void 842 rmixl_get_wakeup_info(struct rmixl_config *rcp) 843 { 844 volatile rmixlfw_cpu_wakeup_info_t *wip; 845 int32_t scratch_7; 846 intptr_t end; 847 848 __asm__ volatile( 849 ".set push" "\n" 850 ".set noreorder" "\n" 851 ".set mips64" "\n" 852 "dmfc0 %0, $22, 7" "\n" 853 ".set pop" "\n" 854 : "=r"(scratch_7)); 855 856 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 857 (intptr_t)scratch_7; 858 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 859 860 if (wip->valid == 1) { 861 rcp->rc_cpu_wakeup_end = (const void *)end; 862 rcp->rc_cpu_wakeup_info = wip; 863 } 864 }; 865 866 #ifdef MACHDEP_DEBUG 867 static void 868 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 869 { 870 int i; 871 872 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 873 874 printf("cpu_status %#x\n", wip->cpu_status); 875 printf("valid: %d\n", wip->valid); 876 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 877 wip->entry.addr, 878 wip->entry.args, 879 wip->entry.sp, 880 wip->entry.gp); 881 printf("master_cpu %d\n", wip->master_cpu); 882 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 883 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 884 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 885 printf("argc %d\n", wip->argc); 886 printf("argv:"); 887 for (i=0; i < wip->argc; i++) 888 printf(" %#x", wip->argv[i]); 889 printf("\n"); 890 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 891 printf("tlb_map:\n"); 892 for (i=0; i < wip->valid_tlb_entries; i++) { 893 volatile const struct lib_cpu_tlb_mapping *m = 894 &wip->tlb_map[i]; 895 printf(" %d", m->page_size); 896 printf(", %d", m->asid); 897 printf(", %d", m->coherency); 898 printf(", %d", m->coherency); 899 printf(", %d", m->attr); 900 printf(", %#x", m->virt); 901 printf(", %#"PRIx64"\n", m->phys); 902 } 903 printf("elf segs:\n"); 904 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 905 volatile const struct core_segment_info *e = 906 &wip->seg_info[i]; 907 printf(" %#"PRIx64"", e->vaddr); 908 printf(", %#"PRIx64"", e->memsz); 909 printf(", %#x\n", e->flags); 910 } 911 printf("envc %d\n", wip->envc); 912 for (i=0; i < wip->envc; i++) 913 printf(" %#x \"%s\"", wip->envs[i], 914 (char *)(intptr_t)(int32_t)(wip->envs[i])); 915 printf("\n"); 916 printf("app_mode %d\n", wip->app_mode); 917 printf("printk_lock %#x\n", wip->printk_lock); 918 printf("kseg_master %d\n", wip->kseg_master); 919 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 920 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 921 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 922 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 923 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 924 printf("loader_lock %#x\n", wip->loader_lock); 925 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 926 printf("unused_0 %#x\n", wip->unused_0); 927 } 928 #endif /* MACHDEP_DEBUG */ 929 #endif /* MULTIPROCESSOR */ 930 931 void 932 consinit(void) 933 { 934 935 /* 936 * Everything related to console initialization is done 937 * in mach_init(). 938 */ 939 } 940 941 /* 942 * Allocate memory for variable-sized tables, 943 */ 944 void 945 cpu_startup() 946 { 947 vaddr_t minaddr, maxaddr; 948 char pbuf[9]; 949 950 /* 951 * Good {morning,afternoon,evening,night}. 952 */ 953 printf("%s%s", copyright, version); 954 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 955 printf("total memory = %s\n", pbuf); 956 957 /* 958 * Virtual memory is bootstrapped -- notify the bus spaces 959 * that memory allocation is now safe. 960 */ 961 rmixl_configuration.rc_mallocsafe = 1; 962 963 minaddr = 0; 964 /* 965 * Allocate a submap for physio. 966 */ 967 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 968 VM_PHYS_SIZE, 0, FALSE, NULL); 969 970 /* 971 * (No need to allocate an mbuf cluster submap. Mbuf clusters 972 * are allocated via the pool allocator, and we use XKSEG to 973 * map those pages.) 974 */ 975 976 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 977 printf("avail memory = %s\n", pbuf); 978 } 979 980 int waittime = -1; 981 982 void 983 cpu_reboot(int howto, char *bootstr) 984 { 985 986 /* Take a snapshot before clobbering any registers. */ 987 savectx(curpcb); 988 989 if (cold) { 990 howto |= RB_HALT; 991 goto haltsys; 992 } 993 994 /* If "always halt" was specified as a boot flag, obey. */ 995 if (boothowto & RB_HALT) 996 howto |= RB_HALT; 997 998 boothowto = howto; 999 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 1000 waittime = 0; 1001 vfs_shutdown(); 1002 1003 /* 1004 * If we've been adjusting the clock, the todr 1005 * will be out of synch; adjust it now. 1006 */ 1007 resettodr(); 1008 } 1009 1010 splhigh(); 1011 1012 if (howto & RB_DUMP) 1013 dumpsys(); 1014 1015 haltsys: 1016 doshutdownhooks(); 1017 1018 if (howto & RB_HALT) { 1019 printf("\n"); 1020 printf("The operating system has halted.\n"); 1021 printf("Please press any key to reboot.\n\n"); 1022 cnpollc(1); /* For proper keyboard command handling */ 1023 cngetc(); 1024 cnpollc(0); 1025 } 1026 1027 printf("rebooting...\n\n"); 1028 1029 rmixl_reset(); 1030 } 1031 1032 /* 1033 * goodbye world 1034 */ 1035 void __attribute__((__noreturn__)) 1036 rmixl_reset(void) 1037 { 1038 uint32_t r; 1039 1040 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1041 r |= RMIXL_GPIO_RESET_RESET; 1042 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1043 1044 printf("soft reset failed, spinning...\n"); 1045 for (;;); 1046 } 1047
Indexes created Tue Sep 30 11:09:46 GMT 2025