1 1.21 thorpej /* $NetBSD: ev64260_locore.S,v 1.21 2021/02/26 02:18:56 thorpej Exp $ */ 2 1.1 matt /* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */ 3 1.1 matt 4 1.1 matt /* 5 1.1 matt * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 1.1 matt * Copyright (C) 1995, 1996 TooLs GmbH. 7 1.1 matt * All rights reserved. 8 1.1 matt * 9 1.1 matt * Redistribution and use in source and binary forms, with or without 10 1.1 matt * modification, are permitted provided that the following conditions 11 1.1 matt * are met: 12 1.1 matt * 1. Redistributions of source code must retain the above copyright 13 1.1 matt * notice, this list of conditions and the following disclaimer. 14 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright 15 1.1 matt * notice, this list of conditions and the following disclaimer in the 16 1.1 matt * documentation and/or other materials provided with the distribution. 17 1.1 matt * 3. All advertising materials mentioning features or use of this software 18 1.1 matt * must display the following acknowledgement: 19 1.1 matt * This product includes software developed by TooLs GmbH. 20 1.1 matt * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 1.1 matt * derived from this software without specific prior written permission. 22 1.1 matt * 23 1.1 matt * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 1.1 matt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 1.1 matt * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 1.1 matt * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 1.1 matt * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 1.1 matt * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 1.1 matt * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 1.1 matt * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 1.1 matt * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 1.1 matt * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 1.1 matt */ 34 1.1 matt 35 1.1 matt #include "opt_ddb.h" 36 1.1 matt #include "opt_ppcparam.h" 37 1.11 apb #include "opt_modular.h" 38 1.1 matt #include "opt_multiprocessor.h" 39 1.1 matt #include "opt_openpic.h" 40 1.1 matt #include "assym.h" 41 1.1 matt 42 1.1 matt #include <sys/syscall.h> 43 1.1 matt 44 1.1 matt #include <machine/param.h> 45 1.1 matt #include <machine/psl.h> 46 1.1 matt #include <machine/trap.h> 47 1.1 matt #include <machine/asm.h> 48 1.1 matt 49 1.1 matt #include <powerpc/spr.h> 50 1.13 matt #include <powerpc/oea/spr.h> 51 1.2 matt #include <powerpc/oea/bat.h> 52 1.1 matt #include <powerpc/oea/hid.h> 53 1.1 matt 54 1.1 matt /* 55 1.1 matt * Some instructions gas doesn't understand (yet?) 56 1.1 matt */ 57 1.1 matt #define bdneq bdnzf 2, 58 1.1 matt 59 1.1 matt /* 60 1.1 matt * Globals 61 1.1 matt */ 62 1.1 matt GLOBAL(startsym) 63 1.1 matt .long 0 /* start symbol table */ 64 1.1 matt GLOBAL(endsym) 65 1.1 matt .long 0 /* end symbol table */ 66 1.1 matt /* 67 1.1 matt * File-scope for locore.S 68 1.1 matt */ 69 1.1 matt #ifdef DINK 70 1.1 matt .data 71 1.1 matt dink_return: 72 1.1 matt .long 0 /* fake uarea during idle after exit */ 73 1.1 matt dink_stack: 74 1.1 matt .long 0 /* fake uarea during idle after exit */ 75 1.1 matt #endif 76 1.1 matt 77 1.4 matt 78 1.1 matt /* 79 1.1 matt * This symbol is here for the benefit of kvm_mkdb, and is supposed to 80 1.1 matt * mark the start of kernel text. 81 1.1 matt */ 82 1.1 matt .text 83 1.1 matt .globl _C_LABEL(kernel_text) 84 1.1 matt _C_LABEL(kernel_text): 85 1.1 matt 86 1.1 matt /* 87 1.1 matt * Startup entry. Note, this must be the first thing in the text 88 1.1 matt * segment! 89 1.1 matt */ 90 1.1 matt .text 91 1.1 matt .globl __start 92 1.1 matt __start: 93 1.1 matt #ifdef DINK 94 1.1 matt mflr 0 95 1.1 matt lis 8, dink_stack@ha 96 1.1 matt stw 1, dink_stack@l(8) 97 1.1 matt lis 8, dink_return@ha 98 1.1 matt stw 0, dink_return@l(8) 99 1.1 matt #endif 100 1.1 matt 101 1.1 matt #if 0 102 1.1 matt eieio; sync 103 1.1 matt lis 8, 0xf100f104@ha 104 1.1 matt lwz 7, -3836(8) 105 1.1 matt li 0, 1 106 1.1 matt andc 7,7,0 107 1.1 matt stw 7, -3836(8) 108 1.1 matt eieio; sync 109 1.1 matt #endif 110 1.1 matt 111 1.2 matt /* 112 1.2 matt * Make sure that .bss is zeroed. 113 1.2 matt */ 114 1.2 matt li 0,0 115 1.2 matt lis 8,edata@ha 116 1.2 matt addi 8,8,edata@l 117 1.2 matt lis 9,end@ha 118 1.2 matt addi 9,9,end@l 119 1.2 matt 5: cmpw 0,8,9 /* edata & end are >= word aligned */ 120 1.2 matt bge 6f 121 1.2 matt stw 0,0(8) 122 1.2 matt addi 8,8,4 123 1.2 matt b 5b 124 1.2 matt 6: 125 1.2 matt 126 1.1 matt li 0,0 127 1.1 matt mtmsr 0 /* Disable FPU/MMU/exceptions */ 128 1.1 matt sync ; isync 129 1.1 matt 130 1.2 matt #if 1 131 1.4 matt mfpvr 0 132 1.4 matt srwi 0,0,16 133 1.4 matt cmplwi 0,MPC7410 134 1.4 matt bne 16f 135 1.4 matt 136 1.4 matt #if 0 137 1.3 matt /* flush and disable L2 */ 138 1.3 matt mfspr 8,SPR_L2CR 139 1.3 matt lis 0,(L2CR_L2E|L2CR_L2WT)@h /* disable the L2 mode */ 140 1.3 matt andc 8,8,0 141 1.3 matt ori 8,8,L2CR_L2HWF /* enable hardware flush */ 142 1.3 matt sync 143 1.3 matt mtspr SPR_L2CR,8 /* do it */ 144 1.3 matt sync /* wait for it to finish */ 145 1.3 matt 146 1.3 matt /* Disable data lock mode */ 147 1.1 matt mfspr 8,SPR_HID0 148 1.2 matt li 0,HID0_DLOCK 149 1.2 matt andc 8,8,0 150 1.1 matt mtspr SPR_HID0,8 151 1.3 matt sync 152 1.4 matt #endif 153 1.4 matt #if 0 154 1.3 matt /* 155 1.3 matt * Flush the L1 cache 156 1.3 matt */ 157 1.3 matt mfspr 8,SPR_MSSCR0 158 1.3 matt oris 8,8,MSSCR0_DL1HWF@h 159 1.3 matt sync 160 1.3 matt mtspr SPR_MSSCR0,8 161 1.3 matt sync 162 1.3 matt #endif 163 1.3 matt #if 1 164 1.3 matt /* disable data and instruction caches */ 165 1.3 matt mfspr 8,SPR_HID0 166 1.4 matt li 0,HID0_DLOCK@l 167 1.4 matt andc 8,8,0 168 1.4 matt sync 169 1.4 matt mtspr SPR_HID0,8 170 1.4 matt sync 171 1.4 matt isync 172 1.4 matt #endif 173 1.4 matt 7: 174 1.4 matt #if 0 175 1.4 matt /* disable data and instruction caches */ 176 1.4 matt mfspr 8,SPR_HID0 177 1.3 matt li 0,(HID0_ICE|HID0_DCE)@l 178 1.3 matt andc 8,8,0 179 1.3 matt sync 180 1.3 matt mtspr SPR_HID0,8 181 1.3 matt sync 182 1.3 matt isync 183 1.3 matt #endif 184 1.4 matt 7: 185 1.4 matt #if 0 186 1.3 matt /* Enable and flush data and instruction caches */ 187 1.4 matt ori 8,8,(HID0_ICFI|HID0_ICE|HID0_DCFI|HID0_DCE) 188 1.4 matt # ori 8,8,(HID0_ICFI|HID0_ICE) 189 1.3 matt mtspr SPR_HID0,8 190 1.3 matt isync 191 1.4 matt 8: sync 192 1.3 matt mfspr 8,SPR_HID0 193 1.3 matt andi. 0,8,(HID0_ICFI|HID0_DCFI) 194 1.4 matt bne 8b 195 1.3 matt #endif 196 1.3 matt 197 1.4 matt #if 0 198 1.3 matt mfspr 8,SPR_L2CR 199 1.3 matt oris 8,8,L2CR_L2E@h 200 1.3 matt sync 201 1.3 matt mtspr SPR_L2CR,8 202 1.3 matt sync 203 1.3 matt #endif 204 1.4 matt 16: 205 1.2 matt #endif 206 1.1 matt 207 1.1 matt /* compute end of kernel memory */ 208 1.1 matt lis 8,_C_LABEL(end)@ha 209 1.1 matt addi 8,8,_C_LABEL(end)@l 210 1.15 pooka #if NKSYMS || defined(DDB) || defined(MODULAR) 211 1.1 matt lis 7,_C_LABEL(startsym)@ha 212 1.1 matt addi 7,7,_C_LABEL(startsym)@l 213 1.1 matt stw 3,0(7) 214 1.1 matt lis 7,_C_LABEL(endsym)@ha 215 1.1 matt addi 7,7,_C_LABEL(endsym)@l 216 1.1 matt stw 4,0(7) 217 1.1 matt /* mr 8,4 * end of symbol table */ 218 1.1 matt #endif 219 1.1 matt mr 4,8 /* end of mem reserved for kernel */ 220 1.1 matt INIT_CPUINFO(4,1,9,0) 221 1.1 matt 222 1.1 matt lis 3,__start@ha 223 1.1 matt addi 3,3,__start@l 224 1.1 matt li 5,0 225 1.1 matt li 6,0 226 1.1 matt 227 1.17 matt bl _C_LABEL(cpu_model_init) 228 1.1 matt bl _C_LABEL(initppc) 229 1.1 matt bl _C_LABEL(main) 230 1.1 matt 231 1.1 matt loop: b loop /* XXX not reached */ 232 1.1 matt 233 1.1 matt #if 0 234 1.1 matt .globl _C_LABEL(extintr_enable) 235 1.1 matt _C_LABEL(extintr_enable): 236 1.1 matt mfmsr 3 237 1.1 matt ori 3,3,PSL_EE@l 238 1.1 matt sync 239 1.1 matt mtmsr 3 240 1.1 matt blr 241 1.1 matt 242 1.1 matt .globl _C_LABEL(extintr_restore) 243 1.1 matt _C_LABEL(extintr_restore): 244 1.1 matt mfmsr 4 245 1.1 matt or 3,4,3 246 1.1 matt sync 247 1.1 matt mtmsr 3 248 1.1 matt blr 249 1.1 matt 250 1.1 matt .globl _C_LABEL(extintr_disable) 251 1.1 matt _C_LABEL(extintr_disable): 252 1.1 matt mfmsr 3 253 1.1 matt andi. 4,3,~PSL_EE@l 254 1.1 matt sync 255 1.1 matt mtmsr 4 256 1.1 matt andi. 3,3,PSL_EE@l 257 1.1 matt blr 258 1.1 matt 259 1.1 matt .globl _C_LABEL(mvpppc_reboot) 260 1.1 matt _C_LABEL(mvpppc_reboot): 261 1.1 matt mfmsr 3 262 1.1 matt ori 3,3,PSL_IP@l 263 1.1 matt sync 264 1.1 matt mtmsr 3 265 1.1 matt b 0xFFF00100 266 1.1 matt #endif 267 1.1 matt 268 1.1 matt #ifdef DINK 269 1.1 matt .globl _C_LABEL(return_to_dink) 270 1.1 matt _C_LABEL(return_to_dink): 271 1.1 matt sync 272 1.1 matt lis 4, dink_stack@ha 273 1.1 matt lwz 1, dink_stack@l(4) 274 1.1 matt lis 4, dink_return@ha 275 1.1 matt lwz 5, dink_return@l(4) 276 1.1 matt mtlr 5 277 1.1 matt blr 278 1.1 matt #endif 279 1.1 matt 280 1.1 matt /* 281 1.1 matt * Include common switch / setfault code 282 1.1 matt */ 283 1.1 matt #include <powerpc/powerpc/locore_subr.S> 284 1.1 matt 285 1.1 matt /* 286 1.14 snj * Include common trap / exception code 287 1.1 matt */ 288 1.1 matt #include <powerpc/powerpc/trap_subr.S> 289 1.2 matt 290 1.2 matt /* 291 1.2 matt * Include PIO routines 292 1.2 matt */ 293 1.2 matt #include <powerpc/powerpc/pio_subr.S> 294