gt_mainbus.c revision 1.15
1 /* $NetBSD: gt_mainbus.c,v 1.15 2010/04/28 13:51:55 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: gt_mainbus.c,v 1.15 2010/04/28 13:51:55 kiyohara Exp $"); 40 41 #include "opt_ev64260.h" 42 #include "opt_pci.h" 43 #include "pci.h" 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/device.h> 48 #include <sys/errno.h> 49 #include <sys/extent.h> 50 #include <sys/malloc.h> 51 52 #define _POWERPC_BUS_DMA_PRIVATE 53 #include <machine/bus.h> 54 55 #include "opt_pci.h" 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pciconf.h> 58 59 #include "opt_marvell.h" 60 #include <dev/marvell/gtreg.h> 61 #include <dev/marvell/gtvar.h> 62 #include <dev/marvell/gtintrreg.h> 63 #include <dev/marvell/gtpcireg.h> 64 #include <dev/marvell/gtpcivar.h> 65 #include <dev/marvell/marvellvar.h> 66 #include <dev/marvell/gtsdmareg.h> 67 #include <dev/marvell/gtmpscreg.h> 68 #ifdef MPSC_CONSOLE 69 #include <dev/marvell/gtmpscvar.h> 70 #endif 71 72 #include <evbppc/ev64260/ev64260.h> 73 74 #include <powerpc/pic/picvar.h> 75 76 77 static int gt_match(device_t, cfdata_t, void *); 78 static void gt_attach(device_t, device_t, void *); 79 80 void gtpci_md_conf_interrupt(void *, int, int, int, int, int *); 81 int gtpci_md_conf_hook(void *, int, int, int, pcireg_t); 82 83 CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL); 84 85 86 int 87 gt_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 struct mainbus_attach_args *mba = aux; 90 91 if (strcmp(mba->mba_name, "gt") != 0) 92 return 0; 93 94 return 1; 95 } 96 97 void 98 gt_attach(device_t parent, device_t self, void *aux) 99 { 100 extern struct powerpc_bus_space ev64260_gt_bs_tag; 101 extern struct powerpc_bus_dma_tag ev64260_bus_dma_tag; 102 struct mainbus_attach_args *mba = aux; 103 struct gt_softc *sc = device_private(self); 104 uint32_t cpumstr, cr, r; 105 106 sc->sc_dev = self; 107 sc->sc_addr = mba->mba_addr; 108 sc->sc_iot = &ev64260_gt_bs_tag; 109 sc->sc_dmat = &ev64260_bus_dma_tag; 110 111 #ifdef MPSC_CONSOLE 112 { 113 /* First, unmap already mapped console space. */ 114 gtmpsc_softc_t *gtmpsc = >mpsc_cn_softc; 115 116 bus_space_unmap(gtmpsc->sc_iot, gtmpsc->sc_mpsch, GTMPSC_SIZE); 117 bus_space_unmap(gtmpsc->sc_iot, gtmpsc->sc_sdmah, GTSDMA_SIZE); 118 } 119 #endif 120 if (bus_space_map(sc->sc_iot, sc->sc_addr, GT_SIZE, 0, &sc->sc_ioh) != 121 0) { 122 aprint_error_dev(self, "registers map failed\n"); 123 return; 124 } 125 #ifdef MPSC_CONSOLE 126 { 127 /* Next, remap console space. */ 128 gtmpsc_softc_t *gtmpsc = >mpsc_cn_softc; 129 130 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 131 GTMPSC_BASE(gtmpsc->sc_unit), GTMPSC_SIZE, 132 >mpsc->sc_mpsch)) { 133 aprint_error_dev(self, "Cannot map MPSC registers\n"); 134 return; 135 } 136 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 137 GTSDMA_BASE(gtmpsc->sc_unit), GTSDMA_SIZE, 138 >mpsc->sc_sdmah)) { 139 aprint_error_dev(self, "Cannot map SDMA registers\n"); 140 return; 141 } 142 } 143 #endif 144 145 /* 146 * Set MPSC Routing: 147 * MR0 --> Serial Port 0 148 * MR1 --> Serial Port 1 149 */ 150 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTMPSC_MRR, GTMPSC_MRR_RES); 151 152 /* 153 * RX and TX Clock Routing: 154 * CRR0 --> BRG0 155 * CRR1 --> BRG1 156 */ 157 cr = GTMPSC_CRR(0, GTMPSC_CRR_BRG0) | GTMPSC_CRR(1, GTMPSC_CRR_BRG1); 158 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTMPSC_RCRR, cr); 159 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTMPSC_TCRR, cr); 160 161 /* 162 * Setup Multi-Purpose Pins (MPP). 163 * Change to GPP. 164 * GPP 21 (DUART channel A intr) 165 * GPP 22 (DUART channel B intr) 166 * GPP 26 (RTC INT) 167 * GPP 27 (PCI 0 INTA) 168 * GPP 29 (PCI 1 INTA) 169 */ 170 #define PIN2SHIFT(pin) ((pin % 8) * 4) 171 r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_MPP_Control2); 172 r |= ((0xf << PIN2SHIFT(21)) | (0xf << PIN2SHIFT(22))); 173 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_MPP_Control2, r); 174 r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_MPP_Control3); 175 r |= ((0xf << PIN2SHIFT(26))); 176 r |= ((0xf << PIN2SHIFT(27)) | (0xf << PIN2SHIFT(29))); 177 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_MPP_Control3, r); 178 179 /* Also configure GPP. */ 180 #define GPP_EXTERNAL_INTERRUPS \ 181 ((1 << 21) | (1 << 22) | (1 << 26) | (1 << 27) | (1 << 29)) 182 r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_IO_Control); 183 r &= ~GPP_EXTERNAL_INTERRUPS; 184 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_IO_Control, r); 185 r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Level_Control); 186 r |= GPP_EXTERNAL_INTERRUPS; 187 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Level_Control, r); 188 189 /* clear interrupts */ 190 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ICR_CIM_LO, 0); 191 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ICR_CIM_HI, 0); 192 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Cause, 193 ~GPP_EXTERNAL_INTERRUPS); 194 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask, 195 GPP_EXTERNAL_INTERRUPS); 196 197 discovery_pic->pic_cookie = sc; 198 intr_establish(IRQ_GPP7_0, IST_LEVEL, IPL_NONE, 199 pic_handle_intr, discovery_gpp_pic[0]); 200 intr_establish(IRQ_GPP15_8, IST_LEVEL, IPL_NONE, 201 pic_handle_intr, discovery_gpp_pic[1]); 202 intr_establish(IRQ_GPP23_16, IST_LEVEL, IPL_NONE, 203 pic_handle_intr, discovery_gpp_pic[2]); 204 intr_establish(IRQ_GPP31_24, IST_LEVEL, IPL_NONE, 205 pic_handle_intr, discovery_gpp_pic[3]); 206 207 cpumstr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_CPU_Master_Ctl); 208 cpumstr &= ~(GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock); 209 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_CPU_Master_Ctl, cpumstr); 210 211 gt_attach_common(sc); 212 } 213 214 215 void 216 gtpci_md_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, 217 int *iline) 218 { 219 #ifdef PCI_NETBSD_CONFIGURE 220 struct gtpci_softc *sc = v; 221 222 *iline = (sc->sc_unit == 0 ? 27 : 29); 223 224 #define IRQ_GPP_BASE (discovery_pic->pic_numintrs); 225 226 if (*iline != 0xff) 227 *iline += IRQ_GPP_BASE; 228 #endif /* PCI_NETBSD_CONFIGURE */ 229 } 230 231 int 232 gtpci_md_conf_hook(void *v, int bus, int dev, int func, pcireg_t id) 233 { 234 struct gtpci_softc *sc = v; 235 236 return gtpci_conf_hook(sc->sc_pc, bus, dev, func, id); 237 } 238 239 240 void * 241 marvell_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 242 { 243 244 /* pass through */ 245 return intr_establish(irq, IST_LEVEL, ipl, func, arg); 246 } 247
Indexes created Tue Sep 30 11:09:46 GMT 2025