gt_mainbus.c revision 1.2
1 /* $NetBSD: gt_mainbus.c,v 1.2 2003/03/06 06:04:22 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/extent.h> 42 #include <sys/malloc.h> 43 44 #define _POWERPC_BUS_DMA_PRIVATE 45 #include <machine/bus.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pciconf.h> 49 50 #include "opt_marvell.h" 51 #include <dev/marvell/gtreg.h> 52 #include <dev/marvell/gtvar.h> 53 #include <dev/marvell/gtpcireg.h> 54 #include <dev/marvell/gtpcivar.h> 55 56 extern struct powerpc_bus_space ev64260_gt_mem_bs_tag; 57 extern struct powerpc_bus_space ev64260_pci0_mem_bs_tag; 58 extern struct powerpc_bus_space ev64260_pci0_io_bs_tag; 59 extern struct powerpc_bus_space ev64260_pci1_mem_bs_tag; 60 extern struct powerpc_bus_space ev64260_pci1_io_bs_tag; 61 62 struct powerpc_bus_dma_tag gt_bus_dma_tag = { 63 0, /* _bounce_thresh */ 64 _bus_dmamap_create, 65 _bus_dmamap_destroy, 66 _bus_dmamap_load, 67 _bus_dmamap_load_mbuf, 68 _bus_dmamap_load_uio, 69 _bus_dmamap_load_raw, 70 _bus_dmamap_unload, 71 _bus_dmamap_sync, 72 _bus_dmamem_alloc, 73 _bus_dmamem_free, 74 _bus_dmamem_map, 75 _bus_dmamem_unmap, 76 _bus_dmamem_mmap, 77 }; 78 79 static int gt_match(struct device *, struct cfdata *, void *); 80 static void gt_attach(struct device *, struct device *, void *); 81 82 CFATTACH_DECL(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL); 83 84 extern struct cfdriver gt_cd; 85 86 static int gt_found; 87 88 vaddr_t gtbase = 0x14000000; /* default address */ 89 90 int 91 gt_match(struct device *parent, struct cfdata *cf, void *aux) 92 { 93 const char *busname = aux; 94 95 if (strcmp(busname, gt_cd.cd_name) != 0) 96 return 0; 97 98 if (gt_found) 99 return 0; 100 101 return 1; 102 } 103 104 void 105 gt_attach(struct device *parent, struct device *self, void *aux) 106 { 107 struct gt_softc *gt = (struct gt_softc *) self; 108 109 gt->gt_vbase = GT_BASE; 110 gt->gt_dmat = >_bus_dma_tag; 111 gt->gt_memt = &ev64260_gt_mem_bs_tag; 112 gt->gt_pci0_memt = &ev64260_pci0_io_bs_tag; 113 gt->gt_pci0_iot = &ev64260_pci0_mem_bs_tag; 114 gt->gt_pci1_memt = &ev64260_pci1_io_bs_tag; 115 gt->gt_pci1_iot = &ev64260_pci1_mem_bs_tag; 116 117 gt_attach_common(gt); 118 } 119 120 void 121 gt_setup(struct device *gt) 122 { 123 #if 1 124 GT_DecodeAddr_SET(gt, GT_PCI0_IO_Low_Decode, 0x80000000); 125 GT_DecodeAddr_SET(gt, GT_PCI0_IO_High_Decode, 0x807FFFFF); 126 GT_DecodeAddr_SET(gt, GT_PCI1_IO_Low_Decode, 0x80800000); 127 GT_DecodeAddr_SET(gt, GT_PCI1_IO_High_Decode, 0x80FFFFFF); 128 GT_DecodeAddr_SET(gt, GT_PCI0_Mem0_Low_Decode, 0x81000000); 129 GT_DecodeAddr_SET(gt, GT_PCI0_Mem0_High_Decode, 0x88FFFFFF); 130 GT_DecodeAddr_SET(gt, GT_PCI1_Mem0_Low_Decode, 0x89000000); 131 GT_DecodeAddr_SET(gt, GT_PCI1_Mem0_High_Decode, 0x8FFFFFFF); 132 #endif 133 } 134 135 void 136 gtpci_config_bus(struct pci_chipset *pc, int busno) 137 { 138 struct extent *ioext, *memext; 139 uint32_t data; 140 pcitag_t tag; 141 #if 0 142 uint32_t data2; 143 int i; 144 #endif 145 146 switch (busno) { 147 case 0: 148 ioext = extent_create("pciio0", 0x00000600, 0x0000ffff, 149 M_DEVBUF, NULL, 0, EX_NOWAIT); 150 memext = extent_create("pcimem0", 0x81000000, 0x88ffffff, 151 M_DEVBUF, NULL, 0, EX_NOWAIT); 152 break; 153 case 1: 154 ioext = extent_create("pciio1", 0x00000600, 0x0000ffff, 155 M_DEVBUF, NULL, 0, EX_NOWAIT); 156 memext = extent_create("pcimem1", 0x89000000, 0x8fffffff, 157 M_DEVBUF, NULL, 0, EX_NOWAIT); 158 break; 159 } 160 161 pci_configure_bus(pc, ioext, memext, NULL, 0, 32); 162 163 extent_destroy(ioext); 164 extent_destroy(memext); 165 166 gtpci_write(pc, PCI_BASE_ADDR_REGISTERS_ENABLE(pc->pc_md.mdpc_busno), 167 0xffffffff); 168 169 tag = gtpci_make_tag(pc, 0, 0, 0); 170 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 171 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 172 gtpci_conf_write(pc, tag, 0x10, 0x00000000); 173 gtpci_write(pc, PCI_SCS0_BAR_SIZE(busno), 0x0fffffff); 174 gtpci_conf_write(pc, tag, 0x14, 0x04000000); 175 gtpci_write(pc, PCI_SCS1_BAR_SIZE(busno), 0x03ffffff); 176 gtpci_conf_write(pc, tag, 0x18, 0x10000000); 177 gtpci_write(pc, PCI_SCS2_BAR_SIZE(busno), 0x0fffffff); 178 gtpci_conf_write(pc, tag, 0x1c, 0x0c000000); 179 gtpci_write(pc, PCI_SCS3_BAR_SIZE(busno), 0x03ffffff); 180 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 181 182 #if 0 183 tag = gtpci_make_tag(pc, 0, 0, 1); 184 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 185 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 186 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 187 gtpci_write(pc, PCI_CS0_BAR_SIZE(busno), 0x00000000); 188 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 189 gtpci_write(pc, PCI_CS1_BAR_SIZE(busno), 0x00000000); 190 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 191 gtpci_write(pc, PCI_CS2_BAR_SIZE(busno), 0x00000000); 192 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 193 gtpci_write(pc, PCI_CS3_BAR_SIZE(busno), 0x00000000); 194 gtpci_conf_write(pc, tag, 0x20, 0xfff00000); 195 gtpci_write(pc, PCI_BOOTCS_BAR_SIZE(busno), 0x00000000); 196 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 197 198 tag = gtpci_make_tag(pc, 0, 0, 2); 199 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 200 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 201 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 202 gtpci_write(pc, PCI_P2P_MEM0_BAR_SIZE(busno), 0x00000000); 203 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 204 gtpci_write(pc, PCI_P2P_MEM1_BAR_SIZE(busno), 0x00000000); 205 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 206 gtpci_write(pc, PCI_P2P_IO_BAR_SIZE(busno), 0x00000000); 207 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 208 gtpci_write(pc, PCI_CPU_BAR_SIZE(busno), 0x00000000); 209 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 210 211 for (i=4; i<8; i++) { 212 tag = gtpci_make_tag(pc, 0, 0, i); 213 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 214 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 215 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 216 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 217 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 218 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 219 gtpci_conf_write(pc, tag, 0x20, 0xfff00000); 220 gtpci_conf_write(pc, tag, 0x24, 0xfff00000); 221 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 222 } 223 #endif 224 switch (busno) { 225 case 0: 226 /* set Internal Mem to 1d000000 - 1dffffff */ 227 tag = gtpci_make_tag(pc, 0, 0, 0); 228 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 229 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 230 231 gtpci_conf_write(pc, tag, 0x20, 0xf1000008); 232 gtpci_conf_write(pc, tag, 0x24, 0xf1000001); 233 234 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 235 break; 236 case 1: 237 /* set Internal Mem to 1f000000 - 1fffffff */ 238 tag = gtpci_make_tag(pc, 0, 0, 0); 239 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 240 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 241 242 gtpci_conf_write(pc, tag, 0x20, 0xf1000008); 243 gtpci_conf_write(pc, tag, 0x24, 0xf1000001); 244 245 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 246 break; 247 } 248 249 #if 0 250 tag = gtpci_make_tag(pc, 0, 0, 3); 251 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data2); 252 #endif 253 254 data = ~(PCI_BARE_SCS0En | /* PCI_BARE_SCS1En | */ \ 255 PCI_BARE_SCS2En | /* PCI_BARE_SCS3En | */ \ 256 PCI_BARE_IntMemEn | PCI_BARE_IntIOEn); 257 gtpci_write(pc, PCI_BASE_ADDR_REGISTERS_ENABLE(pc->pc_md.mdpc_busno), data); 258 } 259 260 void 261 gtpci_md_bus_devorder(pci_chipset_tag_t pc, int busno, char devs[]) 262 { 263 int i; 264 265 for (i = 0; i < 32; i++) 266 *devs++ = i; 267 *devs = -1; 268 } 269 270 int 271 gtpci_md_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, 272 pcireg_t id) 273 { 274 if (bus == 0 && dev == 0) 275 return 0; 276 277 return 1; 278 } 279 280 void 281 gtpci_md_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, 282 int swiz, int *iline) 283 { 284 } 285 286 int 287 gtpci_md_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 288 { 289 int pin = pa->pa_intrpin; 290 int line = pa->pa_intrline; 291 292 if (pin > 4) { 293 printf("pci_intr_map: bad interrupt pin %d\n", pin); 294 *ihp = -1; 295 return 1; 296 } 297 298 *ihp = line; 299 return 0; 300 } 301
Indexes created Mon Sep 29 03:10:08 GMT 2025