gt_mainbus.c revision 1.3
1 /* $NetBSD: gt_mainbus.c,v 1.3 2003/03/07 18:24:01 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/extent.h> 42 #include <sys/malloc.h> 43 44 #define _POWERPC_BUS_DMA_PRIVATE 45 #include <machine/bus.h> 46 47 #include "opt_pci.h" 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include "opt_marvell.h" 52 #include <dev/marvell/gtreg.h> 53 #include <dev/marvell/gtvar.h> 54 #include <dev/marvell/gtpcireg.h> 55 #include <dev/marvell/gtpcivar.h> 56 57 extern struct powerpc_bus_space gt_mem_bs_tag; 58 extern struct powerpc_bus_space gt_pci0_mem_bs_tag; 59 extern struct powerpc_bus_space gt_pci0_io_bs_tag; 60 extern struct powerpc_bus_space gt_pci1_mem_bs_tag; 61 extern struct powerpc_bus_space gt_pci1_io_bs_tag; 62 63 struct powerpc_bus_dma_tag gt_bus_dma_tag = { 64 0, /* _bounce_thresh */ 65 _bus_dmamap_create, 66 _bus_dmamap_destroy, 67 _bus_dmamap_load, 68 _bus_dmamap_load_mbuf, 69 _bus_dmamap_load_uio, 70 _bus_dmamap_load_raw, 71 _bus_dmamap_unload, 72 _bus_dmamap_sync, 73 _bus_dmamem_alloc, 74 _bus_dmamem_free, 75 _bus_dmamem_map, 76 _bus_dmamem_unmap, 77 _bus_dmamem_mmap, 78 }; 79 80 static int gt_match(struct device *, struct cfdata *, void *); 81 static void gt_attach(struct device *, struct device *, void *); 82 83 CFATTACH_DECL(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL); 84 85 extern struct cfdriver gt_cd; 86 87 static int gt_found; 88 89 vaddr_t gtbase = 0x14000000; /* default address */ 90 91 int 92 gt_match(struct device *parent, struct cfdata *cf, void *aux) 93 { 94 const char *busname = aux; 95 96 if (strcmp(busname, gt_cd.cd_name) != 0) 97 return 0; 98 99 if (gt_found) 100 return 0; 101 102 return 1; 103 } 104 105 void 106 gt_attach(struct device *parent, struct device *self, void *aux) 107 { 108 struct gt_softc *gt = (struct gt_softc *) self; 109 110 gt->gt_vbase = GT_BASE; 111 gt->gt_dmat = >_bus_dma_tag; 112 gt->gt_memt = >_mem_bs_tag; 113 gt->gt_pci0_memt = >_pci0_io_bs_tag; 114 gt->gt_pci0_iot = >_pci0_mem_bs_tag; 115 gt->gt_pci1_memt = >_pci1_io_bs_tag; 116 gt->gt_pci1_iot = >_pci1_mem_bs_tag; 117 118 gt_attach_common(gt); 119 } 120 121 void 122 gt_setup(struct device *gt) 123 { 124 #if 1 125 GT_DecodeAddr_SET(gt, GT_PCI0_IO_Low_Decode, 126 gt_pci0_io_bs_tag.pbs_offset + gt_pci0_io_bs_tag.pbs_base); 127 GT_DecodeAddr_SET(gt, GT_PCI0_IO_High_Decode, 128 gt_pci0_io_bs_tag.pbs_offset + gt_pci0_io_bs_tag.pbs_limit - 1); 129 130 GT_DecodeAddr_SET(gt, GT_PCI1_IO_Low_Decode, 131 gt_pci1_io_bs_tag.pbs_offset + gt_pci1_io_bs_tag.pbs_base); 132 GT_DecodeAddr_SET(gt, GT_PCI1_IO_High_Decode, 133 gt_pci1_io_bs_tag.pbs_offset + gt_pci1_io_bs_tag.pbs_limit - 1); 134 135 GT_DecodeAddr_SET(gt, GT_PCI0_Mem0_Low_Decode, 136 gt_pci0_mem_bs_tag.pbs_offset + gt_pci0_mem_bs_tag.pbs_base); 137 GT_DecodeAddr_SET(gt, GT_PCI0_Mem0_High_Decode, 138 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_limit - 1); 139 140 GT_DecodeAddr_SET(gt, GT_PCI1_Mem0_Low_Decode, 141 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_base); 142 GT_DecodeAddr_SET(gt, GT_PCI1_Mem0_High_Decode, 143 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_limit - 1); 144 #endif 145 } 146 147 void 148 gtpci_config_bus(struct pci_chipset *pc, int busno) 149 { 150 #ifdef PCI_NETBSD_CONFIGURE 151 struct extent *ioext, *memext; 152 uint32_t data; 153 pcitag_t tag; 154 #if 0 155 uint32_t data2; 156 int i; 157 #endif 158 159 switch (busno) { 160 case 0: 161 ioext = extent_create("pci0-io", 0x00000600, 0x0000ffff, 162 M_DEVBUF, NULL, 0, EX_NOWAIT); 163 memext = extent_create("pci0-mem", 164 gt_pci0_mem_bs_tag.pbs_base, 165 gt_pci0_mem_bs_tag.pbs_limit-1, 166 M_DEVBUF, NULL, 0, EX_NOWAIT); 167 break; 168 case 1: 169 ioext = extent_create("pci1-io", 0x00000600, 0x0000ffff, 170 M_DEVBUF, NULL, 0, EX_NOWAIT); 171 memext = extent_create("pci1-mem", 172 gt_pci1_mem_bs_tag.pbs_base, 173 gt_pci1_mem_bs_tag.pbs_limit-1, 174 M_DEVBUF, NULL, 0, EX_NOWAIT); 175 break; 176 } 177 178 pci_configure_bus(pc, ioext, memext, NULL, 0, 32); 179 180 extent_destroy(ioext); 181 extent_destroy(memext); 182 183 gtpci_write(pc, PCI_BASE_ADDR_REGISTERS_ENABLE(pc->pc_md.mdpc_busno), 184 0xffffffff); 185 186 tag = gtpci_make_tag(pc, 0, 0, 0); 187 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 188 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 189 gtpci_conf_write(pc, tag, 0x10, 0x00000000); 190 gtpci_write(pc, PCI_SCS0_BAR_SIZE(busno), 0x0fffffff); 191 gtpci_conf_write(pc, tag, 0x14, 0x04000000); 192 gtpci_write(pc, PCI_SCS1_BAR_SIZE(busno), 0x03ffffff); 193 gtpci_conf_write(pc, tag, 0x18, 0x10000000); 194 gtpci_write(pc, PCI_SCS2_BAR_SIZE(busno), 0x0fffffff); 195 gtpci_conf_write(pc, tag, 0x1c, 0x0c000000); 196 gtpci_write(pc, PCI_SCS3_BAR_SIZE(busno), 0x03ffffff); 197 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 198 199 #if 0 200 tag = gtpci_make_tag(pc, 0, 0, 1); 201 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 202 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 203 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 204 gtpci_write(pc, PCI_CS0_BAR_SIZE(busno), 0x00000000); 205 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 206 gtpci_write(pc, PCI_CS1_BAR_SIZE(busno), 0x00000000); 207 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 208 gtpci_write(pc, PCI_CS2_BAR_SIZE(busno), 0x00000000); 209 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 210 gtpci_write(pc, PCI_CS3_BAR_SIZE(busno), 0x00000000); 211 gtpci_conf_write(pc, tag, 0x20, 0xfff00000); 212 gtpci_write(pc, PCI_BOOTCS_BAR_SIZE(busno), 0x00000000); 213 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 214 215 tag = gtpci_make_tag(pc, 0, 0, 2); 216 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 217 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 218 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 219 gtpci_write(pc, PCI_P2P_MEM0_BAR_SIZE(busno), 0x00000000); 220 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 221 gtpci_write(pc, PCI_P2P_MEM1_BAR_SIZE(busno), 0x00000000); 222 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 223 gtpci_write(pc, PCI_P2P_IO_BAR_SIZE(busno), 0x00000000); 224 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 225 gtpci_write(pc, PCI_CPU_BAR_SIZE(busno), 0x00000000); 226 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 227 228 for (i=4; i<8; i++) { 229 tag = gtpci_make_tag(pc, 0, 0, i); 230 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 231 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 232 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 233 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 234 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 235 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 236 gtpci_conf_write(pc, tag, 0x20, 0xfff00000); 237 gtpci_conf_write(pc, tag, 0x24, 0xfff00000); 238 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 239 } 240 #endif 241 switch (busno) { 242 case 0: 243 /* set Internal Mem to 1d000000 - 1dffffff */ 244 tag = gtpci_make_tag(pc, 0, 0, 0); 245 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 246 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 247 248 gtpci_conf_write(pc, tag, 0x20, 0xf1000008); 249 gtpci_conf_write(pc, tag, 0x24, 0xf1000001); 250 251 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 252 break; 253 case 1: 254 /* set Internal Mem to 1f000000 - 1fffffff */ 255 tag = gtpci_make_tag(pc, 0, 0, 0); 256 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 257 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 258 259 gtpci_conf_write(pc, tag, 0x20, 0xf1000008); 260 gtpci_conf_write(pc, tag, 0x24, 0xf1000001); 261 262 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 263 break; 264 } 265 266 #if 0 267 tag = gtpci_make_tag(pc, 0, 0, 3); 268 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data2); 269 #endif 270 271 data = ~(PCI_BARE_SCS0En | /* PCI_BARE_SCS1En | */ \ 272 PCI_BARE_SCS2En | /* PCI_BARE_SCS3En | */ \ 273 PCI_BARE_IntMemEn | PCI_BARE_IntIOEn); 274 gtpci_write(pc, PCI_BASE_ADDR_REGISTERS_ENABLE(pc->pc_md.mdpc_busno), data); 275 #endif /* PCI_NETBSD_CONFIGURE */ 276 } 277 278 void 279 gtpci_md_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, 280 int swiz, int *iline) 281 { 282 #ifdef PCI_NETBSD_CONFIGURE 283 #endif /* PCI_NETBSD_CONFIGURE */ 284 } 285 286 void 287 gtpci_md_bus_devorder(pci_chipset_tag_t pc, int busno, char devs[]) 288 { 289 int i; 290 291 for (i = 0; i < 32; i++) 292 *devs++ = i; 293 *devs = -1; 294 } 295 296 int 297 gtpci_md_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, 298 pcireg_t id) 299 { 300 if (bus == 0 && dev == 0) 301 return 0; 302 303 return 1; 304 } 305 306 int 307 gtpci_md_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 308 { 309 int pin = pa->pa_intrpin; 310 int line = pa->pa_intrline; 311 312 if (pin > 4) { 313 printf("pci_intr_map: bad interrupt pin %d\n", pin); 314 *ihp = -1; 315 return 1; 316 } 317 318 *ihp = line; 319 return 0; 320 } 321
Indexes created Mon Sep 29 03:10:08 GMT 2025