gt_mainbus.c revision 1.4
1 /* $NetBSD: gt_mainbus.c,v 1.4 2003/03/16 07:07:19 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/extent.h> 42 #include <sys/malloc.h> 43 44 #define _POWERPC_BUS_DMA_PRIVATE 45 #include <machine/bus.h> 46 47 #include "opt_pci.h" 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include "opt_marvell.h" 52 #include <dev/marvell/gtreg.h> 53 #include <dev/marvell/gtvar.h> 54 #include <dev/marvell/gtpcireg.h> 55 #include <dev/marvell/gtpcivar.h> 56 57 extern struct powerpc_bus_space gt_mem_bs_tag; 58 extern struct powerpc_bus_space gt_pci0_mem_bs_tag; 59 extern struct powerpc_bus_space gt_pci0_io_bs_tag; 60 extern struct powerpc_bus_space gt_pci1_mem_bs_tag; 61 extern struct powerpc_bus_space gt_pci1_io_bs_tag; 62 63 struct powerpc_bus_dma_tag gt_bus_dma_tag = { 64 0, /* _bounce_thresh */ 65 _bus_dmamap_create, 66 _bus_dmamap_destroy, 67 _bus_dmamap_load, 68 _bus_dmamap_load_mbuf, 69 _bus_dmamap_load_uio, 70 _bus_dmamap_load_raw, 71 _bus_dmamap_unload, 72 _bus_dmamap_sync, 73 _bus_dmamem_alloc, 74 _bus_dmamem_free, 75 _bus_dmamem_map, 76 _bus_dmamem_unmap, 77 _bus_dmamem_mmap, 78 }; 79 80 static int gt_match(struct device *, struct cfdata *, void *); 81 static void gt_attach(struct device *, struct device *, void *); 82 83 CFATTACH_DECL(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL); 84 85 extern struct cfdriver gt_cd; 86 extern bus_space_handle_t gt_memh; 87 88 static int gt_found; 89 90 vaddr_t gtbase = 0xf8000000; /* default address */ 91 92 int 93 gt_match(struct device *parent, struct cfdata *cf, void *aux) 94 { 95 const char **busname = aux; 96 97 if (strcmp(*busname, gt_cd.cd_name) != 0) 98 return 0; 99 100 if (gt_found) 101 return 0; 102 103 return 1; 104 } 105 106 void 107 gt_attach(struct device *parent, struct device *self, void *aux) 108 { 109 struct gt_softc *gt = (struct gt_softc *) self; 110 111 gt->gt_dmat = >_bus_dma_tag; 112 gt->gt_memt = >_mem_bs_tag; 113 gt->gt_pci0_memt = >_pci0_io_bs_tag; 114 gt->gt_pci0_iot = >_pci0_mem_bs_tag; 115 gt->gt_pci1_memt = >_pci1_io_bs_tag; 116 gt->gt_pci1_iot = >_pci1_mem_bs_tag; 117 118 gt->gt_memh = gt_memh; 119 120 #if 1 121 GT_DecodeAddr_SET(gt, GT_PCI0_IO_Low_Decode, 122 gt_pci0_io_bs_tag.pbs_offset + gt_pci0_io_bs_tag.pbs_base); 123 GT_DecodeAddr_SET(gt, GT_PCI0_IO_High_Decode, 124 gt_pci0_io_bs_tag.pbs_offset + gt_pci0_io_bs_tag.pbs_limit - 1); 125 126 GT_DecodeAddr_SET(gt, GT_PCI1_IO_Low_Decode, 127 gt_pci1_io_bs_tag.pbs_offset + gt_pci1_io_bs_tag.pbs_base); 128 GT_DecodeAddr_SET(gt, GT_PCI1_IO_High_Decode, 129 gt_pci1_io_bs_tag.pbs_offset + gt_pci1_io_bs_tag.pbs_limit - 1); 130 131 GT_DecodeAddr_SET(gt, GT_PCI0_Mem0_Low_Decode, 132 gt_pci0_mem_bs_tag.pbs_offset + gt_pci0_mem_bs_tag.pbs_base); 133 GT_DecodeAddr_SET(gt, GT_PCI0_Mem0_High_Decode, 134 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_limit - 1); 135 136 GT_DecodeAddr_SET(gt, GT_PCI1_Mem0_Low_Decode, 137 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_base); 138 GT_DecodeAddr_SET(gt, GT_PCI1_Mem0_High_Decode, 139 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_limit - 1); 140 #endif 141 142 gt_attach_common(gt); 143 } 144 145 void 146 gtpci_config_bus(struct pci_chipset *pc, int busno) 147 { 148 #ifdef PCI_NETBSD_CONFIGURE 149 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 150 struct extent *ioext, *memext; 151 uint32_t data; 152 pcitag_t tag; 153 #if 0 154 uint32_t data2; 155 int i; 156 #endif 157 158 switch (busno) { 159 case 0: 160 ioext = extent_create("pci0-io", 0x00000600, 0x0000ffff, 161 M_DEVBUF, NULL, 0, EX_NOWAIT); 162 memext = extent_create("pci0-mem", 163 gt_pci0_mem_bs_tag.pbs_base, 164 gt_pci0_mem_bs_tag.pbs_limit-1, 165 M_DEVBUF, NULL, 0, EX_NOWAIT); 166 break; 167 case 1: 168 ioext = extent_create("pci1-io", 0x00000600, 0x0000ffff, 169 M_DEVBUF, NULL, 0, EX_NOWAIT); 170 memext = extent_create("pci1-mem", 171 gt_pci1_mem_bs_tag.pbs_base, 172 gt_pci1_mem_bs_tag.pbs_limit-1, 173 M_DEVBUF, NULL, 0, EX_NOWAIT); 174 break; 175 } 176 177 pci_configure_bus(pc, ioext, memext, NULL, 0, 32); 178 179 extent_destroy(ioext); 180 extent_destroy(memext); 181 182 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 183 0xffffffff); 184 185 tag = gtpci_make_tag(pc, 0, 0, 0); 186 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 187 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 188 gtpci_conf_write(pc, tag, 0x10, 0x00000000); 189 gtpci_write(gtpc, PCI_SCS0_BAR_SIZE(busno), 0x0fffffff); 190 gtpci_conf_write(pc, tag, 0x14, 0x04000000); 191 gtpci_write(gtpc, PCI_SCS1_BAR_SIZE(busno), 0x03ffffff); 192 gtpci_conf_write(pc, tag, 0x18, 0x10000000); 193 gtpci_write(gtpc, PCI_SCS2_BAR_SIZE(busno), 0x0fffffff); 194 gtpci_conf_write(pc, tag, 0x1c, 0x0c000000); 195 gtpci_write(gtpc, PCI_SCS3_BAR_SIZE(busno), 0x03ffffff); 196 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 197 198 #if 0 199 tag = gtpci_make_tag(pc, 0, 0, 1); 200 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 201 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 202 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 203 gtpci_write(gtpc, PCI_CS0_BAR_SIZE(busno), 0x00000000); 204 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 205 gtpci_write(gtpc, PCI_CS1_BAR_SIZE(busno), 0x00000000); 206 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 207 gtpci_write(gtpc, PCI_CS2_BAR_SIZE(busno), 0x00000000); 208 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 209 gtpci_write(gtpc, PCI_CS3_BAR_SIZE(busno), 0x00000000); 210 gtpci_conf_write(pc, tag, 0x20, 0xfff00000); 211 gtpci_write(gtpc, PCI_BOOTCS_BAR_SIZE(busno), 0x00000000); 212 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 213 214 tag = gtpci_make_tag(pc, 0, 0, 2); 215 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 216 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 217 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 218 gtpci_write(gtpc, PCI_P2P_MEM0_BAR_SIZE(busno), 0x00000000); 219 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 220 gtpci_write(gtpc, PCI_P2P_MEM1_BAR_SIZE(busno), 0x00000000); 221 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 222 gtpci_write(gtpc, PCI_P2P_IO_BAR_SIZE(busno), 0x00000000); 223 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 224 gtpci_write(gtpc, PCI_CPU_BAR_SIZE(busno), 0x00000000); 225 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 226 227 for (i=4; i<8; i++) { 228 tag = gtpci_make_tag(pc, 0, 0, i); 229 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 230 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 231 gtpci_conf_write(pc, tag, 0x10, 0xfff00000); 232 gtpci_conf_write(pc, tag, 0x14, 0xfff00000); 233 gtpci_conf_write(pc, tag, 0x18, 0xfff00000); 234 gtpci_conf_write(pc, tag, 0x1c, 0xfff00000); 235 gtpci_conf_write(pc, tag, 0x20, 0xfff00000); 236 gtpci_conf_write(pc, tag, 0x24, 0xfff00000); 237 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 238 } 239 #endif 240 switch (busno) { 241 case 0: 242 /* set Internal Mem to 1d000000 - 1dffffff */ 243 tag = gtpci_make_tag(pc, 0, 0, 0); 244 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 245 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 246 247 gtpci_conf_write(pc, tag, 0x20, 0xf1000008); 248 gtpci_conf_write(pc, tag, 0x24, 0xf1000001); 249 250 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 251 break; 252 case 1: 253 /* set Internal Mem to 1f000000 - 1fffffff */ 254 tag = gtpci_make_tag(pc, 0, 0, 0); 255 data = gtpci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 256 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 0); 257 258 gtpci_conf_write(pc, tag, 0x20, 0xf1000008); 259 gtpci_conf_write(pc, tag, 0x24, 0xf1000001); 260 261 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data); 262 break; 263 } 264 265 #if 0 266 tag = gtpci_make_tag(pc, 0, 0, 3); 267 gtpci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, data2); 268 #endif 269 270 data = ~(PCI_BARE_SCS0En | /* PCI_BARE_SCS1En | */ \ 271 PCI_BARE_SCS2En | /* PCI_BARE_SCS3En | */ \ 272 PCI_BARE_IntMemEn | PCI_BARE_IntIOEn); 273 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), data); 274 #endif /* PCI_NETBSD_CONFIGURE */ 275 } 276 277 void 278 gtpci_md_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, 279 int swiz, int *iline) 280 { 281 #ifdef PCI_NETBSD_CONFIGURE 282 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 283 if (gtpc->gtpc_busno == 0) 284 *iline = IRQ_GPP_BASE + 27; 285 else 286 *iline = IRQ_GPP_BASE + 29; 287 #endif /* PCI_NETBSD_CONFIGURE */ 288 } 289 290 void 291 gtpci_md_bus_devorder(pci_chipset_tag_t pc, int busno, char devs[]) 292 { 293 int i; 294 295 for (i = 0; i < 32; i++) 296 *devs++ = i; 297 *devs = -1; 298 } 299 300 int 301 gtpci_md_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, 302 pcireg_t id) 303 { 304 if (bus == 0 && dev == 0) 305 return 0; 306 307 return PCI_CONF_MAP_MEM|PCI_CONF_ENABLE_MEM; 308 } 309 310 int 311 gtpci_md_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 312 { 313 int pin = pa->pa_intrpin; 314 int line = pa->pa_intrline; 315 316 if (pin > 4) { 317 printf("pci_intr_map: bad interrupt pin %d\n", pin); 318 *ihp = -1; 319 return 1; 320 } 321 322 *ihp = line; 323 return 0; 324 } 325
Indexes created Mon Sep 29 21:09:56 GMT 2025