gt_mainbus.c revision 1.8
1 /* $NetBSD: gt_mainbus.c,v 1.8 2003/06/12 19:21:09 scw Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include "opt_ev64260.h" 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/extent.h> 43 #include <sys/malloc.h> 44 45 #define _POWERPC_BUS_DMA_PRIVATE 46 #include <machine/bus.h> 47 48 #include "opt_pci.h" 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 52 #include "opt_marvell.h" 53 #include <dev/marvell/gtreg.h> 54 #include <dev/marvell/gtvar.h> 55 #include <dev/marvell/gtpcireg.h> 56 #include <dev/marvell/gtpcivar.h> 57 58 extern struct powerpc_bus_space gt_mem_bs_tag; 59 extern struct powerpc_bus_space gt_pci0_mem_bs_tag; 60 extern struct powerpc_bus_space gt_pci0_io_bs_tag; 61 extern struct powerpc_bus_space gt_pci1_mem_bs_tag; 62 extern struct powerpc_bus_space gt_pci1_io_bs_tag; 63 64 struct powerpc_bus_dma_tag gt_bus_dma_tag = { 65 0, /* _bounce_thresh */ 66 _bus_dmamap_create, 67 _bus_dmamap_destroy, 68 _bus_dmamap_load, 69 _bus_dmamap_load_mbuf, 70 _bus_dmamap_load_uio, 71 _bus_dmamap_load_raw, 72 _bus_dmamap_unload, 73 _bus_dmamap_sync, 74 _bus_dmamem_alloc, 75 _bus_dmamem_free, 76 _bus_dmamem_map, 77 _bus_dmamem_unmap, 78 _bus_dmamem_mmap, 79 }; 80 81 const int gtpci_skipmask[2] = { 82 #ifdef PCI0_SKIPMASK 83 PCI0_SKIPMASK, 84 #else 85 0, 86 #endif 87 #ifdef PCI1_SKIPMASK 88 PCI1_SKIPMASK, 89 #else 90 0, 91 #endif 92 }; 93 94 static int gt_match(struct device *, struct cfdata *, void *); 95 static void gt_attach(struct device *, struct device *, void *); 96 97 CFATTACH_DECL(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL); 98 99 extern struct cfdriver gt_cd; 100 extern bus_space_handle_t gt_memh; 101 102 static int gt_found; 103 104 int 105 gt_match(struct device *parent, struct cfdata *cf, void *aux) 106 { 107 const char **busname = aux; 108 109 if (strcmp(*busname, gt_cd.cd_name) != 0) 110 return 0; 111 112 if (gt_found) 113 return 0; 114 115 return 1; 116 } 117 118 void 119 gt_attach(struct device *parent, struct device *self, void *aux) 120 { 121 struct gt_softc *gt = (struct gt_softc *) self; 122 123 gt->gt_dmat = >_bus_dma_tag; 124 gt->gt_memt = >_mem_bs_tag; 125 gt->gt_pci0_memt = >_pci0_mem_bs_tag; 126 gt->gt_pci0_iot = >_pci0_io_bs_tag; 127 gt->gt_pci0_host = TRUE; 128 gt->gt_pci1_memt = >_pci1_mem_bs_tag; 129 gt->gt_pci1_iot = >_pci1_io_bs_tag; 130 gt->gt_pci1_host = TRUE; 131 132 gt->gt_memh = gt_memh; 133 134 #if 0 135 GT_DecodeAddr_SET(gt, GT_PCI0_IO_Low_Decode, 136 gt_pci0_io_bs_tag.pbs_offset + gt_pci0_io_bs_tag.pbs_base); 137 GT_DecodeAddr_SET(gt, GT_PCI0_IO_High_Decode, 138 gt_pci0_io_bs_tag.pbs_offset + gt_pci0_io_bs_tag.pbs_limit - 1); 139 140 GT_DecodeAddr_SET(gt, GT_PCI1_IO_Low_Decode, 141 gt_pci1_io_bs_tag.pbs_offset + gt_pci1_io_bs_tag.pbs_base); 142 GT_DecodeAddr_SET(gt, GT_PCI1_IO_High_Decode, 143 gt_pci1_io_bs_tag.pbs_offset + gt_pci1_io_bs_tag.pbs_limit - 1); 144 145 GT_DecodeAddr_SET(gt, GT_PCI0_Mem0_Low_Decode, 146 gt_pci0_mem_bs_tag.pbs_offset + gt_pci0_mem_bs_tag.pbs_base); 147 GT_DecodeAddr_SET(gt, GT_PCI0_Mem0_High_Decode, 148 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_limit - 1); 149 150 GT_DecodeAddr_SET(gt, GT_PCI1_Mem0_Low_Decode, 151 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_base); 152 GT_DecodeAddr_SET(gt, GT_PCI1_Mem0_High_Decode, 153 gt_pci1_mem_bs_tag.pbs_offset + gt_pci1_mem_bs_tag.pbs_limit - 1); 154 #endif 155 156 gt_attach_common(gt); 157 } 158 159 void 160 gtpci_bus_configure(struct gtpci_chipset *gtpc) 161 { 162 #ifdef PCI_NETBSD_CONFIGURE 163 struct extent *ioext, *memext; 164 #if 0 165 extern int pci_conf_debug; 166 pci_conf_debug = 1; 167 #endif 168 169 switch (gtpc->gtpc_busno) { 170 case 0: 171 ioext = extent_create("pci0-io", 0x00000600, 0x0000ffff, 172 M_DEVBUF, NULL, 0, EX_NOWAIT); 173 memext = extent_create("pci0-mem", 174 gt_pci0_mem_bs_tag.pbs_base, 175 gt_pci0_mem_bs_tag.pbs_limit-1, 176 M_DEVBUF, NULL, 0, EX_NOWAIT); 177 break; 178 case 1: 179 ioext = extent_create("pci1-io", 0x00000600, 0x0000ffff, 180 M_DEVBUF, NULL, 0, EX_NOWAIT); 181 memext = extent_create("pci1-mem", 182 gt_pci1_mem_bs_tag.pbs_base, 183 gt_pci1_mem_bs_tag.pbs_limit-1, 184 M_DEVBUF, NULL, 0, EX_NOWAIT); 185 break; 186 } 187 188 pci_configure_bus(>pc->gtpc_pc, ioext, memext, NULL, 0, 32); 189 190 extent_destroy(ioext); 191 extent_destroy(memext); 192 #endif /* PCI_NETBSD_CONFIGURE */ 193 } 194 195 void 196 gtpci_md_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, 197 int swiz, int *iline) 198 { 199 #ifdef PCI_NETBSD_CONFIGURE 200 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 201 int line = (gtpc->gtpc_busno == 0 ? PCI0_GPPINTS : PCI1_GPPINTS); 202 *iline = (line >> (8 * ((pin + swiz - 1) & 3))) & 0xff; 203 if (*iline != 0xff) 204 *iline += IRQ_GPP_BASE; 205 #endif /* PCI_NETBSD_CONFIGURE */ 206 } 207 208 void 209 gtpci_md_bus_devorder(pci_chipset_tag_t pc, int busno, char devs[]) 210 { 211 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 212 int dev; 213 214 /* 215 * Don't bother probing the GT itself. 216 */ 217 for (dev = 0; dev < 32; dev++) { 218 if (PCI_CFG_GET_BUSNO(gtpc->gtpc_self) == busno && 219 (PCI_CFG_GET_DEVNO(gtpc->gtpc_self) == dev || 220 (gtpci_skipmask[gtpc->gtpc_busno] & (1 << dev)))) 221 continue; 222 223 *devs++ = dev; 224 } 225 *devs = -1; 226 } 227 228 int 229 gtpci_md_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, 230 pcireg_t id) 231 { 232 if (bus == 0 && dev == 0) /* don't configure GT */ 233 return 0; 234 235 return PCI_CONF_ALL; 236 } 237 238 int 239 gtpci_md_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 240 { 241 int pin = pa->pa_intrpin; 242 int line = pa->pa_intrline; 243 244 if (pin > 4 || line >= NIRQ) { 245 printf("pci_intr_map: bad interrupt pin %d\n", pin); 246 *ihp = -1; 247 return 1; 248 } 249 250 *ihp = line; 251 return 0; 252 } 253
Indexes created Tue Sep 30 07:10:03 GMT 2025