machdep.c revision 1.12
1 /* $NetBSD: machdep.c,v 1.12 2003/06/14 17:01:11 thorpej Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "opt_marvell.h" 35 #include "opt_ev64260.h" 36 #include "opt_compat_netbsd.h" 37 #include "opt_ddb.h" 38 #include "opt_inet.h" 39 #include "opt_ccitt.h" 40 #include "opt_iso.h" 41 #include "opt_ns.h" 42 #include "opt_ipkdb.h" 43 44 #include <sys/param.h> 45 #include <sys/conf.h> 46 #include <sys/device.h> 47 #include <sys/kernel.h> 48 #include <sys/malloc.h> 49 #include <sys/mount.h> 50 #include <sys/msgbuf.h> 51 #include <sys/proc.h> 52 #include <sys/reboot.h> 53 #include <sys/extent.h> 54 #include <sys/syslog.h> 55 #include <sys/systm.h> 56 #include <sys/termios.h> 57 #include <sys/ksyms.h> 58 59 #include <uvm/uvm.h> 60 #include <uvm/uvm_extern.h> 61 62 #include <net/netisr.h> 63 64 #include <machine/bus.h> 65 #include <machine/db_machdep.h> 66 #include <machine/intr.h> 67 #include <machine/pmap.h> 68 #include <machine/powerpc.h> 69 #include <machine/trap.h> 70 71 #include <powerpc/oea/bat.h> 72 #include <powerpc/marvell/watchdog.h> 73 74 #include <ddb/db_extern.h> 75 76 #include <dev/cons.h> 77 78 #include "vga.h" 79 #if (NVGA > 0) 80 #include <dev/ic/mc6845reg.h> 81 #include <dev/ic/pcdisplayvar.h> 82 #include <dev/ic/vgareg.h> 83 #include <dev/ic/vgavar.h> 84 #endif 85 86 #include "isa.h" 87 #if (NISA > 0) 88 void isa_intr_init(void); 89 #endif 90 91 #include "pckbc.h" 92 #if (NPCKBC > 0) 93 #include <dev/isa/isareg.h> 94 #include <dev/ic/i8042reg.h> 95 #include <dev/ic/pckbcvar.h> 96 #endif 97 98 #include "com.h" 99 #if (NCOM > 0) 100 #include <dev/ic/comreg.h> 101 #include <dev/ic/comvar.h> 102 #endif 103 104 #include <dev/marvell/gtreg.h> 105 #include <dev/marvell/gtvar.h> 106 #include <dev/marvell/gtethreg.h> 107 108 #include "gtmpsc.h" 109 #if (NGTMPSC > 0) 110 #include <dev/marvell/gtsdmareg.h> 111 #include <dev/marvell/gtmpscreg.h> 112 #include <dev/marvell/gtmpscvar.h> 113 #endif 114 115 #include "ksyms.h" 116 117 /* 118 * Global variables used here and there 119 */ 120 extern struct user *proc0paddr; 121 122 #define PMONMEMREGIONS 32 123 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 124 125 char *bootpath; 126 127 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 128 void strayintr(int); 129 int lcsplx(int); 130 void gt_bus_space_init(void); 131 void gt_find_memory(bus_space_tag_t, bus_space_handle_t, paddr_t); 132 void gt_halt(bus_space_tag_t, bus_space_handle_t); 133 void return_to_dink(int); 134 void calc_delayconst(void); 135 136 void kcomcnputs(dev_t, const char *); 137 138 struct powerpc_bus_space gt_pci0_mem_bs_tag = { 139 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 140 0x00000000, 0x00000000, 0x00000000, 141 }; 142 struct powerpc_bus_space gt_pci0_io_bs_tag = { 143 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 144 0x00000000, 0x00000000, 0x00000000, 145 }; 146 struct powerpc_bus_space gt_pci1_mem_bs_tag = { 147 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 148 0x00000000, 0x00000000, 0x00000000, 149 }; 150 struct powerpc_bus_space gt_pci1_io_bs_tag = { 151 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 152 0x00000000, 0x00000000, 0x00000000, 153 }; 154 struct powerpc_bus_space gt_obio0_bs_tag = { 155 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE, 156 0x00000000, 0x00000000, 0x00000000, 157 }; 158 struct powerpc_bus_space gt_obio1_bs_tag = { 159 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE, 160 0x00000000, 0x00000000, 0x00000000, 161 }; 162 struct powerpc_bus_space gt_obio2_bs_tag = { 163 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE, 164 0x00000000, 0x00000000, 0x00000000, 165 }; 166 struct powerpc_bus_space gt_obio3_bs_tag = { 167 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE, 168 0x00000000, 0x00000000, 0x00000000, 169 }; 170 struct powerpc_bus_space gt_bootcs_bs_tag = { 171 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 172 0x00000000, 0x00000000, 0x00000000, 173 }; 174 struct powerpc_bus_space gt_mem_bs_tag = { 175 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 176 GT_BASE, 0x00000000, 0x00010000, 177 }; 178 179 bus_space_handle_t gt_memh; 180 181 struct powerpc_bus_space *obio_bs_tags[5] = { 182 >_obio0_bs_tag, >_obio1_bs_tag, >_obio2_bs_tag, 183 >_obio3_bs_tag, >_bootcs_bs_tag 184 }; 185 186 static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)] 187 __attribute__((aligned(8))); 188 189 const struct gt_decode_info { 190 bus_addr_t low_decode; 191 bus_addr_t high_decode; 192 } decode_regs[] = { 193 { GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 194 { GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 195 { GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 196 { GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 197 { GT_CS0_Low_Decode, GT_CS0_High_Decode }, 198 { GT_CS1_Low_Decode, GT_CS1_High_Decode }, 199 { GT_CS2_Low_Decode, GT_CS2_High_Decode }, 200 { GT_CS3_Low_Decode, GT_CS3_High_Decode }, 201 { GT_BootCS_Low_Decode, GT_BootCS_High_Decode }, 202 }; 203 204 void 205 initppc(startkernel, endkernel, args, btinfo) 206 u_int startkernel, endkernel, args; 207 void *btinfo; 208 { 209 oea_batinit(0xf0000000, BAT_BL_256M); 210 oea_init((void (*)(void))ext_intr); 211 212 calc_delayconst(); /* Set CPU clock */ 213 214 DELAY(100000); 215 216 gt_bus_space_init(); 217 gt_find_memory(>_mem_bs_tag, gt_memh, roundup(endkernel, PAGE_SIZE)); 218 gt_halt(>_mem_bs_tag, gt_memh); 219 220 /* 221 * Now that we known how much memory, reinit the bats. 222 */ 223 oea_batinit(0xf0000000, BAT_BL_256M); 224 225 consinit(); 226 227 #if (NISA > 0) 228 isa_intr_init(); 229 #endif 230 231 /* 232 * Set the page size. 233 */ 234 uvm_setpagesize(); 235 236 /* 237 * Initialize pmap module. 238 */ 239 pmap_bootstrap(startkernel, endkernel); 240 241 #if NKSYMS || defined(DDB) || defined(LKM) 242 { 243 extern void *startsym, *endsym; 244 ksyms_init((int)((u_int)endsym - (u_int)startsym), 245 startsym, endsym); 246 } 247 #endif 248 #ifdef IPKDB 249 /* 250 * Now trap to IPKDB 251 */ 252 ipkdb_init(); 253 if (boothowto & RB_KDB) 254 ipkdb_connect(0); 255 #endif 256 } 257 258 void 259 mem_regions(struct mem_region **mem, struct mem_region **avail) 260 { 261 *mem = physmemr; 262 *avail = availmemr; 263 } 264 265 static __inline void 266 gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel) 267 { 268 physmemr[j].start = start; 269 physmemr[j].size = end - start; 270 if (start < endkernel) 271 start = endkernel; 272 availmemr[j].start = start; 273 availmemr[j].size = end - start; 274 } 275 276 void 277 gt_find_memory(bus_space_tag_t memt, bus_space_handle_t memh, 278 paddr_t endkernel) 279 { 280 paddr_t start, end; 281 int i, j = 0, first = 1; 282 283 /* 284 * Round kernel end to a page boundary. 285 */ 286 for (i = 0; i < 4; i++) { 287 paddr_t nstart, nend; 288 nstart = GT_LowAddr_GET(bus_space_read_4(>_mem_bs_tag, 289 gt_memh, decode_regs[i].low_decode)); 290 nend = GT_HighAddr_GET(bus_space_read_4(>_mem_bs_tag, 291 gt_memh, decode_regs[i].high_decode)) + 1; 292 if (nstart >= nend) 293 continue; 294 if (first) { 295 /* 296 * First entry? Just remember it. 297 */ 298 start = nstart; 299 end = nend; 300 first = 0; 301 } else if (nstart == end) { 302 /* 303 * Contiguous? Just update the end. 304 */ 305 end = nend; 306 } else { 307 /* 308 * Disjoint? record it. 309 */ 310 gt_record_memory(j, start, end, endkernel); 311 start = nstart; 312 end = nend; 313 j++; 314 } 315 } 316 gt_record_memory(j, start, end, endkernel); 317 } 318 319 /* 320 * Machine dependent startup code. 321 */ 322 void 323 cpu_startup(void) 324 { 325 register_t msr; 326 327 oea_startup(NULL); 328 329 /* 330 * Now that we have VM, malloc()s are OK in bus_space. 331 */ 332 bus_space_mallocok(); 333 334 /* 335 * Now allow hardware interrupts. 336 */ 337 splhigh(); 338 __asm __volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 339 : "=r"(msr) 340 : "K"(PSL_EE)); 341 } 342 343 /* 344 * consinit 345 * Initialize system console. 346 */ 347 void 348 consinit(void) 349 { 350 #ifdef MPSC_CONSOLE 351 /* PMON using MPSC0 @ 9600 */ 352 gtmpsccnattach(>_mem_bs_tag, gt_memh, MPSC_CONSOLE, 9600, 353 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 354 #else 355 /* PPCBOOT using COM1 @ 57600 */ 356 comcnattach(>_obio2_bs_tag, 0, 57600, 357 COM_FREQ*2, COM_TYPE_NORMAL, 358 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 359 #endif 360 } 361 362 #if (NPCKBC > 0) && (NPCKBD == 0) 363 /* 364 * glue code to support old console code with the 365 * mi keyboard controller driver 366 */ 367 int 368 pckbc_machdep_cnattach(pckbc_tag_t kbctag, pckbc_slot_t kbcslot) 369 { 370 #if (NPC > 0) 371 return (pcconskbd_cnattach(kbctag, kbcslot)); 372 #else 373 return (ENXIO); 374 #endif 375 } 376 #endif 377 378 /* 379 * Stray interrupts. 380 */ 381 void 382 strayintr(int irq) 383 { 384 log(LOG_ERR, "stray interrupt %d\n", irq); 385 } 386 387 /* 388 * Halt or reboot the machine after syncing/dumping according to howto. 389 */ 390 void 391 cpu_reboot(int howto, char *what) 392 { 393 static int syncing; 394 static char str[256]; 395 char *ap = str, *ap1 = ap; 396 397 boothowto = howto; 398 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 399 syncing = 1; 400 vfs_shutdown(); /* sync */ 401 resettodr(); /* set wall clock */ 402 } 403 splhigh(); 404 if (howto & RB_HALT) { 405 doshutdownhooks(); 406 printf("halted\n\n"); 407 cnhalt(); 408 while(1); 409 } 410 if (!cold && (howto & RB_DUMP)) 411 oea_dumpsys(); 412 doshutdownhooks(); 413 printf("rebooting\n\n"); 414 if (what && *what) { 415 if (strlen(what) > sizeof str - 5) 416 printf("boot string too large, ignored\n"); 417 else { 418 strcpy(str, what); 419 ap1 = ap = str + strlen(str); 420 *ap++ = ' '; 421 } 422 } 423 *ap++ = '-'; 424 if (howto & RB_SINGLE) 425 *ap++ = 's'; 426 if (howto & RB_KDB) 427 *ap++ = 'd'; 428 *ap++ = 0; 429 if (ap[-2] == '-') 430 *ap1 = 0; 431 #if 0 432 { 433 void mvpppc_reboot(void); 434 mvpppc_reboot(); 435 } 436 #endif 437 gt_watchdog_reset(); 438 /* NOTREACHED */ 439 while (1); 440 } 441 442 int 443 lcsplx(int ipl) 444 { 445 return spllower(ipl); 446 } 447 448 void 449 gt_halt(bus_space_tag_t gt_memt, bus_space_handle_t gt_memh) 450 { 451 int i; 452 u_int32_t data; 453 454 /* 455 * Shut down the MPSC ports 456 */ 457 for (i = 0; i < 2; i++) { 458 bus_space_write_4(gt_memt, gt_memh, 459 SDMA_U_SDCM(i), SDMA_SDCM_AR|SDMA_SDCM_AT); 460 for (;;) { 461 data = bus_space_read_4(gt_memt, gt_memh, 462 SDMA_U_SDCM(i)); 463 if (((SDMA_SDCM_AR|SDMA_SDCM_AT) & data) == 0) 464 break; 465 } 466 } 467 468 /* 469 * Shut down the Ethernets 470 */ 471 for (i = 0; i < 3; i++) { 472 bus_space_write_4(gt_memt, gt_memh, 473 ETH_ESDCMR(2), ETH_ESDCMR_AR|ETH_ESDCMR_AT); 474 for (;;) { 475 data = bus_space_read_4(gt_memt, gt_memh, 476 ETH_ESDCMR(i)); 477 if (((ETH_ESDCMR_AR|ETH_ESDCMR_AT) & data) == 0) 478 break; 479 } 480 data = bus_space_read_4(gt_memt, gt_memh, ETH_EPCR(i)); 481 data &= ~ETH_EPCR_EN; 482 bus_space_write_4(gt_memt, gt_memh, ETH_EPCR(i), data); 483 } 484 } 485 486 int 487 gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr) 488 { 489 enaddr[0] = 0x02; 490 enaddr[1] = 0x00; 491 enaddr[2] = 0x04; 492 enaddr[3] = 0x00; 493 enaddr[4] = 0x00; 494 enaddr[5] = 0x04 + macno; 495 496 return 0; 497 } 498 499 void 500 gt_bus_space_init(void) 501 { 502 bus_space_tag_t gt_memt = >_mem_bs_tag; 503 const struct gt_decode_info *di; 504 uint32_t datal, datah; 505 int error; 506 int bs = 0; 507 int j; 508 509 error = bus_space_init(>_mem_bs_tag, "gtmem", 510 ex_storage[bs], sizeof(ex_storage[bs])); 511 512 error = bus_space_map(gt_memt, 0, 0x10000, 0, >_memh); 513 514 for (j = 0, di = &decode_regs[4]; j < 5; j++, di++) { 515 struct powerpc_bus_space *memt = obio_bs_tags[j]; 516 datal = bus_space_read_4(gt_memt, gt_memh, di->low_decode); 517 datah = bus_space_read_4(gt_memt, gt_memh, di->high_decode); 518 519 if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) { 520 obio_bs_tags[j] = NULL; 521 continue; 522 } 523 memt->pbs_offset = GT_LowAddr_GET(datal); 524 memt->pbs_limit = GT_HighAddr_GET(datah) + 1 - 525 memt->pbs_offset; 526 527 error = bus_space_init(memt, "obio2", 528 ex_storage[bs], sizeof(ex_storage[bs])); 529 bs++; 530 } 531 532 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode); 533 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode); 534 #if defined(GT_PCI0_MEMBASE) 535 datal &= ~0xfff; 536 datal |= (GT_PCI0_MEMBASE >> 20); 537 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode, datal); 538 #endif 539 #if defined(GT_PCI0_MEMSIZE) 540 datah &= ~0xfff; 541 datah |= (GT_PCI0_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 542 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode, datal); 543 #endif 544 gt_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 545 gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 546 547 error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem", 548 ex_storage[bs], sizeof(ex_storage[bs])); 549 bs++; 550 551 /* 552 * Make sure PCI0 Memory is BAT mapped. 553 */ 554 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 555 oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 556 557 /* 558 * Make sure that I/O space start at 0. 559 */ 560 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 561 562 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode); 563 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode); 564 #if defined(GT_PCI0_IOBASE) 565 datal &= ~0xfff; 566 datal |= (GT_PCI0_IOBASE >> 20); 567 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode, datal); 568 #endif 569 #if defined(GT_PCI0_IOSIZE) 570 datah &= ~0xfff; 571 datah |= (GT_PCI0_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 572 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode, datal); 573 #endif 574 gt_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 575 gt_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 576 gt_pci0_io_bs_tag.pbs_offset; 577 578 error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport", 579 ex_storage[bs], sizeof(ex_storage[bs])); 580 bs++; 581 582 #if 0 583 error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent, 584 0x10000, 0x7F0000, EX_NOWAIT); 585 if (error) 586 panic("gt_bus_space_init: can't block out reserved " 587 "I/O space 0x10000-0x7fffff: error=%d\n", error); 588 #endif 589 590 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode); 591 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode); 592 #if defined(GT_PCI1_MEMBASE) 593 datal &= ~0xfff; 594 datal |= (GT_PCI1_MEMBASE >> 20); 595 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode, datal); 596 #endif 597 #if defined(GT_PCI1_MEMSIZE) 598 datah &= ~0xfff; 599 datah |= (GT_PCI1_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 600 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode, datal); 601 #endif 602 gt_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 603 gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 604 605 error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem", 606 ex_storage[bs], sizeof(ex_storage[bs])); 607 bs++; 608 609 /* 610 * Make sure PCI1 Memory is BAT mapped. 611 */ 612 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 613 oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 614 615 /* 616 * Make sure that I/O space start at 0. 617 */ 618 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 619 620 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode); 621 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode); 622 #if defined(GT_PCI1_IOBASE) 623 datal &= ~0xfff; 624 datal |= (GT_PCI1_IOBASE >> 20); 625 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode, datal); 626 #endif 627 #if defined(GT_PCI1_IOSIZE) 628 datah &= ~0xfff; 629 datah |= (GT_PCI1_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 630 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode, datal); 631 #endif 632 gt_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 633 gt_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 634 gt_pci1_io_bs_tag.pbs_offset; 635 636 error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport", 637 ex_storage[bs], sizeof(ex_storage[bs])); 638 bs++; 639 640 #if 0 641 error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent, 642 0x10000, 0x7F0000, EX_NOWAIT); 643 if (error) 644 panic("gt_bus_space_init: can't block out reserved " 645 "I/O space 0x10000-0x7fffff: error=%d\n", error); 646 #endif 647 } 648
Indexes created Thu Oct 02 01:09:59 GMT 2025