machdep.c revision 1.16
1 /* $NetBSD: machdep.c,v 1.16 2004/03/13 07:22:21 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.16 2004/03/13 07:22:21 matt Exp $"); 36 37 #include "opt_marvell.h" 38 #include "opt_ev64260.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_inet.h" 42 #include "opt_ccitt.h" 43 #include "opt_iso.h" 44 #include "opt_ns.h" 45 #include "opt_ipkdb.h" 46 47 #include <sys/param.h> 48 #include <sys/conf.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/mount.h> 53 #include <sys/msgbuf.h> 54 #include <sys/proc.h> 55 #include <sys/reboot.h> 56 #include <sys/extent.h> 57 #include <sys/syslog.h> 58 #include <sys/systm.h> 59 #include <sys/termios.h> 60 #include <sys/ksyms.h> 61 62 #include <uvm/uvm.h> 63 #include <uvm/uvm_extern.h> 64 65 #include <net/netisr.h> 66 67 #include <machine/bus.h> 68 #include <machine/db_machdep.h> 69 #include <machine/intr.h> 70 #include <machine/pmap.h> 71 #include <machine/powerpc.h> 72 #include <machine/trap.h> 73 74 #include <powerpc/oea/bat.h> 75 #include <powerpc/marvell/watchdog.h> 76 77 #include <ddb/db_extern.h> 78 79 #include <dev/cons.h> 80 81 #include "vga.h" 82 #if (NVGA > 0) 83 #include <dev/ic/mc6845reg.h> 84 #include <dev/ic/pcdisplayvar.h> 85 #include <dev/ic/vgareg.h> 86 #include <dev/ic/vgavar.h> 87 #endif 88 89 #include "isa.h" 90 #if (NISA > 0) 91 void isa_intr_init(void); 92 #endif 93 94 #include "com.h" 95 #if (NCOM > 0) 96 #include <dev/ic/comreg.h> 97 #include <dev/ic/comvar.h> 98 #endif 99 100 #include <dev/marvell/gtreg.h> 101 #include <dev/marvell/gtvar.h> 102 #include <dev/marvell/gtethreg.h> 103 104 #include "gtmpsc.h" 105 #if (NGTMPSC > 0) 106 #include <dev/marvell/gtsdmareg.h> 107 #include <dev/marvell/gtmpscreg.h> 108 #include <dev/marvell/gtmpscvar.h> 109 #endif 110 111 #include "ksyms.h" 112 113 /* 114 * Global variables used here and there 115 */ 116 extern struct user *proc0paddr; 117 118 #define PMONMEMREGIONS 32 119 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 120 121 char *bootpath; 122 123 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 124 void strayintr(int); 125 int lcsplx(int); 126 void gt_bus_space_init(void); 127 void gt_find_memory(bus_space_tag_t, bus_space_handle_t, paddr_t); 128 void gt_halt(bus_space_tag_t, bus_space_handle_t); 129 void return_to_dink(int); 130 void calc_delayconst(void); 131 132 void kcomcnputs(dev_t, const char *); 133 134 struct powerpc_bus_space gt_pci0_mem_bs_tag = { 135 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 136 0x00000000, 0x00000000, 0x00000000, 137 }; 138 struct powerpc_bus_space gt_pci0_io_bs_tag = { 139 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 140 0x00000000, 0x00000000, 0x00000000, 141 }; 142 struct powerpc_bus_space gt_pci1_mem_bs_tag = { 143 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 144 0x00000000, 0x00000000, 0x00000000, 145 }; 146 struct powerpc_bus_space gt_pci1_io_bs_tag = { 147 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 148 0x00000000, 0x00000000, 0x00000000, 149 }; 150 struct powerpc_bus_space gt_obio0_bs_tag = { 151 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE, 152 0x00000000, 0x00000000, 0x00000000, 153 }; 154 struct powerpc_bus_space gt_obio1_bs_tag = { 155 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE, 156 0x00000000, 0x00000000, 0x00000000, 157 }; 158 struct powerpc_bus_space gt_obio2_bs_tag = { 159 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE, 160 0x00000000, 0x00000000, 0x00000000, 161 }; 162 struct powerpc_bus_space gt_obio3_bs_tag = { 163 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE, 164 0x00000000, 0x00000000, 0x00000000, 165 }; 166 struct powerpc_bus_space gt_bootcs_bs_tag = { 167 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 168 0x00000000, 0x00000000, 0x00000000, 169 }; 170 struct powerpc_bus_space gt_mem_bs_tag = { 171 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 172 GT_BASE, 0x00000000, 0x00010000, 173 }; 174 175 bus_space_handle_t gt_memh; 176 177 struct powerpc_bus_space *obio_bs_tags[5] = { 178 >_obio0_bs_tag, >_obio1_bs_tag, >_obio2_bs_tag, 179 >_obio3_bs_tag, >_bootcs_bs_tag 180 }; 181 182 static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)] 183 __attribute__((aligned(8))); 184 185 const struct gt_decode_info { 186 bus_addr_t low_decode; 187 bus_addr_t high_decode; 188 } decode_regs[] = { 189 { GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 190 { GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 191 { GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 192 { GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 193 { GT_CS0_Low_Decode, GT_CS0_High_Decode }, 194 { GT_CS1_Low_Decode, GT_CS1_High_Decode }, 195 { GT_CS2_Low_Decode, GT_CS2_High_Decode }, 196 { GT_CS3_Low_Decode, GT_CS3_High_Decode }, 197 { GT_BootCS_Low_Decode, GT_BootCS_High_Decode }, 198 }; 199 200 void 201 initppc(startkernel, endkernel, args, btinfo) 202 u_int startkernel, endkernel, args; 203 void *btinfo; 204 { 205 oea_batinit(0xf0000000, BAT_BL_256M); 206 oea_init((void (*)(void))ext_intr); 207 208 calc_delayconst(); /* Set CPU clock */ 209 210 DELAY(100000); 211 212 gt_bus_space_init(); 213 gt_find_memory(>_mem_bs_tag, gt_memh, roundup(endkernel, PAGE_SIZE)); 214 gt_halt(>_mem_bs_tag, gt_memh); 215 216 /* 217 * Now that we known how much memory, reinit the bats. 218 */ 219 oea_batinit(0xf0000000, BAT_BL_256M); 220 221 consinit(); 222 223 #if (NISA > 0) 224 isa_intr_init(); 225 #endif 226 227 /* 228 * Set the page size. 229 */ 230 uvm_setpagesize(); 231 232 /* 233 * Initialize pmap module. 234 */ 235 pmap_bootstrap(startkernel, endkernel); 236 237 #if NKSYMS || defined(DDB) || defined(LKM) 238 { 239 extern void *startsym, *endsym; 240 ksyms_init((int)((u_int)endsym - (u_int)startsym), 241 startsym, endsym); 242 } 243 #endif 244 #ifdef IPKDB 245 /* 246 * Now trap to IPKDB 247 */ 248 ipkdb_init(); 249 if (boothowto & RB_KDB) 250 ipkdb_connect(0); 251 #endif 252 } 253 254 void 255 mem_regions(struct mem_region **mem, struct mem_region **avail) 256 { 257 *mem = physmemr; 258 *avail = availmemr; 259 } 260 261 static __inline void 262 gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel) 263 { 264 physmemr[j].start = start; 265 physmemr[j].size = end - start; 266 if (start < endkernel) 267 start = endkernel; 268 availmemr[j].start = start; 269 availmemr[j].size = end - start; 270 } 271 272 void 273 gt_find_memory(bus_space_tag_t memt, bus_space_handle_t memh, 274 paddr_t endkernel) 275 { 276 paddr_t start = ~0, end = 0; 277 int i, j = 0, first = 1; 278 279 /* 280 * Round kernel end to a page boundary. 281 */ 282 for (i = 0; i < 4; i++) { 283 paddr_t nstart, nend; 284 nstart = GT_LowAddr_GET(bus_space_read_4(>_mem_bs_tag, 285 gt_memh, decode_regs[i].low_decode)); 286 nend = GT_HighAddr_GET(bus_space_read_4(>_mem_bs_tag, 287 gt_memh, decode_regs[i].high_decode)) + 1; 288 if (nstart >= nend) 289 continue; 290 if (first) { 291 /* 292 * First entry? Just remember it. 293 */ 294 start = nstart; 295 end = nend; 296 first = 0; 297 } else if (nstart == end) { 298 /* 299 * Contiguous? Just update the end. 300 */ 301 end = nend; 302 } else { 303 /* 304 * Disjoint? record it. 305 */ 306 gt_record_memory(j, start, end, endkernel); 307 start = nstart; 308 end = nend; 309 j++; 310 } 311 } 312 gt_record_memory(j, start, end, endkernel); 313 } 314 315 /* 316 * Machine dependent startup code. 317 */ 318 void 319 cpu_startup(void) 320 { 321 register_t msr; 322 323 oea_startup(NULL); 324 325 /* 326 * Now that we have VM, malloc()s are OK in bus_space. 327 */ 328 bus_space_mallocok(); 329 330 /* 331 * Now allow hardware interrupts. 332 */ 333 splhigh(); 334 __asm __volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 335 : "=r"(msr) 336 : "K"(PSL_EE)); 337 } 338 339 /* 340 * consinit 341 * Initialize system console. 342 */ 343 void 344 consinit(void) 345 { 346 #ifdef MPSC_CONSOLE 347 /* PMON using MPSC0 @ 9600 */ 348 gtmpsccnattach(>_mem_bs_tag, gt_memh, MPSC_CONSOLE, 9600, 349 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 350 #else 351 /* PPCBOOT using COM1 @ 57600 */ 352 comcnattach(>_obio2_bs_tag, 0, 57600, 353 COM_FREQ*2, COM_TYPE_NORMAL, 354 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 355 #endif 356 } 357 358 /* 359 * Stray interrupts. 360 */ 361 void 362 strayintr(int irq) 363 { 364 log(LOG_ERR, "stray interrupt %d\n", irq); 365 } 366 367 /* 368 * Halt or reboot the machine after syncing/dumping according to howto. 369 */ 370 void 371 cpu_reboot(int howto, char *what) 372 { 373 static int syncing; 374 static char str[256]; 375 char *ap = str, *ap1 = ap; 376 377 boothowto = howto; 378 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 379 syncing = 1; 380 vfs_shutdown(); /* sync */ 381 resettodr(); /* set wall clock */ 382 } 383 splhigh(); 384 if (howto & RB_HALT) { 385 doshutdownhooks(); 386 printf("halted\n\n"); 387 cnhalt(); 388 while(1); 389 } 390 if (!cold && (howto & RB_DUMP)) 391 oea_dumpsys(); 392 doshutdownhooks(); 393 printf("rebooting\n\n"); 394 if (what && *what) { 395 if (strlen(what) > sizeof str - 5) 396 printf("boot string too large, ignored\n"); 397 else { 398 strcpy(str, what); 399 ap1 = ap = str + strlen(str); 400 *ap++ = ' '; 401 } 402 } 403 *ap++ = '-'; 404 if (howto & RB_SINGLE) 405 *ap++ = 's'; 406 if (howto & RB_KDB) 407 *ap++ = 'd'; 408 *ap++ = 0; 409 if (ap[-2] == '-') 410 *ap1 = 0; 411 #if 0 412 { 413 void mvpppc_reboot(void); 414 mvpppc_reboot(); 415 } 416 #endif 417 gt_watchdog_reset(); 418 /* NOTREACHED */ 419 while (1); 420 } 421 422 int 423 lcsplx(int ipl) 424 { 425 return spllower(ipl); 426 } 427 428 void 429 gt_halt(bus_space_tag_t gt_memt, bus_space_handle_t gt_memh) 430 { 431 int i; 432 u_int32_t data; 433 434 /* 435 * Shut down the MPSC ports 436 */ 437 for (i = 0; i < 2; i++) { 438 bus_space_write_4(gt_memt, gt_memh, 439 SDMA_U_SDCM(i), SDMA_SDCM_AR|SDMA_SDCM_AT); 440 for (;;) { 441 data = bus_space_read_4(gt_memt, gt_memh, 442 SDMA_U_SDCM(i)); 443 if (((SDMA_SDCM_AR|SDMA_SDCM_AT) & data) == 0) 444 break; 445 } 446 } 447 448 /* 449 * Shut down the Ethernets 450 */ 451 for (i = 0; i < 3; i++) { 452 bus_space_write_4(gt_memt, gt_memh, 453 ETH_ESDCMR(2), ETH_ESDCMR_AR|ETH_ESDCMR_AT); 454 for (;;) { 455 data = bus_space_read_4(gt_memt, gt_memh, 456 ETH_ESDCMR(i)); 457 if (((ETH_ESDCMR_AR|ETH_ESDCMR_AT) & data) == 0) 458 break; 459 } 460 data = bus_space_read_4(gt_memt, gt_memh, ETH_EPCR(i)); 461 data &= ~ETH_EPCR_EN; 462 bus_space_write_4(gt_memt, gt_memh, ETH_EPCR(i), data); 463 } 464 } 465 466 int 467 gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr) 468 { 469 enaddr[0] = 0x02; 470 enaddr[1] = 0x00; 471 enaddr[2] = 0x04; 472 enaddr[3] = 0x00; 473 enaddr[4] = 0x00; 474 enaddr[5] = 0x04 + macno; 475 476 return 0; 477 } 478 479 void 480 gt_bus_space_init(void) 481 { 482 bus_space_tag_t gt_memt = >_mem_bs_tag; 483 const struct gt_decode_info *di; 484 uint32_t datal, datah; 485 int error; 486 int bs = 0; 487 int j; 488 489 error = bus_space_init(>_mem_bs_tag, "gtmem", 490 ex_storage[bs], sizeof(ex_storage[bs])); 491 492 error = bus_space_map(gt_memt, 0, 0x10000, 0, >_memh); 493 494 for (j = 0, di = &decode_regs[4]; j < 5; j++, di++) { 495 struct powerpc_bus_space *memt = obio_bs_tags[j]; 496 datal = bus_space_read_4(gt_memt, gt_memh, di->low_decode); 497 datah = bus_space_read_4(gt_memt, gt_memh, di->high_decode); 498 499 if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) { 500 obio_bs_tags[j] = NULL; 501 continue; 502 } 503 memt->pbs_offset = GT_LowAddr_GET(datal); 504 memt->pbs_limit = GT_HighAddr_GET(datah) + 1 - 505 memt->pbs_offset; 506 507 error = bus_space_init(memt, "obio2", 508 ex_storage[bs], sizeof(ex_storage[bs])); 509 bs++; 510 } 511 512 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode); 513 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode); 514 #if defined(GT_PCI0_MEMBASE) 515 datal &= ~0xfff; 516 datal |= (GT_PCI0_MEMBASE >> 20); 517 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode, datal); 518 #endif 519 #if defined(GT_PCI0_MEMSIZE) 520 datah &= ~0xfff; 521 datah |= (GT_PCI0_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 522 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode, datal); 523 #endif 524 gt_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 525 gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 526 527 error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem", 528 ex_storage[bs], sizeof(ex_storage[bs])); 529 bs++; 530 531 /* 532 * Make sure PCI0 Memory is BAT mapped. 533 */ 534 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 535 oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 536 537 /* 538 * Make sure that I/O space start at 0. 539 */ 540 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 541 542 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode); 543 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode); 544 #if defined(GT_PCI0_IOBASE) 545 datal &= ~0xfff; 546 datal |= (GT_PCI0_IOBASE >> 20); 547 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode, datal); 548 #endif 549 #if defined(GT_PCI0_IOSIZE) 550 datah &= ~0xfff; 551 datah |= (GT_PCI0_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 552 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode, datal); 553 #endif 554 gt_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 555 gt_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 556 gt_pci0_io_bs_tag.pbs_offset; 557 558 error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport", 559 ex_storage[bs], sizeof(ex_storage[bs])); 560 bs++; 561 562 #if 0 563 error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent, 564 0x10000, 0x7F0000, EX_NOWAIT); 565 if (error) 566 panic("gt_bus_space_init: can't block out reserved " 567 "I/O space 0x10000-0x7fffff: error=%d\n", error); 568 #endif 569 570 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode); 571 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode); 572 #if defined(GT_PCI1_MEMBASE) 573 datal &= ~0xfff; 574 datal |= (GT_PCI1_MEMBASE >> 20); 575 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode, datal); 576 #endif 577 #if defined(GT_PCI1_MEMSIZE) 578 datah &= ~0xfff; 579 datah |= (GT_PCI1_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 580 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode, datal); 581 #endif 582 gt_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 583 gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 584 585 error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem", 586 ex_storage[bs], sizeof(ex_storage[bs])); 587 bs++; 588 589 /* 590 * Make sure PCI1 Memory is BAT mapped. 591 */ 592 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 593 oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 594 595 /* 596 * Make sure that I/O space start at 0. 597 */ 598 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 599 600 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode); 601 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode); 602 #if defined(GT_PCI1_IOBASE) 603 datal &= ~0xfff; 604 datal |= (GT_PCI1_IOBASE >> 20); 605 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode, datal); 606 #endif 607 #if defined(GT_PCI1_IOSIZE) 608 datah &= ~0xfff; 609 datah |= (GT_PCI1_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 610 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode, datal); 611 #endif 612 gt_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 613 gt_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 614 gt_pci1_io_bs_tag.pbs_offset; 615 616 error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport", 617 ex_storage[bs], sizeof(ex_storage[bs])); 618 bs++; 619 620 #if 0 621 error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent, 622 0x10000, 0x7F0000, EX_NOWAIT); 623 if (error) 624 panic("gt_bus_space_init: can't block out reserved " 625 "I/O space 0x10000-0x7fffff: error=%d\n", error); 626 #endif 627 } 628
Indexes created Tue Sep 30 20:09:53 GMT 2025