machdep.c revision 1.19.38.1
1 /* $NetBSD: machdep.c,v 1.19.38.1 2007/05/22 15:59:26 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.19.38.1 2007/05/22 15:59:26 matt Exp $"); 36 37 #include "opt_marvell.h" 38 #include "opt_ev64260.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_inet.h" 42 #include "opt_ccitt.h" 43 #include "opt_iso.h" 44 #include "opt_ns.h" 45 #include "opt_ipkdb.h" 46 47 #include <sys/param.h> 48 #include <sys/conf.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/mount.h> 53 #include <sys/msgbuf.h> 54 #include <sys/proc.h> 55 #include <sys/reboot.h> 56 #include <sys/extent.h> 57 #include <sys/syslog.h> 58 #include <sys/systm.h> 59 #include <sys/termios.h> 60 #include <sys/ksyms.h> 61 62 #include <uvm/uvm.h> 63 #include <uvm/uvm_extern.h> 64 65 #include <net/netisr.h> 66 67 #include <machine/bus.h> 68 #include <machine/db_machdep.h> 69 #include <machine/intr.h> 70 #include <machine/pmap.h> 71 #include <machine/powerpc.h> 72 #include <machine/trap.h> 73 74 #include <powerpc/oea/bat.h> 75 #include <powerpc/marvell/watchdog.h> 76 #include <powerpc/pic/picvar.h> 77 78 #include <ddb/db_extern.h> 79 80 #include <dev/cons.h> 81 82 #include "vga.h" 83 #if (NVGA > 0) 84 #include <dev/ic/mc6845reg.h> 85 #include <dev/ic/pcdisplayvar.h> 86 #include <dev/ic/vgareg.h> 87 #include <dev/ic/vgavar.h> 88 #endif 89 90 #include "isa.h" 91 #if (NISA > 0) 92 void isa_intr_init(void); 93 #endif 94 95 #include "com.h" 96 #if (NCOM > 0) 97 #include <dev/ic/comreg.h> 98 #include <dev/ic/comvar.h> 99 #endif 100 101 #include <dev/marvell/gtreg.h> 102 #include <dev/marvell/gtvar.h> 103 #include <dev/marvell/gtethreg.h> 104 105 #include "gtmpsc.h" 106 #if (NGTMPSC > 0) 107 #include <dev/marvell/gtsdmareg.h> 108 #include <dev/marvell/gtmpscreg.h> 109 #include <dev/marvell/gtmpscvar.h> 110 #endif 111 112 #include "ksyms.h" 113 114 /* 115 * Global variables used here and there 116 */ 117 extern struct user *proc0paddr; 118 119 #define PMONMEMREGIONS 32 120 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 121 122 char *bootpath; 123 124 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 125 void strayintr(int); 126 int lcsplx(int); 127 void gt_bus_space_init(void); 128 void gt_find_memory(bus_space_tag_t, bus_space_handle_t, paddr_t); 129 void gt_halt(bus_space_tag_t, bus_space_handle_t); 130 void return_to_dink(int); 131 void calc_delayconst(void); 132 133 void kcomcnputs(dev_t, const char *); 134 135 struct powerpc_bus_space gt_pci0_mem_bs_tag = { 136 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 137 0x00000000, 0x00000000, 0x00000000, 138 }; 139 struct powerpc_bus_space gt_pci0_io_bs_tag = { 140 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 141 0x00000000, 0x00000000, 0x00000000, 142 }; 143 struct powerpc_bus_space gt_pci1_mem_bs_tag = { 144 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 145 0x00000000, 0x00000000, 0x00000000, 146 }; 147 struct powerpc_bus_space gt_pci1_io_bs_tag = { 148 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 149 0x00000000, 0x00000000, 0x00000000, 150 }; 151 struct powerpc_bus_space gt_obio0_bs_tag = { 152 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE, 153 0x00000000, 0x00000000, 0x00000000, 154 }; 155 struct powerpc_bus_space gt_obio1_bs_tag = { 156 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE, 157 0x00000000, 0x00000000, 0x00000000, 158 }; 159 struct powerpc_bus_space gt_obio2_bs_tag = { 160 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE, 161 0x00000000, 0x00000000, 0x00000000, 162 }; 163 struct powerpc_bus_space gt_obio3_bs_tag = { 164 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE, 165 0x00000000, 0x00000000, 0x00000000, 166 }; 167 struct powerpc_bus_space gt_bootcs_bs_tag = { 168 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 169 0x00000000, 0x00000000, 0x00000000, 170 }; 171 struct powerpc_bus_space gt_mem_bs_tag = { 172 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 173 GT_BASE, 0x00000000, 0x00010000, 174 }; 175 176 bus_space_handle_t gt_memh; 177 178 struct powerpc_bus_space *obio_bs_tags[5] = { 179 >_obio0_bs_tag, >_obio1_bs_tag, >_obio2_bs_tag, 180 >_obio3_bs_tag, >_bootcs_bs_tag 181 }; 182 183 static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)] 184 __attribute__((aligned(8))); 185 186 const struct gt_decode_info { 187 bus_addr_t low_decode; 188 bus_addr_t high_decode; 189 } decode_regs[] = { 190 { GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 191 { GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 192 { GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 193 { GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 194 { GT_CS0_Low_Decode, GT_CS0_High_Decode }, 195 { GT_CS1_Low_Decode, GT_CS1_High_Decode }, 196 { GT_CS2_Low_Decode, GT_CS2_High_Decode }, 197 { GT_CS3_Low_Decode, GT_CS3_High_Decode }, 198 { GT_BootCS_Low_Decode, GT_BootCS_High_Decode }, 199 }; 200 201 void 202 initppc(startkernel, endkernel, args, btinfo) 203 u_int startkernel, endkernel, args; 204 void *btinfo; 205 { 206 oea_batinit(0xf0000000, BAT_BL_256M); 207 oea_init(pic_ext_intr); 208 209 calc_delayconst(); /* Set CPU clock */ 210 211 DELAY(100000); 212 213 gt_bus_space_init(); 214 gt_find_memory(>_mem_bs_tag, gt_memh, roundup(endkernel, PAGE_SIZE)); 215 gt_halt(>_mem_bs_tag, gt_memh); 216 217 /* 218 * Now that we known how much memory, reinit the bats. 219 */ 220 oea_batinit(0xf0000000, BAT_BL_256M); 221 222 consinit(); 223 224 #if (NISA > 0) 225 isa_intr_init(); 226 #endif 227 228 /* 229 * Set the page size. 230 */ 231 uvm_setpagesize(); 232 233 /* 234 * Initialize pmap module. 235 */ 236 pmap_bootstrap(startkernel, endkernel); 237 238 #if NKSYMS || defined(DDB) || defined(LKM) 239 { 240 extern void *startsym, *endsym; 241 ksyms_init((int)((u_int)endsym - (u_int)startsym), 242 startsym, endsym); 243 } 244 #endif 245 #ifdef IPKDB 246 /* 247 * Now trap to IPKDB 248 */ 249 ipkdb_init(); 250 if (boothowto & RB_KDB) 251 ipkdb_connect(0); 252 #endif 253 } 254 255 void 256 mem_regions(struct mem_region **mem, struct mem_region **avail) 257 { 258 *mem = physmemr; 259 *avail = availmemr; 260 } 261 262 static inline void 263 gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel) 264 { 265 physmemr[j].start = start; 266 physmemr[j].size = end - start; 267 if (start < endkernel) 268 start = endkernel; 269 availmemr[j].start = start; 270 availmemr[j].size = end - start; 271 } 272 273 void 274 gt_find_memory(bus_space_tag_t memt, bus_space_handle_t memh, 275 paddr_t endkernel) 276 { 277 paddr_t start = ~0, end = 0; 278 int i, j = 0, first = 1; 279 280 /* 281 * Round kernel end to a page boundary. 282 */ 283 for (i = 0; i < 4; i++) { 284 paddr_t nstart, nend; 285 nstart = GT_LowAddr_GET(bus_space_read_4(>_mem_bs_tag, 286 gt_memh, decode_regs[i].low_decode)); 287 nend = GT_HighAddr_GET(bus_space_read_4(>_mem_bs_tag, 288 gt_memh, decode_regs[i].high_decode)) + 1; 289 if (nstart >= nend) 290 continue; 291 if (first) { 292 /* 293 * First entry? Just remember it. 294 */ 295 start = nstart; 296 end = nend; 297 first = 0; 298 } else if (nstart == end) { 299 /* 300 * Contiguous? Just update the end. 301 */ 302 end = nend; 303 } else { 304 /* 305 * Disjoint? record it. 306 */ 307 gt_record_memory(j, start, end, endkernel); 308 start = nstart; 309 end = nend; 310 j++; 311 } 312 } 313 gt_record_memory(j, start, end, endkernel); 314 } 315 316 /* 317 * Machine dependent startup code. 318 */ 319 void 320 cpu_startup(void) 321 { 322 register_t msr; 323 324 oea_startup(NULL); 325 326 /* 327 * Now that we have VM, malloc()s are OK in bus_space. 328 */ 329 bus_space_mallocok(); 330 331 /* 332 * Now allow hardware interrupts. 333 */ 334 splhigh(); 335 __asm volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 336 : "=r"(msr) 337 : "K"(PSL_EE)); 338 } 339 340 /* 341 * consinit 342 * Initialize system console. 343 */ 344 void 345 consinit(void) 346 { 347 #ifdef MPSC_CONSOLE 348 /* PMON using MPSC0 @ 9600 */ 349 gtmpsccnattach(>_mem_bs_tag, gt_memh, MPSC_CONSOLE, 9600, 350 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 351 #else 352 /* PPCBOOT using COM1 @ 57600 */ 353 comcnattach(>_obio2_bs_tag, 0, 57600, 354 COM_FREQ*2, COM_TYPE_NORMAL, 355 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 356 #endif 357 } 358 359 /* 360 * Stray interrupts. 361 */ 362 void 363 strayintr(int irq) 364 { 365 log(LOG_ERR, "stray interrupt %d\n", irq); 366 } 367 368 /* 369 * Halt or reboot the machine after syncing/dumping according to howto. 370 */ 371 void 372 cpu_reboot(int howto, char *what) 373 { 374 static int syncing; 375 static char str[256]; 376 char *ap = str, *ap1 = ap; 377 378 boothowto = howto; 379 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 380 syncing = 1; 381 vfs_shutdown(); /* sync */ 382 resettodr(); /* set wall clock */ 383 } 384 splhigh(); 385 if (howto & RB_HALT) { 386 doshutdownhooks(); 387 printf("halted\n\n"); 388 cnhalt(); 389 while(1); 390 } 391 if (!cold && (howto & RB_DUMP)) 392 oea_dumpsys(); 393 doshutdownhooks(); 394 printf("rebooting\n\n"); 395 if (what && *what) { 396 if (strlen(what) > sizeof str - 5) 397 printf("boot string too large, ignored\n"); 398 else { 399 strcpy(str, what); 400 ap1 = ap = str + strlen(str); 401 *ap++ = ' '; 402 } 403 } 404 *ap++ = '-'; 405 if (howto & RB_SINGLE) 406 *ap++ = 's'; 407 if (howto & RB_KDB) 408 *ap++ = 'd'; 409 *ap++ = 0; 410 if (ap[-2] == '-') 411 *ap1 = 0; 412 #if 0 413 { 414 void mvpppc_reboot(void); 415 mvpppc_reboot(); 416 } 417 #endif 418 gt_watchdog_reset(); 419 /* NOTREACHED */ 420 while (1); 421 } 422 423 int 424 lcsplx(int ipl) 425 { 426 return spllower(ipl); 427 } 428 429 void 430 gt_halt(bus_space_tag_t memt, bus_space_handle_t memh) 431 { 432 int i; 433 u_int32_t data; 434 435 /* 436 * Shut down the MPSC ports 437 */ 438 for (i = 0; i < 2; i++) { 439 bus_space_write_4(memt, memh, 440 SDMA_U_SDCM(i), SDMA_SDCM_AR|SDMA_SDCM_AT); 441 for (;;) { 442 data = bus_space_read_4(memt, memh, 443 SDMA_U_SDCM(i)); 444 if (((SDMA_SDCM_AR|SDMA_SDCM_AT) & data) == 0) 445 break; 446 } 447 } 448 449 /* 450 * Shut down the Ethernets 451 */ 452 for (i = 0; i < 3; i++) { 453 bus_space_write_4(memt, memh, 454 ETH_ESDCMR(2), ETH_ESDCMR_AR|ETH_ESDCMR_AT); 455 for (;;) { 456 data = bus_space_read_4(memt, memh, 457 ETH_ESDCMR(i)); 458 if (((ETH_ESDCMR_AR|ETH_ESDCMR_AT) & data) == 0) 459 break; 460 } 461 data = bus_space_read_4(memt, memh, ETH_EPCR(i)); 462 data &= ~ETH_EPCR_EN; 463 bus_space_write_4(memt, memh, ETH_EPCR(i), data); 464 } 465 } 466 467 int 468 gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr) 469 { 470 enaddr[0] = 0x02; 471 enaddr[1] = 0x00; 472 enaddr[2] = 0x04; 473 enaddr[3] = 0x00; 474 enaddr[4] = 0x00; 475 enaddr[5] = 0x04 + macno; 476 477 return 0; 478 } 479 480 void 481 gt_bus_space_init(void) 482 { 483 bus_space_tag_t gt_memt = >_mem_bs_tag; 484 const struct gt_decode_info *di; 485 uint32_t datal, datah; 486 int error; 487 int bs = 0; 488 int j; 489 490 error = bus_space_init(>_mem_bs_tag, "gtmem", 491 ex_storage[bs], sizeof(ex_storage[bs])); 492 493 error = bus_space_map(gt_memt, 0, 0x10000, 0, >_memh); 494 495 for (j = 0, di = &decode_regs[4]; j < 5; j++, di++) { 496 struct powerpc_bus_space *memt = obio_bs_tags[j]; 497 datal = bus_space_read_4(gt_memt, gt_memh, di->low_decode); 498 datah = bus_space_read_4(gt_memt, gt_memh, di->high_decode); 499 500 if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) { 501 obio_bs_tags[j] = NULL; 502 continue; 503 } 504 memt->pbs_offset = GT_LowAddr_GET(datal); 505 memt->pbs_limit = GT_HighAddr_GET(datah) + 1 - 506 memt->pbs_offset; 507 508 error = bus_space_init(memt, "obio2", 509 ex_storage[bs], sizeof(ex_storage[bs])); 510 bs++; 511 } 512 513 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode); 514 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode); 515 #if defined(GT_PCI0_MEMBASE) 516 datal &= ~0xfff; 517 datal |= (GT_PCI0_MEMBASE >> 20); 518 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode, datal); 519 #endif 520 #if defined(GT_PCI0_MEMSIZE) 521 datah &= ~0xfff; 522 datah |= (GT_PCI0_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 523 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode, datal); 524 #endif 525 gt_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 526 gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 527 528 error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem", 529 ex_storage[bs], sizeof(ex_storage[bs])); 530 bs++; 531 532 /* 533 * Make sure PCI0 Memory is BAT mapped. 534 */ 535 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 536 oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 537 538 /* 539 * Make sure that I/O space start at 0. 540 */ 541 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 542 543 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode); 544 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode); 545 #if defined(GT_PCI0_IOBASE) 546 datal &= ~0xfff; 547 datal |= (GT_PCI0_IOBASE >> 20); 548 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode, datal); 549 #endif 550 #if defined(GT_PCI0_IOSIZE) 551 datah &= ~0xfff; 552 datah |= (GT_PCI0_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 553 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode, datal); 554 #endif 555 gt_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 556 gt_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 557 gt_pci0_io_bs_tag.pbs_offset; 558 559 error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport", 560 ex_storage[bs], sizeof(ex_storage[bs])); 561 bs++; 562 563 #if 0 564 error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent, 565 0x10000, 0x7F0000, EX_NOWAIT); 566 if (error) 567 panic("gt_bus_space_init: can't block out reserved " 568 "I/O space 0x10000-0x7fffff: error=%d\n", error); 569 #endif 570 571 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode); 572 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode); 573 #if defined(GT_PCI1_MEMBASE) 574 datal &= ~0xfff; 575 datal |= (GT_PCI1_MEMBASE >> 20); 576 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode, datal); 577 #endif 578 #if defined(GT_PCI1_MEMSIZE) 579 datah &= ~0xfff; 580 datah |= (GT_PCI1_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 581 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode, datal); 582 #endif 583 gt_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 584 gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 585 586 error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem", 587 ex_storage[bs], sizeof(ex_storage[bs])); 588 bs++; 589 590 /* 591 * Make sure PCI1 Memory is BAT mapped. 592 */ 593 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 594 oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 595 596 /* 597 * Make sure that I/O space start at 0. 598 */ 599 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 600 601 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode); 602 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode); 603 #if defined(GT_PCI1_IOBASE) 604 datal &= ~0xfff; 605 datal |= (GT_PCI1_IOBASE >> 20); 606 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode, datal); 607 #endif 608 #if defined(GT_PCI1_IOSIZE) 609 datah &= ~0xfff; 610 datah |= (GT_PCI1_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 611 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode, datal); 612 #endif 613 gt_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 614 gt_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 615 gt_pci1_io_bs_tag.pbs_offset; 616 617 error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport", 618 ex_storage[bs], sizeof(ex_storage[bs])); 619 bs++; 620 621 #if 0 622 error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent, 623 0x10000, 0x7F0000, EX_NOWAIT); 624 if (error) 625 panic("gt_bus_space_init: can't block out reserved " 626 "I/O space 0x10000-0x7fffff: error=%d\n", error); 627 #endif 628 } 629
Indexes created Sat Oct 25 01:09:55 GMT 2025