machdep.c revision 1.25
1 /* $NetBSD: machdep.c,v 1.25 2009/03/14 21:04:09 dsl Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.25 2009/03/14 21:04:09 dsl Exp $"); 36 37 #include "opt_marvell.h" 38 #include "opt_modular.h" 39 #include "opt_ev64260.h" 40 #include "opt_compat_netbsd.h" 41 #include "opt_ddb.h" 42 #include "opt_inet.h" 43 #include "opt_ccitt.h" 44 #include "opt_iso.h" 45 #include "opt_ns.h" 46 #include "opt_ipkdb.h" 47 48 #include <sys/param.h> 49 #include <sys/conf.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/mount.h> 54 #include <sys/msgbuf.h> 55 #include <sys/proc.h> 56 #include <sys/reboot.h> 57 #include <sys/extent.h> 58 #include <sys/syslog.h> 59 #include <sys/systm.h> 60 #include <sys/termios.h> 61 #include <sys/ksyms.h> 62 63 #include <uvm/uvm.h> 64 #include <uvm/uvm_extern.h> 65 66 #include <net/netisr.h> 67 68 #include <machine/bus.h> 69 #include <machine/db_machdep.h> 70 #include <machine/intr.h> 71 #include <machine/pmap.h> 72 #include <machine/powerpc.h> 73 #include <machine/trap.h> 74 75 #include <powerpc/oea/bat.h> 76 #include <powerpc/marvell/watchdog.h> 77 78 #include <ddb/db_extern.h> 79 80 #include <dev/cons.h> 81 82 #include "vga.h" 83 #if (NVGA > 0) 84 #include <dev/ic/mc6845reg.h> 85 #include <dev/ic/pcdisplayvar.h> 86 #include <dev/ic/vgareg.h> 87 #include <dev/ic/vgavar.h> 88 #endif 89 90 #include "isa.h" 91 #if (NISA > 0) 92 void isa_intr_init(void); 93 #endif 94 95 #include "com.h" 96 #if (NCOM > 0) 97 #include <dev/ic/comreg.h> 98 #include <dev/ic/comvar.h> 99 #endif 100 101 #include <dev/marvell/gtreg.h> 102 #include <dev/marvell/gtvar.h> 103 #include <dev/marvell/gtethreg.h> 104 105 #include "gtmpsc.h" 106 #if (NGTMPSC > 0) 107 #include <dev/marvell/gtsdmareg.h> 108 #include <dev/marvell/gtmpscreg.h> 109 #include <dev/marvell/gtmpscvar.h> 110 #endif 111 112 #include "ksyms.h" 113 114 /* 115 * Global variables used here and there 116 */ 117 extern struct user *proc0paddr; 118 119 #define PMONMEMREGIONS 32 120 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 121 122 char *bootpath; 123 124 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 125 void strayintr(int); 126 int lcsplx(int); 127 void gt_bus_space_init(void); 128 void gt_find_memory(bus_space_tag_t, bus_space_handle_t, paddr_t); 129 void gt_halt(bus_space_tag_t, bus_space_handle_t); 130 void return_to_dink(int); 131 132 void kcomcnputs(dev_t, const char *); 133 134 struct powerpc_bus_space gt_pci0_mem_bs_tag = { 135 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 136 0x00000000, 0x00000000, 0x00000000, 137 }; 138 struct powerpc_bus_space gt_pci0_io_bs_tag = { 139 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 140 0x00000000, 0x00000000, 0x00000000, 141 }; 142 struct powerpc_bus_space gt_pci1_mem_bs_tag = { 143 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 144 0x00000000, 0x00000000, 0x00000000, 145 }; 146 struct powerpc_bus_space gt_pci1_io_bs_tag = { 147 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 148 0x00000000, 0x00000000, 0x00000000, 149 }; 150 struct powerpc_bus_space gt_obio0_bs_tag = { 151 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE, 152 0x00000000, 0x00000000, 0x00000000, 153 }; 154 struct powerpc_bus_space gt_obio1_bs_tag = { 155 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE, 156 0x00000000, 0x00000000, 0x00000000, 157 }; 158 struct powerpc_bus_space gt_obio2_bs_tag = { 159 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE, 160 0x00000000, 0x00000000, 0x00000000, 161 }; 162 struct powerpc_bus_space gt_obio3_bs_tag = { 163 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE, 164 0x00000000, 0x00000000, 0x00000000, 165 }; 166 struct powerpc_bus_space gt_bootcs_bs_tag = { 167 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 168 0x00000000, 0x00000000, 0x00000000, 169 }; 170 struct powerpc_bus_space gt_mem_bs_tag = { 171 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 172 GT_BASE, 0x00000000, 0x00010000, 173 }; 174 175 bus_space_handle_t gt_memh; 176 177 struct powerpc_bus_space *obio_bs_tags[5] = { 178 >_obio0_bs_tag, >_obio1_bs_tag, >_obio2_bs_tag, 179 >_obio3_bs_tag, >_bootcs_bs_tag 180 }; 181 182 static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)] 183 __attribute__((aligned(8))); 184 185 const struct gt_decode_info { 186 bus_addr_t low_decode; 187 bus_addr_t high_decode; 188 } decode_regs[] = { 189 { GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 190 { GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 191 { GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 192 { GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 193 { GT_CS0_Low_Decode, GT_CS0_High_Decode }, 194 { GT_CS1_Low_Decode, GT_CS1_High_Decode }, 195 { GT_CS2_Low_Decode, GT_CS2_High_Decode }, 196 { GT_CS3_Low_Decode, GT_CS3_High_Decode }, 197 { GT_BootCS_Low_Decode, GT_BootCS_High_Decode }, 198 }; 199 200 void 201 initppc(u_int startkernel, u_int endkernel, u_int args, void *btinfo) 202 { 203 oea_batinit(0xf0000000, BAT_BL_256M); 204 oea_init((void (*)(void))ext_intr); 205 206 DELAY(100000); 207 208 gt_bus_space_init(); 209 gt_find_memory(>_mem_bs_tag, gt_memh, roundup(endkernel, PAGE_SIZE)); 210 gt_halt(>_mem_bs_tag, gt_memh); 211 212 /* 213 * Now that we known how much memory, reinit the bats. 214 */ 215 oea_batinit(0xf0000000, BAT_BL_256M); 216 217 consinit(); 218 219 #if (NISA > 0) 220 isa_intr_init(); 221 #endif 222 223 /* 224 * Set the page size. 225 */ 226 uvm_setpagesize(); 227 228 /* 229 * Initialize pmap module. 230 */ 231 pmap_bootstrap(startkernel, endkernel); 232 233 #if NKSYMS || defined(DDB) || defined(MODULAR) 234 { 235 extern void *startsym, *endsym; 236 ksyms_addsyms_elf((int)((u_int)endsym - (u_int)startsym), 237 startsym, endsym); 238 } 239 #endif 240 #ifdef IPKDB 241 /* 242 * Now trap to IPKDB 243 */ 244 ipkdb_init(); 245 if (boothowto & RB_KDB) 246 ipkdb_connect(0); 247 #endif 248 } 249 250 void 251 mem_regions(struct mem_region **mem, struct mem_region **avail) 252 { 253 *mem = physmemr; 254 *avail = availmemr; 255 } 256 257 static inline void 258 gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel) 259 { 260 physmemr[j].start = start; 261 physmemr[j].size = end - start; 262 if (start < endkernel) 263 start = endkernel; 264 availmemr[j].start = start; 265 availmemr[j].size = end - start; 266 } 267 268 void 269 gt_find_memory(bus_space_tag_t memt, bus_space_handle_t memh, 270 paddr_t endkernel) 271 { 272 paddr_t start = ~0, end = 0; 273 int i, j = 0, first = 1; 274 275 /* 276 * Round kernel end to a page boundary. 277 */ 278 for (i = 0; i < 4; i++) { 279 paddr_t nstart, nend; 280 nstart = GT_LowAddr_GET(bus_space_read_4(>_mem_bs_tag, 281 gt_memh, decode_regs[i].low_decode)); 282 nend = GT_HighAddr_GET(bus_space_read_4(>_mem_bs_tag, 283 gt_memh, decode_regs[i].high_decode)) + 1; 284 if (nstart >= nend) 285 continue; 286 if (first) { 287 /* 288 * First entry? Just remember it. 289 */ 290 start = nstart; 291 end = nend; 292 first = 0; 293 } else if (nstart == end) { 294 /* 295 * Contiguous? Just update the end. 296 */ 297 end = nend; 298 } else { 299 /* 300 * Disjoint? record it. 301 */ 302 gt_record_memory(j, start, end, endkernel); 303 start = nstart; 304 end = nend; 305 j++; 306 } 307 } 308 gt_record_memory(j, start, end, endkernel); 309 } 310 311 /* 312 * Machine dependent startup code. 313 */ 314 void 315 cpu_startup(void) 316 { 317 register_t msr; 318 319 oea_startup(NULL); 320 321 /* 322 * Now that we have VM, malloc()s are OK in bus_space. 323 */ 324 bus_space_mallocok(); 325 326 /* 327 * Now allow hardware interrupts. 328 */ 329 splhigh(); 330 __asm volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 331 : "=r"(msr) 332 : "K"(PSL_EE)); 333 } 334 335 /* 336 * consinit 337 * Initialize system console. 338 */ 339 void 340 consinit(void) 341 { 342 #ifdef MPSC_CONSOLE 343 /* PMON using MPSC0 @ 9600 */ 344 gtmpsccnattach(>_mem_bs_tag, gt_memh, MPSC_CONSOLE, 9600, 345 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 346 #else 347 /* PPCBOOT using COM1 @ 57600 */ 348 comcnattach(>_obio2_bs_tag, 0, 57600, 349 COM_FREQ*2, COM_TYPE_NORMAL, 350 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 351 #endif 352 } 353 354 /* 355 * Stray interrupts. 356 */ 357 void 358 strayintr(int irq) 359 { 360 log(LOG_ERR, "stray interrupt %d\n", irq); 361 } 362 363 /* 364 * Halt or reboot the machine after syncing/dumping according to howto. 365 */ 366 void 367 cpu_reboot(int howto, char *what) 368 { 369 static int syncing; 370 static char str[256]; 371 char *ap = str, *ap1 = ap; 372 373 boothowto = howto; 374 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 375 syncing = 1; 376 vfs_shutdown(); /* sync */ 377 resettodr(); /* set wall clock */ 378 } 379 splhigh(); 380 if (howto & RB_HALT) { 381 doshutdownhooks(); 382 pmf_system_shutdown(boothowto); 383 printf("halted\n\n"); 384 cnhalt(); 385 while(1); 386 } 387 if (!cold && (howto & RB_DUMP)) 388 oea_dumpsys(); 389 doshutdownhooks(); 390 391 pmf_system_shutdown(boothowto); 392 printf("rebooting\n\n"); 393 if (what && *what) { 394 if (strlen(what) > sizeof str - 5) 395 printf("boot string too large, ignored\n"); 396 else { 397 strcpy(str, what); 398 ap1 = ap = str + strlen(str); 399 *ap++ = ' '; 400 } 401 } 402 *ap++ = '-'; 403 if (howto & RB_SINGLE) 404 *ap++ = 's'; 405 if (howto & RB_KDB) 406 *ap++ = 'd'; 407 *ap++ = 0; 408 if (ap[-2] == '-') 409 *ap1 = 0; 410 #if 0 411 { 412 void mvpppc_reboot(void); 413 mvpppc_reboot(); 414 } 415 #endif 416 gt_watchdog_reset(); 417 /* NOTREACHED */ 418 while (1); 419 } 420 421 int 422 lcsplx(int ipl) 423 { 424 return spllower(ipl); 425 } 426 427 void 428 gt_halt(bus_space_tag_t memt, bus_space_handle_t memh) 429 { 430 int i; 431 u_int32_t data; 432 433 /* 434 * Shut down the MPSC ports 435 */ 436 for (i = 0; i < 2; i++) { 437 bus_space_write_4(memt, memh, 438 SDMA_U_SDCM(i), SDMA_SDCM_AR|SDMA_SDCM_AT); 439 for (;;) { 440 data = bus_space_read_4(memt, memh, 441 SDMA_U_SDCM(i)); 442 if (((SDMA_SDCM_AR|SDMA_SDCM_AT) & data) == 0) 443 break; 444 } 445 } 446 447 /* 448 * Shut down the Ethernets 449 */ 450 for (i = 0; i < 3; i++) { 451 bus_space_write_4(memt, memh, 452 ETH_ESDCMR(2), ETH_ESDCMR_AR|ETH_ESDCMR_AT); 453 for (;;) { 454 data = bus_space_read_4(memt, memh, 455 ETH_ESDCMR(i)); 456 if (((ETH_ESDCMR_AR|ETH_ESDCMR_AT) & data) == 0) 457 break; 458 } 459 data = bus_space_read_4(memt, memh, ETH_EPCR(i)); 460 data &= ~ETH_EPCR_EN; 461 bus_space_write_4(memt, memh, ETH_EPCR(i), data); 462 } 463 } 464 465 int 466 gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr) 467 { 468 enaddr[0] = 0x02; 469 enaddr[1] = 0x00; 470 enaddr[2] = 0x04; 471 enaddr[3] = 0x00; 472 enaddr[4] = 0x00; 473 enaddr[5] = 0x04 + macno; 474 475 return 0; 476 } 477 478 void 479 gt_bus_space_init(void) 480 { 481 bus_space_tag_t gt_memt = >_mem_bs_tag; 482 const struct gt_decode_info *di; 483 uint32_t datal, datah; 484 int error; 485 int bs = 0; 486 int j; 487 488 error = bus_space_init(>_mem_bs_tag, "gtmem", 489 ex_storage[bs], sizeof(ex_storage[bs])); 490 491 error = bus_space_map(gt_memt, 0, 0x10000, 0, >_memh); 492 493 for (j = 0, di = &decode_regs[4]; j < 5; j++, di++) { 494 struct powerpc_bus_space *memt = obio_bs_tags[j]; 495 datal = bus_space_read_4(gt_memt, gt_memh, di->low_decode); 496 datah = bus_space_read_4(gt_memt, gt_memh, di->high_decode); 497 498 if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) { 499 obio_bs_tags[j] = NULL; 500 continue; 501 } 502 memt->pbs_offset = GT_LowAddr_GET(datal); 503 memt->pbs_limit = GT_HighAddr_GET(datah) + 1 - 504 memt->pbs_offset; 505 506 error = bus_space_init(memt, "obio2", 507 ex_storage[bs], sizeof(ex_storage[bs])); 508 bs++; 509 } 510 511 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode); 512 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode); 513 #if defined(GT_PCI0_MEMBASE) 514 datal &= ~0xfff; 515 datal |= (GT_PCI0_MEMBASE >> 20); 516 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode, datal); 517 #endif 518 #if defined(GT_PCI0_MEMSIZE) 519 datah &= ~0xfff; 520 datah |= (GT_PCI0_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 521 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode, datal); 522 #endif 523 gt_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 524 gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 525 526 error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem", 527 ex_storage[bs], sizeof(ex_storage[bs])); 528 bs++; 529 530 /* 531 * Make sure PCI0 Memory is BAT mapped. 532 */ 533 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 534 oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 535 536 /* 537 * Make sure that I/O space start at 0. 538 */ 539 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 540 541 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode); 542 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode); 543 #if defined(GT_PCI0_IOBASE) 544 datal &= ~0xfff; 545 datal |= (GT_PCI0_IOBASE >> 20); 546 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode, datal); 547 #endif 548 #if defined(GT_PCI0_IOSIZE) 549 datah &= ~0xfff; 550 datah |= (GT_PCI0_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 551 bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode, datal); 552 #endif 553 gt_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 554 gt_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 555 gt_pci0_io_bs_tag.pbs_offset; 556 557 error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport", 558 ex_storage[bs], sizeof(ex_storage[bs])); 559 bs++; 560 561 #if 0 562 error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent, 563 0x10000, 0x7F0000, EX_NOWAIT); 564 if (error) 565 panic("gt_bus_space_init: can't block out reserved " 566 "I/O space 0x10000-0x7fffff: error=%d\n", error); 567 #endif 568 569 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode); 570 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode); 571 #if defined(GT_PCI1_MEMBASE) 572 datal &= ~0xfff; 573 datal |= (GT_PCI1_MEMBASE >> 20); 574 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode, datal); 575 #endif 576 #if defined(GT_PCI1_MEMSIZE) 577 datah &= ~0xfff; 578 datah |= (GT_PCI1_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 579 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode, datal); 580 #endif 581 gt_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 582 gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 583 584 error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem", 585 ex_storage[bs], sizeof(ex_storage[bs])); 586 bs++; 587 588 /* 589 * Make sure PCI1 Memory is BAT mapped. 590 */ 591 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 592 oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 593 594 /* 595 * Make sure that I/O space start at 0. 596 */ 597 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 598 599 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode); 600 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode); 601 #if defined(GT_PCI1_IOBASE) 602 datal &= ~0xfff; 603 datal |= (GT_PCI1_IOBASE >> 20); 604 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode, datal); 605 #endif 606 #if defined(GT_PCI1_IOSIZE) 607 datah &= ~0xfff; 608 datah |= (GT_PCI1_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 609 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode, datal); 610 #endif 611 gt_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 612 gt_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 613 gt_pci1_io_bs_tag.pbs_offset; 614 615 error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport", 616 ex_storage[bs], sizeof(ex_storage[bs])); 617 bs++; 618 619 #if 0 620 error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent, 621 0x10000, 0x7F0000, EX_NOWAIT); 622 if (error) 623 panic("gt_bus_space_init: can't block out reserved " 624 "I/O space 0x10000-0x7fffff: error=%d\n", error); 625 #endif 626 } 627
Indexes created Thu Oct 02 07:10:07 GMT 2025