machdep.c revision 1.27
1 /* $NetBSD: machdep.c,v 1.27 2010/04/28 13:51:55 kiyohara Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.27 2010/04/28 13:51:55 kiyohara Exp $"); 36 37 #include "opt_marvell.h" 38 #include "opt_modular.h" 39 #include "opt_ev64260.h" 40 #include "opt_compat_netbsd.h" 41 #include "opt_ddb.h" 42 #include "opt_inet.h" 43 #include "opt_ccitt.h" 44 #include "opt_iso.h" 45 #include "opt_ns.h" 46 #include "opt_ipkdb.h" 47 48 #define _POWERPC_BUS_DMA_PRIVATE 49 50 #include <sys/param.h> 51 #include <sys/bus.h> 52 #include <sys/conf.h> 53 #include <sys/device.h> 54 #include <sys/extent.h> 55 #include <sys/kernel.h> 56 #include <sys/ksyms.h> 57 #include <sys/mount.h> 58 #include <sys/reboot.h> 59 #include <sys/systm.h> 60 #include <sys/termios.h> 61 #include <sys/vnode.h> 62 63 #include <uvm/uvm.h> 64 #include <uvm/uvm_extern.h> 65 66 #include <net/netisr.h> 67 68 #include <machine/db_machdep.h> 69 #include <machine/pmap.h> 70 #include <machine/powerpc.h> 71 72 #include <powerpc/oea/bat.h> 73 #include <powerpc/pic/picvar.h> 74 #include <powerpc/pio.h> 75 76 #include <ddb/db_extern.h> 77 78 #include <dev/cons.h> 79 80 #include "com.h" 81 #if (NCOM > 0) 82 #include <dev/ic/comreg.h> 83 #include <dev/ic/comvar.h> 84 #endif 85 86 #include <dev/marvell/gtreg.h> 87 #include <dev/marvell/gtvar.h> 88 89 #include "gtmpsc.h" 90 #if (NGTMPSC > 0) 91 #include <dev/marvell/gtbrgreg.h> 92 #include <dev/marvell/gtsdmareg.h> 93 #include <dev/marvell/gtmpscreg.h> 94 #include <dev/marvell/gtmpscvar.h> 95 #endif 96 97 #include "ksyms.h" 98 #include "locators.h" 99 100 101 /* 102 * Global variables used here and there 103 */ 104 #define PMONMEMREGIONS 32 105 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 106 107 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 108 static void gt_bus_space_init(void); 109 static inline void gt_record_memory(int, paddr_t, paddr_t, paddr_t); 110 static void gt_find_memory(paddr_t); 111 112 bus_addr_t gt_base = 0; 113 114 extern int primary_pic; 115 struct pic_ops *discovery_pic; 116 struct pic_ops *discovery_gpp_pic[4]; 117 118 119 struct powerpc_bus_space ev64260_pci0_mem_bs_tag = { 120 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 121 0x00000000, 0x00000000, 0x00000000, 122 }; 123 struct powerpc_bus_space ev64260_pci0_io_bs_tag = { 124 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 125 0x00000000, 0x00000000, 0x00000000, 126 }; 127 struct powerpc_bus_space ev64260_pci1_mem_bs_tag = { 128 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 129 0x00000000, 0x00000000, 0x00000000, 130 }; 131 struct powerpc_bus_space ev64260_pci1_io_bs_tag = { 132 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 133 0x00000000, 0x00000000, 0x00000000, 134 }; 135 struct powerpc_bus_space ev64260_obio0_bs_tag = { 136 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE, 137 0x00000000, 0x00000000, 0x00000000, 138 }; 139 struct powerpc_bus_space ev64260_obio1_bs_tag = { 140 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE, 141 0x00000000, 0x00000000, 0x00000000, 142 }; 143 struct powerpc_bus_space ev64260_obio2_bs_tag = { 144 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE, 145 0x00000000, 0x00000000, 0x00000000, 146 }; 147 struct powerpc_bus_space ev64260_obio3_bs_tag = { 148 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE, 149 0x00000000, 0x00000000, 0x00000000, 150 }; 151 struct powerpc_bus_space ev64260_bootcs_bs_tag = { 152 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 153 0x00000000, 0x00000000, 0x00000000, 154 }; 155 struct powerpc_bus_space ev64260_gt_bs_tag = { 156 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 157 0x00000000, 0x00000000, GT_SIZE, 158 }; 159 160 struct powerpc_bus_space *ev64260_obio_bs_tags[5] = { 161 &ev64260_obio0_bs_tag, &ev64260_obio1_bs_tag, &ev64260_obio2_bs_tag, 162 &ev64260_obio3_bs_tag, &ev64260_bootcs_bs_tag 163 }; 164 165 static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)] 166 __attribute__((aligned(8))); 167 168 const struct gt_decode_info { 169 bus_addr_t low_decode; 170 bus_addr_t high_decode; 171 } decode_regs[] = { 172 { GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 173 { GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 174 { GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 175 { GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 176 { GT_CS0_Low_Decode, GT_CS0_High_Decode }, 177 { GT_CS1_Low_Decode, GT_CS1_High_Decode }, 178 { GT_CS2_Low_Decode, GT_CS2_High_Decode }, 179 { GT_CS3_Low_Decode, GT_CS3_High_Decode }, 180 { GT_BootCS_Low_Decode, GT_BootCS_High_Decode }, 181 }; 182 183 struct powerpc_bus_dma_tag ev64260_bus_dma_tag = { 184 0, /* _bounce_thresh */ 185 _bus_dmamap_create, 186 _bus_dmamap_destroy, 187 _bus_dmamap_load, 188 _bus_dmamap_load_mbuf, 189 _bus_dmamap_load_uio, 190 _bus_dmamap_load_raw, 191 _bus_dmamap_unload, 192 _bus_dmamap_sync, 193 _bus_dmamem_alloc, 194 _bus_dmamem_free, 195 _bus_dmamem_map, 196 _bus_dmamem_unmap, 197 _bus_dmamem_mmap, 198 }; 199 200 201 void 202 initppc(u_int startkernel, u_int endkernel, u_int args, void *btinfo) 203 { 204 extern struct cfdata cfdata[]; 205 cfdata_t cf = &cfdata[0]; 206 207 /* Get mapped address of gt(System Controller) */ 208 while (cf->cf_name != NULL) { 209 if (strcmp(cf->cf_name, "gt") == 0 && 210 *cf->cf_loc != MAINBUSCF_ADDR_DEFAULT) 211 break; 212 cf++; 213 } 214 if (cf->cf_name == NULL) 215 panic("where is gt?"); 216 gt_base = *cf->cf_loc; 217 218 ev64260_gt_bs_tag.pbs_offset = gt_base; 219 ev64260_gt_bs_tag.pbs_base = gt_base; 220 ev64260_gt_bs_tag.pbs_limit += gt_base; 221 oea_batinit(gt_base, BAT_BL_256M); 222 223 oea_init(NULL); 224 225 gt_bus_space_init(); 226 gt_find_memory(roundup(endkernel, PAGE_SIZE)); 227 228 consinit(); 229 230 /* 231 * Set the page size. 232 */ 233 uvm_setpagesize(); 234 235 /* 236 * Initialize pmap module. 237 */ 238 pmap_bootstrap(startkernel, endkernel); 239 240 #if NKSYMS || defined(DDB) || defined(MODULAR) 241 { 242 extern void *startsym, *endsym; 243 ksyms_addsyms_elf((int)((u_int)endsym - (u_int)startsym), 244 startsym, endsym); 245 } 246 #endif 247 #ifdef IPKDB 248 /* 249 * Now trap to IPKDB 250 */ 251 ipkdb_init(); 252 if (boothowto & RB_KDB) 253 ipkdb_connect(0); 254 #endif 255 } 256 257 /* 258 * Machine dependent startup code. 259 */ 260 void 261 cpu_startup(void) 262 { 263 register_t msr; 264 265 oea_startup(NULL); 266 267 pic_init(); 268 discovery_pic = setup_discovery_pic(); 269 primary_pic = 0; 270 discovery_gpp_pic[0] = setup_discovery_gpp_pic(discovery_pic, 0); 271 discovery_gpp_pic[1] = setup_discovery_gpp_pic(discovery_pic, 8); 272 discovery_gpp_pic[2] = setup_discovery_gpp_pic(discovery_pic, 16); 273 discovery_gpp_pic[3] = setup_discovery_gpp_pic(discovery_pic, 24); 274 /* 275 * GPP interrupts establishes later. 276 */ 277 278 oea_install_extint(pic_ext_intr); 279 280 /* 281 * Now that we have VM, malloc()s are OK in bus_space. 282 */ 283 bus_space_mallocok(); 284 285 /* 286 * Now allow hardware interrupts. 287 */ 288 splraise(-1); 289 __asm volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 290 : "=r"(msr) 291 : "K"(PSL_EE)); 292 } 293 294 /* 295 * consinit 296 * Initialize system console. 297 */ 298 void 299 consinit(void) 300 { 301 302 #ifdef MPSC_CONSOLE 303 /* PMON using MPSC0 @ 9600 */ 304 const int brg = GTMPSC_CRR_BRG0; 305 const int baud = 9600; 306 uint32_t cr; 307 308 #if 1 309 /* 310 * XXX HACK FIXME 311 * PMON output has not been flushed. give him a chance 312 */ 313 DELAY(100000); /* XXX */ 314 #endif 315 /* Setup MPSC Routing Registers */ 316 out32rb(gt_base + GTMPSC_MRR, GTMPSC_MRR_RES); 317 cr = in32rb(gt_base + GTMPSC_RCRR); 318 cr &= ~GTMPSC_CRR(MPSC_CONSOLE, GTMPSC_CRR_MASK); 319 cr |= GTMPSC_CRR(MPSC_CONSOLE, brg); 320 out32rb(gt_base + GTMPSC_RCRR, cr); 321 out32rb(gt_base + GTMPSC_TCRR, cr); 322 323 /* Setup Baud Rate Configuration Register of Baud Rate Generator */ 324 out32rb(gt_base + BRG_BCR(brg), 325 BRG_BCR_EN | GT_MPSC_CLOCK_SOURCE | compute_cdv(baud)); 326 327 gtmpsccnattach(&ev64260_gt_bs_tag, &ev64260_bus_dma_tag, gt_base, 328 MPSC_CONSOLE, brg, baud, 329 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 330 #else 331 /* PPCBOOT using COM1 @ 57600 */ 332 comcnattach(>_obio2_bs_tag, 0, 57600, 333 COM_FREQ*2, COM_TYPE_NORMAL, 334 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 335 #endif 336 } 337 338 /* 339 * Halt or reboot the machine after syncing/dumping according to howto. 340 */ 341 void 342 cpu_reboot(int howto, char *what) 343 { 344 static int syncing; 345 static char str[256]; 346 char *ap = str, *ap1 = ap; 347 348 boothowto = howto; 349 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 350 syncing = 1; 351 vfs_shutdown(); /* sync */ 352 resettodr(); /* set wall clock */ 353 } 354 splhigh(); 355 if (howto & RB_HALT) { 356 doshutdownhooks(); 357 pmf_system_shutdown(boothowto); 358 printf("halted\n\n"); 359 cnhalt(); 360 while(1); 361 } 362 if (!cold && (howto & RB_DUMP)) 363 oea_dumpsys(); 364 doshutdownhooks(); 365 366 pmf_system_shutdown(boothowto); 367 printf("rebooting\n\n"); 368 if (what && *what) { 369 if (strlen(what) > sizeof str - 5) 370 printf("boot string too large, ignored\n"); 371 else { 372 strcpy(str, what); 373 ap1 = ap = str + strlen(str); 374 *ap++ = ' '; 375 } 376 } 377 *ap++ = '-'; 378 if (howto & RB_SINGLE) 379 *ap++ = 's'; 380 if (howto & RB_KDB) 381 *ap++ = 'd'; 382 *ap++ = 0; 383 if (ap[-2] == '-') 384 *ap1 = 0; 385 gt_watchdog_reset(); 386 /* NOTREACHED */ 387 while (1); 388 } 389 390 void 391 mem_regions(struct mem_region **mem, struct mem_region **avail) 392 { 393 394 *mem = physmemr; 395 *avail = availmemr; 396 } 397 398 static void 399 gt_bus_space_init(void) 400 { 401 const struct gt_decode_info *di; 402 uint32_t datal, datah; 403 int error, bs, i; 404 405 bs = 0; 406 error = bus_space_init(&ev64260_gt_bs_tag, "gt", 407 ex_storage[bs], sizeof(ex_storage[bs])); 408 bs++; 409 410 for (i = 0, di = &decode_regs[4]; i < 5; i++, di++) { 411 struct powerpc_bus_space *memt = ev64260_obio_bs_tags[i]; 412 413 datal = in32rb(gt_base + di->low_decode); 414 datah = in32rb(gt_base + di->high_decode); 415 416 if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) { 417 ev64260_obio_bs_tags[i] = NULL; 418 continue; 419 } 420 memt->pbs_offset = GT_LowAddr_GET(datal); 421 memt->pbs_limit = GT_HighAddr_GET(datah) + 1 - 422 memt->pbs_offset; 423 424 error = bus_space_init(memt, "obio2", 425 ex_storage[bs], sizeof(ex_storage[bs])); 426 bs++; 427 } 428 429 datal = in32rb(gt_base + GT_PCI0_Mem0_Low_Decode); 430 datah = in32rb(gt_base + GT_PCI0_Mem0_High_Decode); 431 #if defined(GT_PCI0_MEMBASE) 432 datal &= ~0xfff; 433 datal |= (GT_PCI0_MEMBASE >> 20); 434 out32rb(gt_base + GT_PCI0_Mem0_Low_Decode, datal); 435 #endif 436 #if defined(GT_PCI0_MEMSIZE) 437 datah &= ~0xfff; 438 datah |= (GT_PCI0_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 439 out32rb(gt_base + GT_PCI0_Mem0_High_Decode, datal); 440 #endif 441 ev64260_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 442 ev64260_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 443 444 error = bus_space_init(&ev64260_pci0_mem_bs_tag, "pci0-mem", 445 ex_storage[bs], sizeof(ex_storage[bs])); 446 bs++; 447 448 #if 1 /* XXXXXX */ 449 /* 450 * Make sure PCI0 Memory is BAT mapped. 451 */ 452 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 453 oea_iobat_add(ev64260_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, 454 BAT_BL_256M); 455 #endif 456 457 /* 458 * Make sure that I/O space start at 0. 459 */ 460 out32rb(gt_base + GT_PCI1_IO_Remap, 0); 461 462 datal = in32rb(gt_base + GT_PCI0_IO_Low_Decode); 463 datah = in32rb(gt_base + GT_PCI0_IO_High_Decode); 464 #if defined(GT_PCI0_IOBASE) 465 datal &= ~0xfff; 466 datal |= (GT_PCI0_IOBASE >> 20); 467 out32rb(gt_base + GT_PCI0_IO_Low_Decode, datal); 468 #endif 469 #if defined(GT_PCI0_IOSIZE) 470 datah &= ~0xfff; 471 datah |= (GT_PCI0_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 472 out32rb(gt_base + GT_PCI0_IO_High_Decode, datal); 473 #endif 474 ev64260_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 475 ev64260_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 476 ev64260_pci0_io_bs_tag.pbs_offset; 477 478 error = bus_space_init(&ev64260_pci0_io_bs_tag, "pci0-ioport", 479 ex_storage[bs], sizeof(ex_storage[bs])); 480 bs++; 481 482 datal = in32rb(gt_base + GT_PCI1_Mem0_Low_Decode); 483 datah = in32rb(gt_base + GT_PCI1_Mem0_High_Decode); 484 #if defined(GT_PCI1_MEMBASE) 485 datal &= ~0xfff; 486 datal |= (GT_PCI1_MEMBASE >> 20); 487 out32rb(gt_base + GT_PCI1_Mem0_Low_Decode, datal); 488 #endif 489 #if defined(GT_PCI1_MEMSIZE) 490 datah &= ~0xfff; 491 datah |= (GT_PCI1_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 492 out32rb(gt_base + GT_PCI1_Mem0_High_Decode, datal); 493 #endif 494 ev64260_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 495 ev64260_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 496 497 error = bus_space_init(&ev64260_pci1_mem_bs_tag, "pci1-mem", 498 ex_storage[bs], sizeof(ex_storage[bs])); 499 bs++; 500 501 #if 1 /* XXXXXX */ 502 /* 503 * Make sure PCI1 Memory is BAT mapped. 504 */ 505 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 506 oea_iobat_add(ev64260_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, 507 BAT_BL_256M); 508 #endif 509 510 /* 511 * Make sure that I/O space start at 0. 512 */ 513 out32rb(gt_base + GT_PCI1_IO_Remap, 0); 514 515 datal = in32rb(gt_base + GT_PCI1_IO_Low_Decode); 516 datah = in32rb(gt_base + GT_PCI1_IO_High_Decode); 517 #if defined(GT_PCI1_IOBASE) 518 datal &= ~0xfff; 519 datal |= (GT_PCI1_IOBASE >> 20); 520 out32rb(gt_base + GT_PCI1_IO_Low_Decode, datal); 521 #endif 522 #if defined(GT_PCI1_IOSIZE) 523 datah &= ~0xfff; 524 datah |= (GT_PCI1_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 525 out32rb(gt_base + GT_PCI1_IO_High_Decode, datal); 526 #endif 527 ev64260_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 528 ev64260_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 529 ev64260_pci1_io_bs_tag.pbs_offset; 530 531 error = bus_space_init(&ev64260_pci1_io_bs_tag, "pci1-ioport", 532 ex_storage[bs], sizeof(ex_storage[bs])); 533 bs++; 534 } 535 536 static inline void 537 gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel) 538 { 539 physmemr[j].start = start; 540 physmemr[j].size = end - start; 541 if (start < endkernel) 542 start = endkernel; 543 availmemr[j].start = start; 544 availmemr[j].size = end - start; 545 } 546 547 static void 548 gt_find_memory(paddr_t endkernel) 549 { 550 paddr_t start = ~0, end = 0; 551 const struct gt_decode_info *di; 552 int i, j = 0, first = 1; 553 554 /* 555 * Round kernel end to a page boundary. 556 */ 557 for (i = 0; i < 4; i++) { 558 paddr_t nstart, nend; 559 560 di = &decode_regs[i]; 561 nstart = GT_LowAddr_GET(in32rb(gt_base + di->low_decode)); 562 nend = GT_HighAddr_GET(in32rb(gt_base + di->high_decode)) + 1; 563 if (nstart >= nend) 564 continue; 565 if (first) { 566 /* 567 * First entry? Just remember it. 568 */ 569 start = nstart; 570 end = nend; 571 first = 0; 572 } else if (nstart == end) { 573 /* 574 * Contiguous? Just update the end. 575 */ 576 end = nend; 577 } else { 578 /* 579 * Disjoint? record it. 580 */ 581 gt_record_memory(j, start, end, endkernel); 582 start = nstart; 583 end = nend; 584 j++; 585 } 586 } 587 gt_record_memory(j, start, end, endkernel); 588 } 589
Indexes created Wed Oct 01 07:09:59 GMT 2025