machdep.c revision 1.32.14.1
1 /* $NetBSD: machdep.c,v 1.32.14.1 2018/07/28 04:37:33 pgoyette Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.32.14.1 2018/07/28 04:37:33 pgoyette Exp $"); 36 37 #include "opt_marvell.h" 38 #include "opt_modular.h" 39 #include "opt_ev64260.h" 40 #include "opt_compat_netbsd.h" 41 #include "opt_ddb.h" 42 #include "opt_inet.h" 43 #include "opt_ccitt.h" 44 #include "opt_ns.h" 45 46 #define _POWERPC_BUS_DMA_PRIVATE 47 48 #include <sys/param.h> 49 #include <sys/bus.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/extent.h> 53 #include <sys/kernel.h> 54 #include <sys/ksyms.h> 55 #include <sys/mount.h> 56 #include <sys/reboot.h> 57 #include <sys/systm.h> 58 #include <sys/termios.h> 59 #include <sys/vnode.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <machine/powerpc.h> 64 65 #include <powerpc/db_machdep.h> 66 #include <powerpc/pmap.h> 67 68 #include <powerpc/oea/bat.h> 69 #include <powerpc/pic/picvar.h> 70 #include <powerpc/pio.h> 71 72 #include <ddb/db_extern.h> 73 74 #include <dev/cons.h> 75 76 #include "com.h" 77 #if (NCOM > 0) 78 #include <dev/ic/comreg.h> 79 #include <dev/ic/comvar.h> 80 #endif 81 82 #include <dev/marvell/gtreg.h> 83 #include <dev/marvell/gtvar.h> 84 85 #include "gtmpsc.h" 86 #if (NGTMPSC > 0) 87 #include <dev/marvell/gtbrgreg.h> 88 #include <dev/marvell/gtsdmareg.h> 89 #include <dev/marvell/gtmpscreg.h> 90 #include <dev/marvell/gtmpscvar.h> 91 #endif 92 93 #include "ksyms.h" 94 #include "locators.h" 95 96 97 /* 98 * Global variables used here and there 99 */ 100 #define PMONMEMREGIONS 32 101 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 102 103 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 104 static void gt_bus_space_init(void); 105 static inline void gt_record_memory(int, paddr_t, paddr_t, paddr_t); 106 static void gt_find_memory(paddr_t); 107 108 bus_addr_t gt_base = 0; 109 110 extern int primary_pic; 111 struct pic_ops *discovery_pic; 112 struct pic_ops *discovery_gpp_pic[4]; 113 114 115 struct powerpc_bus_space ev64260_pci0_mem_bs_tag = { 116 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 117 0x00000000, 0x00000000, 0x00000000, 118 }; 119 struct powerpc_bus_space ev64260_pci0_io_bs_tag = { 120 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 121 0x00000000, 0x00000000, 0x00000000, 122 }; 123 struct powerpc_bus_space ev64260_pci1_mem_bs_tag = { 124 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 125 0x00000000, 0x00000000, 0x00000000, 126 }; 127 struct powerpc_bus_space ev64260_pci1_io_bs_tag = { 128 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 129 0x00000000, 0x00000000, 0x00000000, 130 }; 131 struct powerpc_bus_space ev64260_obio0_bs_tag = { 132 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE, 133 0x00000000, 0x00000000, 0x00000000, 134 }; 135 struct powerpc_bus_space ev64260_obio1_bs_tag = { 136 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE, 137 0x00000000, 0x00000000, 0x00000000, 138 }; 139 struct powerpc_bus_space ev64260_obio2_bs_tag = { 140 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE, 141 0x00000000, 0x00000000, 0x00000000, 142 }; 143 struct powerpc_bus_space ev64260_obio3_bs_tag = { 144 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE, 145 0x00000000, 0x00000000, 0x00000000, 146 }; 147 struct powerpc_bus_space ev64260_bootcs_bs_tag = { 148 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 149 0x00000000, 0x00000000, 0x00000000, 150 }; 151 struct powerpc_bus_space ev64260_gt_bs_tag = { 152 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 153 0x00000000, 0x00000000, GT_SIZE, 154 }; 155 156 struct powerpc_bus_space *ev64260_obio_bs_tags[5] = { 157 &ev64260_obio0_bs_tag, &ev64260_obio1_bs_tag, &ev64260_obio2_bs_tag, 158 &ev64260_obio3_bs_tag, &ev64260_bootcs_bs_tag 159 }; 160 161 static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)] 162 __attribute__((aligned(8))); 163 164 const struct gt_decode_info { 165 bus_addr_t low_decode; 166 bus_addr_t high_decode; 167 } decode_regs[] = { 168 { GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 169 { GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 170 { GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 171 { GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 172 { GT_CS0_Low_Decode, GT_CS0_High_Decode }, 173 { GT_CS1_Low_Decode, GT_CS1_High_Decode }, 174 { GT_CS2_Low_Decode, GT_CS2_High_Decode }, 175 { GT_CS3_Low_Decode, GT_CS3_High_Decode }, 176 { GT_BootCS_Low_Decode, GT_BootCS_High_Decode }, 177 }; 178 179 struct powerpc_bus_dma_tag ev64260_bus_dma_tag = { 180 0, /* _bounce_thresh */ 181 _bus_dmamap_create, 182 _bus_dmamap_destroy, 183 _bus_dmamap_load, 184 _bus_dmamap_load_mbuf, 185 _bus_dmamap_load_uio, 186 _bus_dmamap_load_raw, 187 _bus_dmamap_unload, 188 _bus_dmamap_sync, 189 _bus_dmamem_alloc, 190 _bus_dmamem_free, 191 _bus_dmamem_map, 192 _bus_dmamem_unmap, 193 _bus_dmamem_mmap, 194 }; 195 196 197 void 198 initppc(u_int startkernel, u_int endkernel, u_int args, void *btinfo) 199 { 200 extern struct cfdata cfdata[]; 201 cfdata_t cf = &cfdata[0]; 202 203 /* Get mapped address of gt(System Controller) */ 204 while (cf->cf_name != NULL) { 205 if (strcmp(cf->cf_name, "gt") == 0 && 206 *cf->cf_loc != MAINBUSCF_ADDR_DEFAULT) 207 break; 208 cf++; 209 } 210 if (cf->cf_name == NULL) 211 panic("where is gt?"); 212 gt_base = *cf->cf_loc; 213 214 ev64260_gt_bs_tag.pbs_offset = gt_base; 215 ev64260_gt_bs_tag.pbs_base = gt_base; 216 ev64260_gt_bs_tag.pbs_limit += gt_base; 217 oea_batinit(gt_base, BAT_BL_256M); 218 219 oea_init(NULL); 220 221 gt_bus_space_init(); 222 gt_find_memory(roundup(endkernel, PAGE_SIZE)); 223 224 consinit(); 225 226 uvm_md_init(); 227 228 /* 229 * Initialize pmap module. 230 */ 231 pmap_bootstrap(startkernel, endkernel); 232 233 #if NKSYMS || defined(DDB) || defined(MODULAR) 234 { 235 extern void *startsym, *endsym; 236 ksyms_addsyms_elf((int)((u_int)endsym - (u_int)startsym), 237 startsym, endsym); 238 } 239 #endif 240 } 241 242 /* 243 * Machine dependent startup code. 244 */ 245 void 246 cpu_startup(void) 247 { 248 register_t msr; 249 250 oea_startup(NULL); 251 252 pic_init(); 253 discovery_pic = setup_discovery_pic(); 254 primary_pic = 0; 255 discovery_gpp_pic[0] = setup_discovery_gpp_pic(discovery_pic, 0); 256 discovery_gpp_pic[1] = setup_discovery_gpp_pic(discovery_pic, 8); 257 discovery_gpp_pic[2] = setup_discovery_gpp_pic(discovery_pic, 16); 258 discovery_gpp_pic[3] = setup_discovery_gpp_pic(discovery_pic, 24); 259 /* 260 * GPP interrupts establishes later. 261 */ 262 263 oea_install_extint(pic_ext_intr); 264 265 /* 266 * Now that we have VM, malloc()s are OK in bus_space. 267 */ 268 bus_space_mallocok(); 269 270 /* 271 * Now allow hardware interrupts. 272 */ 273 splraise(-1); 274 __asm volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 275 : "=r"(msr) 276 : "K"(PSL_EE)); 277 } 278 279 /* 280 * consinit 281 * Initialize system console. 282 */ 283 void 284 consinit(void) 285 { 286 287 #ifdef MPSC_CONSOLE 288 /* PMON using MPSC0 @ 9600 */ 289 const int brg = GTMPSC_CRR_BRG0; 290 const int baud = 9600; 291 uint32_t cr; 292 293 #if 1 294 /* 295 * XXX HACK FIXME 296 * PMON output has not been flushed. give him a chance 297 */ 298 DELAY(100000); /* XXX */ 299 #endif 300 /* Setup MPSC Routing Registers */ 301 out32rb(gt_base + GTMPSC_MRR, GTMPSC_MRR_RES); 302 cr = in32rb(gt_base + GTMPSC_RCRR); 303 cr &= ~GTMPSC_CRR(MPSC_CONSOLE, GTMPSC_CRR_MASK); 304 cr |= GTMPSC_CRR(MPSC_CONSOLE, brg); 305 out32rb(gt_base + GTMPSC_RCRR, cr); 306 out32rb(gt_base + GTMPSC_TCRR, cr); 307 308 /* Setup Baud Rate Configuration Register of Baud Rate Generator */ 309 out32rb(gt_base + BRG_BCR(brg), 310 BRG_BCR_EN | GT_MPSC_CLOCK_SOURCE | compute_cdv(baud)); 311 312 gtmpsccnattach(&ev64260_gt_bs_tag, &ev64260_bus_dma_tag, gt_base, 313 MPSC_CONSOLE, brg, baud, 314 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 315 #else 316 /* PPCBOOT using COM1 @ 57600 */ 317 comcnattach(>_obio2_bs_tag, 0, 57600, 318 COM_FREQ*2, COM_TYPE_NORMAL, 319 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 320 #endif 321 } 322 323 /* 324 * Halt or reboot the machine after syncing/dumping according to howto. 325 */ 326 void 327 cpu_reboot(int howto, char *what) 328 { 329 static int syncing; 330 static char str[256]; 331 char *ap = str, *ap1 = ap; 332 333 boothowto = howto; 334 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 335 syncing = 1; 336 vfs_shutdown(); /* sync */ 337 resettodr(); /* set wall clock */ 338 } 339 splhigh(); 340 if (howto & RB_HALT) { 341 doshutdownhooks(); 342 pmf_system_shutdown(boothowto); 343 printf("halted\n\n"); 344 cnhalt(); 345 while(1); 346 } 347 if (!cold && (howto & RB_DUMP)) 348 oea_dumpsys(); 349 doshutdownhooks(); 350 351 pmf_system_shutdown(boothowto); 352 printf("rebooting\n\n"); 353 if (what && *what) { 354 if (strlen(what) > sizeof str - 5) 355 printf("boot string too large, ignored\n"); 356 else { 357 strcpy(str, what); 358 ap1 = ap = str + strlen(str); 359 *ap++ = ' '; 360 } 361 } 362 *ap++ = '-'; 363 if (howto & RB_SINGLE) 364 *ap++ = 's'; 365 if (howto & RB_KDB) 366 *ap++ = 'd'; 367 *ap++ = 0; 368 if (ap[-2] == '-') 369 *ap1 = 0; 370 gt_watchdog_reset(); 371 /* NOTREACHED */ 372 while (1); 373 } 374 375 void 376 mem_regions(struct mem_region **mem, struct mem_region **avail) 377 { 378 379 *mem = physmemr; 380 *avail = availmemr; 381 } 382 383 static void 384 gt_bus_space_init(void) 385 { 386 const struct gt_decode_info *di; 387 uint32_t datal, datah; 388 int bs, i; 389 390 bs = 0; 391 bus_space_init(&ev64260_gt_bs_tag, "gt", 392 ex_storage[bs], sizeof(ex_storage[bs])); 393 bs++; 394 395 for (i = 0, di = &decode_regs[4]; i < 5; i++, di++) { 396 struct powerpc_bus_space *memt = ev64260_obio_bs_tags[i]; 397 398 datal = in32rb(gt_base + di->low_decode); 399 datah = in32rb(gt_base + di->high_decode); 400 401 if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) { 402 ev64260_obio_bs_tags[i] = NULL; 403 continue; 404 } 405 memt->pbs_offset = GT_LowAddr_GET(datal); 406 memt->pbs_limit = GT_HighAddr_GET(datah) + 1 - 407 memt->pbs_offset; 408 409 bus_space_init(memt, "obio2", 410 ex_storage[bs], sizeof(ex_storage[bs])); 411 bs++; 412 } 413 414 datal = in32rb(gt_base + GT_PCI0_Mem0_Low_Decode); 415 datah = in32rb(gt_base + GT_PCI0_Mem0_High_Decode); 416 #if defined(GT_PCI0_MEMBASE) 417 datal &= ~0xfff; 418 datal |= (GT_PCI0_MEMBASE >> 20); 419 out32rb(gt_base + GT_PCI0_Mem0_Low_Decode, datal); 420 #endif 421 #if defined(GT_PCI0_MEMSIZE) 422 datah &= ~0xfff; 423 datah |= (GT_PCI0_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 424 out32rb(gt_base + GT_PCI0_Mem0_High_Decode, datal); 425 #endif 426 ev64260_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 427 ev64260_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 428 429 bus_space_init(&ev64260_pci0_mem_bs_tag, "pci0-mem", 430 ex_storage[bs], sizeof(ex_storage[bs])); 431 bs++; 432 433 #if 1 /* XXXXXX */ 434 /* 435 * Make sure PCI0 Memory is BAT mapped. 436 */ 437 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 438 oea_iobat_add(ev64260_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, 439 BAT_BL_256M); 440 #endif 441 442 /* 443 * Make sure that I/O space start at 0. 444 */ 445 out32rb(gt_base + GT_PCI1_IO_Remap, 0); 446 447 datal = in32rb(gt_base + GT_PCI0_IO_Low_Decode); 448 datah = in32rb(gt_base + GT_PCI0_IO_High_Decode); 449 #if defined(GT_PCI0_IOBASE) 450 datal &= ~0xfff; 451 datal |= (GT_PCI0_IOBASE >> 20); 452 out32rb(gt_base + GT_PCI0_IO_Low_Decode, datal); 453 #endif 454 #if defined(GT_PCI0_IOSIZE) 455 datah &= ~0xfff; 456 datah |= (GT_PCI0_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 457 out32rb(gt_base + GT_PCI0_IO_High_Decode, datal); 458 #endif 459 ev64260_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 460 ev64260_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 461 ev64260_pci0_io_bs_tag.pbs_offset; 462 463 bus_space_init(&ev64260_pci0_io_bs_tag, "pci0-ioport", 464 ex_storage[bs], sizeof(ex_storage[bs])); 465 bs++; 466 467 datal = in32rb(gt_base + GT_PCI1_Mem0_Low_Decode); 468 datah = in32rb(gt_base + GT_PCI1_Mem0_High_Decode); 469 #if defined(GT_PCI1_MEMBASE) 470 datal &= ~0xfff; 471 datal |= (GT_PCI1_MEMBASE >> 20); 472 out32rb(gt_base + GT_PCI1_Mem0_Low_Decode, datal); 473 #endif 474 #if defined(GT_PCI1_MEMSIZE) 475 datah &= ~0xfff; 476 datah |= (GT_PCI1_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 477 out32rb(gt_base + GT_PCI1_Mem0_High_Decode, datal); 478 #endif 479 ev64260_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 480 ev64260_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 481 482 bus_space_init(&ev64260_pci1_mem_bs_tag, "pci1-mem", 483 ex_storage[bs], sizeof(ex_storage[bs])); 484 bs++; 485 486 #if 1 /* XXXXXX */ 487 /* 488 * Make sure PCI1 Memory is BAT mapped. 489 */ 490 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 491 oea_iobat_add(ev64260_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, 492 BAT_BL_256M); 493 #endif 494 495 /* 496 * Make sure that I/O space start at 0. 497 */ 498 out32rb(gt_base + GT_PCI1_IO_Remap, 0); 499 500 datal = in32rb(gt_base + GT_PCI1_IO_Low_Decode); 501 datah = in32rb(gt_base + GT_PCI1_IO_High_Decode); 502 #if defined(GT_PCI1_IOBASE) 503 datal &= ~0xfff; 504 datal |= (GT_PCI1_IOBASE >> 20); 505 out32rb(gt_base + GT_PCI1_IO_Low_Decode, datal); 506 #endif 507 #if defined(GT_PCI1_IOSIZE) 508 datah &= ~0xfff; 509 datah |= (GT_PCI1_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20; 510 out32rb(gt_base + GT_PCI1_IO_High_Decode, datal); 511 #endif 512 ev64260_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 513 ev64260_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 514 ev64260_pci1_io_bs_tag.pbs_offset; 515 516 bus_space_init(&ev64260_pci1_io_bs_tag, "pci1-ioport", 517 ex_storage[bs], sizeof(ex_storage[bs])); 518 bs++; 519 } 520 521 static inline void 522 gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel) 523 { 524 physmemr[j].start = start; 525 physmemr[j].size = end - start; 526 if (start < endkernel) 527 start = endkernel; 528 availmemr[j].start = start; 529 availmemr[j].size = end - start; 530 } 531 532 static void 533 gt_find_memory(paddr_t endkernel) 534 { 535 paddr_t start = ~0, end = 0; 536 const struct gt_decode_info *di; 537 int i, j = 0, first = 1; 538 539 /* 540 * Round kernel end to a page boundary. 541 */ 542 for (i = 0; i < 4; i++) { 543 paddr_t nstart, nend; 544 545 di = &decode_regs[i]; 546 nstart = GT_LowAddr_GET(in32rb(gt_base + di->low_decode)); 547 nend = GT_HighAddr_GET(in32rb(gt_base + di->high_decode)) + 1; 548 if (nstart >= nend) 549 continue; 550 if (first) { 551 /* 552 * First entry? Just remember it. 553 */ 554 start = nstart; 555 end = nend; 556 first = 0; 557 } else if (nstart == end) { 558 /* 559 * Contiguous? Just update the end. 560 */ 561 end = nend; 562 } else { 563 /* 564 * Disjoint? record it. 565 */ 566 gt_record_memory(j, start, end, endkernel); 567 start = nstart; 568 end = nend; 569 j++; 570 } 571 } 572 gt_record_memory(j, start, end, endkernel); 573 } 574
Indexes created Wed Oct 22 13:09:56 GMT 2025