machdep.c revision 1.5
1 /* $NetBSD: machdep.c,v 1.5 2003/03/17 23:28:09 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "opt_marvell.h" 35 #include "opt_compat_netbsd.h" 36 #include "opt_ddb.h" 37 #include "opt_inet.h" 38 #include "opt_ccitt.h" 39 #include "opt_iso.h" 40 #include "opt_ns.h" 41 #include "opt_ipkdb.h" 42 43 #include <sys/param.h> 44 #include <sys/conf.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/malloc.h> 48 #include <sys/mount.h> 49 #include <sys/msgbuf.h> 50 #include <sys/proc.h> 51 #include <sys/reboot.h> 52 #include <sys/extent.h> 53 #include <sys/syslog.h> 54 #include <sys/systm.h> 55 56 #include <uvm/uvm.h> 57 #include <uvm/uvm_extern.h> 58 59 #include <net/netisr.h> 60 61 #include <machine/bus.h> 62 #include <machine/db_machdep.h> 63 #include <machine/intr.h> 64 #include <machine/pmap.h> 65 #include <machine/powerpc.h> 66 #include <machine/trap.h> 67 68 #include <powerpc/oea/bat.h> 69 #include <powerpc/marvell/watchdog.h> 70 71 #include <ddb/db_extern.h> 72 73 #include <dev/cons.h> 74 75 #include "vga.h" 76 #if (NVGA > 0) 77 #include <dev/ic/mc6845reg.h> 78 #include <dev/ic/pcdisplayvar.h> 79 #include <dev/ic/vgareg.h> 80 #include <dev/ic/vgavar.h> 81 #endif 82 83 #include "isa.h" 84 #if (NISA > 0) 85 void isa_intr_init(void); 86 #endif 87 88 #include "pckbc.h" 89 #if (NPCKBC > 0) 90 #include <dev/isa/isareg.h> 91 #include <dev/ic/i8042reg.h> 92 #include <dev/ic/pckbcvar.h> 93 #endif 94 95 #include "com.h" 96 #if (NCOM > 0) 97 #include <sys/termios.h> 98 #include <dev/ic/comreg.h> 99 #include <dev/ic/comvar.h> 100 #endif 101 102 #include <dev/marvell/gtreg.h> 103 #include <dev/marvell/gtvar.h> 104 105 /* 106 * Global variables used here and there 107 */ 108 extern struct user *proc0paddr; 109 110 #define PMONMEMREGIONS 32 111 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 112 113 char *bootpath; 114 115 paddr_t avail_end; /* XXX temporary */ 116 117 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 118 void strayintr(int); 119 int lcsplx(int); 120 void gt_bus_space_init(void); 121 void return_to_dink(int); 122 void calc_delayconst(void); 123 124 struct powerpc_bus_space gt_pci0_mem_bs_tag = { 125 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 126 0x00000000, 0x00000000, 0x00000000, 127 }; 128 struct powerpc_bus_space gt_pci0_io_bs_tag = { 129 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 130 0x00000000, 0x00000000, 0x00000000, 131 }; 132 struct powerpc_bus_space gt_pci1_mem_bs_tag = { 133 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 134 0x00000000, 0x00000000, 0x00000000, 135 }; 136 struct powerpc_bus_space gt_pci1_io_bs_tag = { 137 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 138 0x00000000, 0x00000000, 0x00000000, 139 }; 140 struct powerpc_bus_space gt_obio2_bs_tag = { 141 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE|2, 142 0x00000000, 0x00000000, 0x00000000, 143 }; 144 struct powerpc_bus_space gt_mem_bs_tag = { 145 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 146 GT_BASE, 0x00000000, 0x00010000, 147 }; 148 149 bus_space_handle_t gt_memh; 150 151 bus_space_tag_t obio_bs_tags[5] = { 152 NULL, NULL, >_obio2_bs_tag, NULL, NULL 153 }; 154 155 static char ex_storage[6][EXTENT_FIXED_STORAGE_SIZE(8)] 156 __attribute__((aligned(8))); 157 158 #if 0 159 cons_decl(gtmpsc); 160 161 struct consdev constab[] = { 162 cons_init_halt(gtmpsc), 163 { 0 } 164 }; 165 #endif 166 167 void 168 initppc(startkernel, endkernel, args, btinfo) 169 u_int startkernel, endkernel, args; 170 void *btinfo; 171 { 172 #ifdef DDB 173 extern void *startsym, *endsym; 174 #endif 175 176 /* 177 * Hardcode 32MB for now--we should probe for this or get it 178 * from a boot loader, but for now, we are booting via an 179 * S-record loader. 180 */ 181 { /* XXX AKB */ 182 u_int32_t physmemsize; 183 184 physmemsize = 92 * 1024 * 1024; 185 physmemr[0].start = 0; 186 physmemr[0].size = physmemsize; 187 physmemr[1].size = 0; 188 availmemr[0].start = (endkernel + PGOFSET) & ~PGOFSET; 189 availmemr[0].size = physmemsize - availmemr[0].start; 190 availmemr[1].size = 0; 191 } 192 avail_end = physmemr[0].start + physmemr[0].size; /* XXX temporary */ 193 194 oea_batinit(0xf0000000, BAT_BL_256M); 195 oea_init((void (*)(void))ext_intr); 196 197 gt_bus_space_init(); 198 199 calc_delayconst(); /* Set CPU clock */ 200 201 consinit(); 202 203 #if (NISA > 0) 204 isa_intr_init(); 205 #endif 206 207 /* 208 * Set the page size. 209 */ 210 uvm_setpagesize(); 211 212 /* 213 * Initialize pmap module. 214 */ 215 pmap_bootstrap(startkernel, endkernel); 216 217 #ifdef DDB 218 ddb_init((int)((u_int)endsym - (u_int)startsym), startsym, endsym); 219 #endif 220 #ifdef IPKDB 221 /* 222 * Now trap to IPKDB 223 */ 224 ipkdb_init(); 225 if (boothowto & RB_KDB) 226 ipkdb_connect(0); 227 #endif 228 } 229 230 void 231 mem_regions(mem, avail) 232 struct mem_region **mem, **avail; 233 { 234 *mem = physmemr; 235 *avail = availmemr; 236 } 237 238 /* 239 * Machine dependent startup code. 240 */ 241 void 242 cpu_startup() 243 { 244 register_t msr; 245 246 oea_startup(NULL); 247 248 /* 249 * Now that we have VM, malloc()s are OK in bus_space. 250 */ 251 bus_space_mallocok(); 252 253 /* 254 * Now allow hardware interrupts. 255 */ 256 splhigh(); 257 __asm __volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 258 : "=r"(msr) 259 : "K"(PSL_EE)); 260 } 261 262 /* 263 * consinit 264 * Initialize system console. 265 */ 266 void 267 consinit() 268 { 269 #if 1 270 /* PPCBOOT using COM1 @ 57600 */ 271 comcnattach(>_obio2_bs_tag, 0, 57600, COM_FREQ*2, 272 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 273 #else 274 cninit(); 275 #endif 276 } 277 278 #if (NPCKBC > 0) && (NPCKBD == 0) 279 /* 280 * glue code to support old console code with the 281 * mi keyboard controller driver 282 */ 283 int 284 pckbc_machdep_cnattach(kbctag, kbcslot) 285 pckbc_tag_t kbctag; 286 pckbc_slot_t kbcslot; 287 { 288 #if (NPC > 0) 289 return (pcconskbd_cnattach(kbctag, kbcslot)); 290 #else 291 return (ENXIO); 292 #endif 293 } 294 #endif 295 296 /* 297 * Stray interrupts. 298 */ 299 void 300 strayintr(int irq) 301 { 302 log(LOG_ERR, "stray interrupt %d\n", irq); 303 } 304 305 /* 306 * Halt or reboot the machine after syncing/dumping according to howto. 307 */ 308 void 309 cpu_reboot(howto, what) 310 int howto; 311 char *what; 312 { 313 static int syncing; 314 static char str[256]; 315 char *ap = str, *ap1 = ap; 316 317 boothowto = howto; 318 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 319 syncing = 1; 320 vfs_shutdown(); /* sync */ 321 resettodr(); /* set wall clock */ 322 } 323 splhigh(); 324 if (howto & RB_HALT) { 325 doshutdownhooks(); 326 printf("halted\n\n"); 327 cnhalt(); 328 while(1); 329 } 330 if (!cold && (howto & RB_DUMP)) 331 oea_dumpsys(); 332 doshutdownhooks(); 333 printf("rebooting\n\n"); 334 if (what && *what) { 335 if (strlen(what) > sizeof str - 5) 336 printf("boot string too large, ignored\n"); 337 else { 338 strcpy(str, what); 339 ap1 = ap = str + strlen(str); 340 *ap++ = ' '; 341 } 342 } 343 *ap++ = '-'; 344 if (howto & RB_SINGLE) 345 *ap++ = 's'; 346 if (howto & RB_KDB) 347 *ap++ = 'd'; 348 *ap++ = 0; 349 if (ap[-2] == '-') 350 *ap1 = 0; 351 #if 0 352 { 353 void mvpppc_reboot(void); 354 mvpppc_reboot(); 355 } 356 #endif 357 gt_watchdog_reset(); 358 /* NOTREACHED */ 359 while (1); 360 } 361 362 int 363 lcsplx(ipl) 364 int ipl; 365 { 366 return spllower(ipl); 367 } 368 369 int 370 gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr) 371 { 372 enaddr[0] = 0x02; 373 enaddr[1] = 0x00; 374 enaddr[2] = 0x04; 375 enaddr[3] = 0x00; 376 enaddr[4] = 0x00; 377 enaddr[5] = 0x04 + macno; 378 379 return 0; 380 } 381 382 void 383 gt_bus_space_init(void) 384 { 385 bus_space_tag_t gt_memt = >_mem_bs_tag; 386 uint32_t datal, datah; 387 int error; 388 389 error = bus_space_init(>_mem_bs_tag, "gtmem", 390 ex_storage[1], sizeof(ex_storage[0])); 391 392 393 error = bus_space_map(gt_memt, 0, 4096, 0, >_memh); 394 395 datal = bus_space_read_4(gt_memt, gt_memh, GT_CS2_Low_Decode); 396 datah = bus_space_read_4(gt_memt, gt_memh, GT_CS2_High_Decode); 397 gt_obio2_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 398 gt_obio2_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 399 gt_obio2_bs_tag.pbs_offset; 400 401 error = bus_space_init(>_obio2_bs_tag, "obio2", 402 ex_storage[1], sizeof(ex_storage[1])); 403 404 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode); 405 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode); 406 gt_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 407 gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 408 409 error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem", 410 ex_storage[2], sizeof(ex_storage[2])); 411 412 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode); 413 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode); 414 gt_pci0_io_bs_tag.pbs_base = GT_LowAddr_GET(datal); 415 gt_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 416 gt_pci0_io_bs_tag.pbs_offset; 417 418 error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport", 419 ex_storage[3], sizeof(ex_storage[3])); 420 421 #if 0 422 error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent, 423 0x10000, 0x7F0000, EX_NOWAIT); 424 if (error) 425 panic("gt_bus_space_init: can't block out reserved " 426 "I/O space 0x10000-0x7fffff: error=%d\n", error); 427 #endif 428 429 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode); 430 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode); 431 gt_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 432 gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 433 434 error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem", 435 ex_storage[4], sizeof(ex_storage[4])); 436 437 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode); 438 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode); 439 gt_pci1_io_bs_tag.pbs_base = GT_LowAddr_GET(datal); 440 gt_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 441 442 error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport", 443 ex_storage[5], sizeof(ex_storage[5])); 444 445 #if 0 446 error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent, 447 0x10000, 0x7F0000, EX_NOWAIT); 448 if (error) 449 panic("gt_bus_space_init: can't block out reserved " 450 "I/O space 0x10000-0x7fffff: error=%d\n", error); 451 #endif 452 } 453
Indexes created Tue Sep 30 20:09:53 GMT 2025