machdep.c revision 1.7
1 /* $NetBSD: machdep.c,v 1.7 2003/03/18 19:33:50 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "opt_marvell.h" 35 #include "opt_compat_netbsd.h" 36 #include "opt_ddb.h" 37 #include "opt_inet.h" 38 #include "opt_ccitt.h" 39 #include "opt_iso.h" 40 #include "opt_ns.h" 41 #include "opt_ipkdb.h" 42 43 #include <sys/param.h> 44 #include <sys/conf.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/malloc.h> 48 #include <sys/mount.h> 49 #include <sys/msgbuf.h> 50 #include <sys/proc.h> 51 #include <sys/reboot.h> 52 #include <sys/extent.h> 53 #include <sys/syslog.h> 54 #include <sys/systm.h> 55 #include <sys/termios.h> 56 57 #include <uvm/uvm.h> 58 #include <uvm/uvm_extern.h> 59 60 #include <net/netisr.h> 61 62 #include <machine/bus.h> 63 #include <machine/db_machdep.h> 64 #include <machine/intr.h> 65 #include <machine/pmap.h> 66 #include <machine/powerpc.h> 67 #include <machine/trap.h> 68 69 #include <powerpc/oea/bat.h> 70 #include <powerpc/marvell/watchdog.h> 71 72 #include <ddb/db_extern.h> 73 74 #include <dev/cons.h> 75 76 #include "vga.h" 77 #if (NVGA > 0) 78 #include <dev/ic/mc6845reg.h> 79 #include <dev/ic/pcdisplayvar.h> 80 #include <dev/ic/vgareg.h> 81 #include <dev/ic/vgavar.h> 82 #endif 83 84 #include "isa.h" 85 #if (NISA > 0) 86 void isa_intr_init(void); 87 #endif 88 89 #include "pckbc.h" 90 #if (NPCKBC > 0) 91 #include <dev/isa/isareg.h> 92 #include <dev/ic/i8042reg.h> 93 #include <dev/ic/pckbcvar.h> 94 #endif 95 96 #include "com.h" 97 #if (NCOM > 0) 98 #include <dev/ic/comreg.h> 99 #include <dev/ic/comvar.h> 100 #endif 101 102 #include <dev/marvell/gtreg.h> 103 #include <dev/marvell/gtvar.h> 104 105 #include "gtmpsc.h" 106 #if (NGTMPSC > 0) 107 #include <dev/marvell/gtsdmareg.h> 108 #include <dev/marvell/gtmpscreg.h> 109 #include <dev/marvell/gtmpscvar.h> 110 #endif 111 112 /* 113 * Global variables used here and there 114 */ 115 extern struct user *proc0paddr; 116 117 #define PMONMEMREGIONS 32 118 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 119 120 char *bootpath; 121 122 paddr_t avail_end; /* XXX temporary */ 123 124 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 125 void strayintr(int); 126 int lcsplx(int); 127 void gt_bus_space_init(void); 128 void return_to_dink(int); 129 void calc_delayconst(void); 130 131 struct powerpc_bus_space gt_pci0_mem_bs_tag = { 132 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 133 0x00000000, 0x00000000, 0x00000000, 134 }; 135 struct powerpc_bus_space gt_pci0_io_bs_tag = { 136 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 137 0x00000000, 0x00000000, 0x00000000, 138 }; 139 struct powerpc_bus_space gt_pci1_mem_bs_tag = { 140 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 141 0x00000000, 0x00000000, 0x00000000, 142 }; 143 struct powerpc_bus_space gt_pci1_io_bs_tag = { 144 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 145 0x00000000, 0x00000000, 0x00000000, 146 }; 147 struct powerpc_bus_space gt_obio2_bs_tag = { 148 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|2, 149 0x00000000, 0x00000000, 0x00000000, 150 }; 151 struct powerpc_bus_space gt_mem_bs_tag = { 152 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 153 GT_BASE, 0x00000000, 0x00010000, 154 }; 155 156 bus_space_handle_t gt_memh; 157 158 bus_space_tag_t obio_bs_tags[5] = { 159 NULL, NULL, >_obio2_bs_tag, NULL, NULL 160 }; 161 162 static char ex_storage[6][EXTENT_FIXED_STORAGE_SIZE(8)] 163 __attribute__((aligned(8))); 164 165 #if 0 166 cons_decl(gtmpsc); 167 168 struct consdev constab[] = { 169 cons_init_halt(gtmpsc), 170 { 0 } 171 }; 172 #endif 173 174 void 175 initppc(startkernel, endkernel, args, btinfo) 176 u_int startkernel, endkernel, args; 177 void *btinfo; 178 { 179 #ifdef DDB 180 extern void *startsym, *endsym; 181 #endif 182 183 /* 184 * Hardcode 32MB for now--we should probe for this or get it 185 * from a boot loader, but for now, we are booting via an 186 * S-record loader. 187 */ 188 { /* XXX AKB */ 189 u_int32_t physmemsize; 190 191 physmemsize = 92 * 1024 * 1024; 192 physmemr[0].start = 0; 193 physmemr[0].size = physmemsize; 194 physmemr[1].size = 0; 195 availmemr[0].start = (endkernel + PGOFSET) & ~PGOFSET; 196 availmemr[0].size = physmemsize - availmemr[0].start; 197 availmemr[1].size = 0; 198 } 199 avail_end = physmemr[0].start + physmemr[0].size; /* XXX temporary */ 200 201 oea_batinit(0xf0000000, BAT_BL_256M); 202 oea_init((void (*)(void))ext_intr); 203 204 gt_bus_space_init(); 205 206 calc_delayconst(); /* Set CPU clock */ 207 208 consinit(); 209 210 #if (NISA > 0) 211 isa_intr_init(); 212 #endif 213 214 /* 215 * Set the page size. 216 */ 217 uvm_setpagesize(); 218 219 /* 220 * Initialize pmap module. 221 */ 222 pmap_bootstrap(startkernel, endkernel); 223 224 #ifdef DDB 225 ddb_init((int)((u_int)endsym - (u_int)startsym), startsym, endsym); 226 #endif 227 #ifdef IPKDB 228 /* 229 * Now trap to IPKDB 230 */ 231 ipkdb_init(); 232 if (boothowto & RB_KDB) 233 ipkdb_connect(0); 234 #endif 235 } 236 237 void 238 mem_regions(mem, avail) 239 struct mem_region **mem, **avail; 240 { 241 *mem = physmemr; 242 *avail = availmemr; 243 } 244 245 /* 246 * Machine dependent startup code. 247 */ 248 void 249 cpu_startup() 250 { 251 register_t msr; 252 253 oea_startup(NULL); 254 255 /* 256 * Now that we have VM, malloc()s are OK in bus_space. 257 */ 258 bus_space_mallocok(); 259 260 /* 261 * Now allow hardware interrupts. 262 */ 263 splhigh(); 264 __asm __volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 265 : "=r"(msr) 266 : "K"(PSL_EE)); 267 } 268 269 /* 270 * consinit 271 * Initialize system console. 272 */ 273 void 274 consinit() 275 { 276 #ifdef MPSC_CONSOLE 277 /* PMON using MPSC0 @ 9600 */ 278 gtmpsccnattach(>_mem_bs_tag, gt_memh, 0, 9600, 279 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 280 #else 281 /* PPCBOOT using COM1 @ 57600 */ 282 comcnattach(>_obio2_bs_tag, 0, 57600, COM_FREQ*2, 283 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 284 #endif 285 } 286 287 #if (NPCKBC > 0) && (NPCKBD == 0) 288 /* 289 * glue code to support old console code with the 290 * mi keyboard controller driver 291 */ 292 int 293 pckbc_machdep_cnattach(kbctag, kbcslot) 294 pckbc_tag_t kbctag; 295 pckbc_slot_t kbcslot; 296 { 297 #if (NPC > 0) 298 return (pcconskbd_cnattach(kbctag, kbcslot)); 299 #else 300 return (ENXIO); 301 #endif 302 } 303 #endif 304 305 /* 306 * Stray interrupts. 307 */ 308 void 309 strayintr(int irq) 310 { 311 log(LOG_ERR, "stray interrupt %d\n", irq); 312 } 313 314 /* 315 * Halt or reboot the machine after syncing/dumping according to howto. 316 */ 317 void 318 cpu_reboot(howto, what) 319 int howto; 320 char *what; 321 { 322 static int syncing; 323 static char str[256]; 324 char *ap = str, *ap1 = ap; 325 326 boothowto = howto; 327 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 328 syncing = 1; 329 vfs_shutdown(); /* sync */ 330 resettodr(); /* set wall clock */ 331 } 332 splhigh(); 333 if (howto & RB_HALT) { 334 doshutdownhooks(); 335 printf("halted\n\n"); 336 cnhalt(); 337 while(1); 338 } 339 if (!cold && (howto & RB_DUMP)) 340 oea_dumpsys(); 341 doshutdownhooks(); 342 printf("rebooting\n\n"); 343 if (what && *what) { 344 if (strlen(what) > sizeof str - 5) 345 printf("boot string too large, ignored\n"); 346 else { 347 strcpy(str, what); 348 ap1 = ap = str + strlen(str); 349 *ap++ = ' '; 350 } 351 } 352 *ap++ = '-'; 353 if (howto & RB_SINGLE) 354 *ap++ = 's'; 355 if (howto & RB_KDB) 356 *ap++ = 'd'; 357 *ap++ = 0; 358 if (ap[-2] == '-') 359 *ap1 = 0; 360 #if 0 361 { 362 void mvpppc_reboot(void); 363 mvpppc_reboot(); 364 } 365 #endif 366 gt_watchdog_reset(); 367 /* NOTREACHED */ 368 while (1); 369 } 370 371 int 372 lcsplx(ipl) 373 int ipl; 374 { 375 return spllower(ipl); 376 } 377 378 int 379 gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr) 380 { 381 enaddr[0] = 0x02; 382 enaddr[1] = 0x00; 383 enaddr[2] = 0x04; 384 enaddr[3] = 0x00; 385 enaddr[4] = 0x00; 386 enaddr[5] = 0x04 + macno; 387 388 return 0; 389 } 390 391 void 392 gt_bus_space_init(void) 393 { 394 bus_space_tag_t gt_memt = >_mem_bs_tag; 395 uint32_t datal, datah; 396 int error; 397 398 error = bus_space_init(>_mem_bs_tag, "gtmem", 399 ex_storage[0], sizeof(ex_storage[0])); 400 401 402 error = bus_space_map(gt_memt, 0, 4096, 0, >_memh); 403 404 datal = bus_space_read_4(gt_memt, gt_memh, GT_CS2_Low_Decode); 405 datah = bus_space_read_4(gt_memt, gt_memh, GT_CS2_High_Decode); 406 gt_obio2_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 407 gt_obio2_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 408 gt_obio2_bs_tag.pbs_offset; 409 410 error = bus_space_init(>_obio2_bs_tag, "obio2", 411 ex_storage[1], sizeof(ex_storage[1])); 412 413 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode); 414 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode); 415 gt_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 416 gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 417 418 error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem", 419 ex_storage[2], sizeof(ex_storage[2])); 420 421 /* 422 * Make sure PCI0 Memory is BAT mapped. 423 */ 424 oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 425 426 /* 427 * Make sure that I/O space start at 0. 428 */ 429 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 430 431 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode); 432 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode); 433 gt_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 434 gt_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 435 gt_pci0_io_bs_tag.pbs_offset; 436 437 error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport", 438 ex_storage[3], sizeof(ex_storage[3])); 439 440 #if 0 441 error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent, 442 0x10000, 0x7F0000, EX_NOWAIT); 443 if (error) 444 panic("gt_bus_space_init: can't block out reserved " 445 "I/O space 0x10000-0x7fffff: error=%d\n", error); 446 #endif 447 448 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode); 449 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode); 450 gt_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 451 gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 452 453 error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem", 454 ex_storage[4], sizeof(ex_storage[4])); 455 456 /* 457 * Make sure PCI1 Memory is BAT mapped. 458 */ 459 oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 460 461 /* 462 * Make sure that I/O space start at 0. 463 */ 464 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 465 466 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode); 467 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode); 468 gt_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 469 gt_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 470 gt_pci1_io_bs_tag.pbs_offset; 471 472 error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport", 473 ex_storage[5], sizeof(ex_storage[5])); 474 475 #if 0 476 error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent, 477 0x10000, 0x7F0000, EX_NOWAIT); 478 if (error) 479 panic("gt_bus_space_init: can't block out reserved " 480 "I/O space 0x10000-0x7fffff: error=%d\n", error); 481 #endif 482 } 483
Indexes created Tue Sep 30 11:09:46 GMT 2025