machdep.c revision 1.8
1 /* $NetBSD: machdep.c,v 1.8 2003/03/24 17:07:18 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "opt_marvell.h" 35 #include "opt_ev64260.h" 36 #include "opt_compat_netbsd.h" 37 #include "opt_ddb.h" 38 #include "opt_inet.h" 39 #include "opt_ccitt.h" 40 #include "opt_iso.h" 41 #include "opt_ns.h" 42 #include "opt_ipkdb.h" 43 44 #include <sys/param.h> 45 #include <sys/conf.h> 46 #include <sys/device.h> 47 #include <sys/kernel.h> 48 #include <sys/malloc.h> 49 #include <sys/mount.h> 50 #include <sys/msgbuf.h> 51 #include <sys/proc.h> 52 #include <sys/reboot.h> 53 #include <sys/extent.h> 54 #include <sys/syslog.h> 55 #include <sys/systm.h> 56 #include <sys/termios.h> 57 58 #include <uvm/uvm.h> 59 #include <uvm/uvm_extern.h> 60 61 #include <net/netisr.h> 62 63 #include <machine/bus.h> 64 #include <machine/db_machdep.h> 65 #include <machine/intr.h> 66 #include <machine/pmap.h> 67 #include <machine/powerpc.h> 68 #include <machine/trap.h> 69 70 #include <powerpc/oea/bat.h> 71 #include <powerpc/marvell/watchdog.h> 72 73 #include <ddb/db_extern.h> 74 75 #include <dev/cons.h> 76 77 #include "vga.h" 78 #if (NVGA > 0) 79 #include <dev/ic/mc6845reg.h> 80 #include <dev/ic/pcdisplayvar.h> 81 #include <dev/ic/vgareg.h> 82 #include <dev/ic/vgavar.h> 83 #endif 84 85 #include "isa.h" 86 #if (NISA > 0) 87 void isa_intr_init(void); 88 #endif 89 90 #include "pckbc.h" 91 #if (NPCKBC > 0) 92 #include <dev/isa/isareg.h> 93 #include <dev/ic/i8042reg.h> 94 #include <dev/ic/pckbcvar.h> 95 #endif 96 97 #include "com.h" 98 #if (NCOM > 0) 99 #include <dev/ic/comreg.h> 100 #include <dev/ic/comvar.h> 101 #endif 102 103 #include <dev/marvell/gtreg.h> 104 #include <dev/marvell/gtvar.h> 105 #include <dev/marvell/gtethreg.h> 106 107 #include "gtmpsc.h" 108 #if (NGTMPSC > 0) 109 #include <dev/marvell/gtsdmareg.h> 110 #include <dev/marvell/gtmpscreg.h> 111 #include <dev/marvell/gtmpscvar.h> 112 #endif 113 114 /* 115 * Global variables used here and there 116 */ 117 extern struct user *proc0paddr; 118 119 #define PMONMEMREGIONS 32 120 struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS]; 121 122 char *bootpath; 123 124 void initppc(u_int, u_int, u_int, void *); /* Called from locore */ 125 void strayintr(int); 126 int lcsplx(int); 127 void gt_bus_space_init(void); 128 void gt_find_memory(bus_space_tag_t, bus_space_handle_t, paddr_t); 129 void gt_halt(bus_space_tag_t, bus_space_handle_t); 130 void return_to_dink(int); 131 void calc_delayconst(void); 132 133 void kcomcnputs(dev_t, const char *); 134 135 struct powerpc_bus_space gt_pci0_mem_bs_tag = { 136 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 137 0x00000000, 0x00000000, 0x00000000, 138 }; 139 struct powerpc_bus_space gt_pci0_io_bs_tag = { 140 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 141 0x00000000, 0x00000000, 0x00000000, 142 }; 143 struct powerpc_bus_space gt_pci1_mem_bs_tag = { 144 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 145 0x00000000, 0x00000000, 0x00000000, 146 }; 147 struct powerpc_bus_space gt_pci1_io_bs_tag = { 148 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE, 149 0x00000000, 0x00000000, 0x00000000, 150 }; 151 struct powerpc_bus_space gt_obio0_bs_tag = { 152 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE, 153 0x00000000, 0x00000000, 0x00000000, 154 }; 155 struct powerpc_bus_space gt_obio1_bs_tag = { 156 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE, 157 0x00000000, 0x00000000, 0x00000000, 158 }; 159 struct powerpc_bus_space gt_obio2_bs_tag = { 160 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE, 161 0x00000000, 0x00000000, 0x00000000, 162 }; 163 struct powerpc_bus_space gt_obio3_bs_tag = { 164 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE, 165 0x00000000, 0x00000000, 0x00000000, 166 }; 167 struct powerpc_bus_space gt_bootcs_bs_tag = { 168 _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 169 0x00000000, 0x00000000, 0x00000000, 170 }; 171 struct powerpc_bus_space gt_mem_bs_tag = { 172 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 173 GT_BASE, 0x00000000, 0x00010000, 174 }; 175 176 bus_space_handle_t gt_memh; 177 178 struct powerpc_bus_space *obio_bs_tags[5] = { 179 >_obio0_bs_tag, >_obio1_bs_tag, >_obio2_bs_tag, 180 >_obio1_bs_tag, >_bootcs_bs_tag 181 }; 182 183 static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)] 184 __attribute__((aligned(8))); 185 186 const struct gt_decode_info { 187 bus_addr_t low_decode; 188 bus_addr_t high_decode; 189 } decode_regs[] = { 190 { GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 191 { GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 192 { GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 193 { GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 194 { GT_CS0_Low_Decode, GT_CS0_High_Decode }, 195 { GT_CS1_Low_Decode, GT_CS1_High_Decode }, 196 { GT_CS2_Low_Decode, GT_CS2_High_Decode }, 197 { GT_CS3_Low_Decode, GT_CS3_High_Decode }, 198 { GT_BootCS_Low_Decode, GT_BootCS_High_Decode }, 199 }; 200 201 void 202 initppc(startkernel, endkernel, args, btinfo) 203 u_int startkernel, endkernel, args; 204 void *btinfo; 205 { 206 oea_batinit(0xf0000000, BAT_BL_256M); 207 oea_init((void (*)(void))ext_intr); 208 209 calc_delayconst(); /* Set CPU clock */ 210 211 DELAY(100000); 212 213 gt_bus_space_init(); 214 gt_find_memory(>_mem_bs_tag, gt_memh, roundup(endkernel, NBPG)); 215 gt_halt(>_mem_bs_tag, gt_memh); 216 217 /* 218 * Now that we known how much memory, reinit the bats. 219 */ 220 oea_batinit(0xf0000000, BAT_BL_256M); 221 222 consinit(); 223 224 #if (NISA > 0) 225 isa_intr_init(); 226 #endif 227 228 /* 229 * Set the page size. 230 */ 231 uvm_setpagesize(); 232 233 /* 234 * Initialize pmap module. 235 */ 236 pmap_bootstrap(startkernel, endkernel); 237 238 #ifdef DDB 239 { 240 extern void *startsym, *endsym; 241 ddb_init((int)((u_int)endsym - (u_int)startsym), 242 startsym, endsym); 243 } 244 #endif 245 #ifdef IPKDB 246 /* 247 * Now trap to IPKDB 248 */ 249 ipkdb_init(); 250 if (boothowto & RB_KDB) 251 ipkdb_connect(0); 252 #endif 253 } 254 255 void 256 mem_regions(struct mem_region **mem, struct mem_region **avail) 257 { 258 *mem = physmemr; 259 *avail = availmemr; 260 } 261 262 static __inline void 263 gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel) 264 { 265 physmemr[j].start = start; 266 physmemr[j].size = end - start; 267 if (start < endkernel) 268 start = endkernel; 269 availmemr[j].start = start; 270 availmemr[j].size = end - start; 271 } 272 273 void 274 gt_find_memory(bus_space_tag_t memt, bus_space_handle_t memh, 275 paddr_t endkernel) 276 { 277 paddr_t start, end; 278 int i, j = 0, first = 1; 279 280 /* 281 * Round kernel end to a page boundary. 282 */ 283 for (i = 0; i < 4; i++) { 284 paddr_t nstart, nend; 285 nstart = GT_LowAddr_GET(bus_space_read_4(>_mem_bs_tag, 286 gt_memh, decode_regs[i].low_decode)); 287 nend = GT_HighAddr_GET(bus_space_read_4(>_mem_bs_tag, 288 gt_memh, decode_regs[i].high_decode)) + 1; 289 if (nstart >= nend) 290 continue; 291 if (first) { 292 /* 293 * First entry? Just remember it. 294 */ 295 start = nstart; 296 end = nend; 297 first = 0; 298 } else if (nstart == end) { 299 /* 300 * Contiguous? Just update the end. 301 */ 302 end = nend; 303 } else { 304 /* 305 * Disjoint? record it. 306 */ 307 gt_record_memory(j, start, end, endkernel); 308 start = nstart; 309 end = nend; 310 j++; 311 } 312 } 313 gt_record_memory(j, start, end, endkernel); 314 } 315 316 /* 317 * Machine dependent startup code. 318 */ 319 void 320 cpu_startup(void) 321 { 322 register_t msr; 323 324 oea_startup(NULL); 325 326 /* 327 * Now that we have VM, malloc()s are OK in bus_space. 328 */ 329 bus_space_mallocok(); 330 331 /* 332 * Now allow hardware interrupts. 333 */ 334 splhigh(); 335 __asm __volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0" 336 : "=r"(msr) 337 : "K"(PSL_EE)); 338 } 339 340 /* 341 * consinit 342 * Initialize system console. 343 */ 344 void 345 consinit(void) 346 { 347 #ifdef MPSC_CONSOLE 348 /* PMON using MPSC0 @ 9600 */ 349 gtmpsccnattach(>_mem_bs_tag, gt_memh, MPSC_CONSOLE, 9600, 350 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 351 #else 352 /* PPCBOOT using COM1 @ 57600 */ 353 comcnattach(>_obio2_bs_tag, 0, 57600, COM_FREQ*2, 354 (TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8); 355 #endif 356 } 357 358 #if (NPCKBC > 0) && (NPCKBD == 0) 359 /* 360 * glue code to support old console code with the 361 * mi keyboard controller driver 362 */ 363 int 364 pckbc_machdep_cnattach(pckbc_tag_t kbctag, pckbc_slot_t kbcslot) 365 { 366 #if (NPC > 0) 367 return (pcconskbd_cnattach(kbctag, kbcslot)); 368 #else 369 return (ENXIO); 370 #endif 371 } 372 #endif 373 374 /* 375 * Stray interrupts. 376 */ 377 void 378 strayintr(int irq) 379 { 380 log(LOG_ERR, "stray interrupt %d\n", irq); 381 } 382 383 /* 384 * Halt or reboot the machine after syncing/dumping according to howto. 385 */ 386 void 387 cpu_reboot(int howto, char *what) 388 { 389 static int syncing; 390 static char str[256]; 391 char *ap = str, *ap1 = ap; 392 393 boothowto = howto; 394 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 395 syncing = 1; 396 vfs_shutdown(); /* sync */ 397 resettodr(); /* set wall clock */ 398 } 399 splhigh(); 400 if (howto & RB_HALT) { 401 doshutdownhooks(); 402 printf("halted\n\n"); 403 cnhalt(); 404 while(1); 405 } 406 if (!cold && (howto & RB_DUMP)) 407 oea_dumpsys(); 408 doshutdownhooks(); 409 printf("rebooting\n\n"); 410 if (what && *what) { 411 if (strlen(what) > sizeof str - 5) 412 printf("boot string too large, ignored\n"); 413 else { 414 strcpy(str, what); 415 ap1 = ap = str + strlen(str); 416 *ap++ = ' '; 417 } 418 } 419 *ap++ = '-'; 420 if (howto & RB_SINGLE) 421 *ap++ = 's'; 422 if (howto & RB_KDB) 423 *ap++ = 'd'; 424 *ap++ = 0; 425 if (ap[-2] == '-') 426 *ap1 = 0; 427 #if 0 428 { 429 void mvpppc_reboot(void); 430 mvpppc_reboot(); 431 } 432 #endif 433 gt_watchdog_reset(); 434 /* NOTREACHED */ 435 while (1); 436 } 437 438 int 439 lcsplx(int ipl) 440 { 441 return spllower(ipl); 442 } 443 444 void 445 gt_halt(bus_space_tag_t gt_memt, bus_space_handle_t gt_memh) 446 { 447 int i; 448 u_int32_t data; 449 450 bus_space_write_4(gt_memt, gt_memh, 451 SDMA_U_SDCM(0), SDMA_SDCM_AR|SDMA_SDCM_AT); 452 bus_space_write_4(gt_memt, gt_memh, 453 SDMA_U_SDCM(1), SDMA_SDCM_AR|SDMA_SDCM_AT); 454 /* 455 * Shut down the Ethernets 456 */ 457 for (i = 0; i < 3; i++) { 458 bus_space_write_4(gt_memt, gt_memh, 459 ETH_ESDCMR(2), ETH_ESDCMR_AR|ETH_ESDCMR_AT); 460 for (;;) { 461 data = bus_space_read_4(gt_memt, gt_memh, 462 ETH_ESDCMR(i)); 463 if (((ETH_ESDCMR_AR|ETH_ESDCMR_AT) & data) == 0) 464 break; 465 } 466 data = bus_space_read_4(gt_memt, gt_memh, ETH_EPCR(i)); 467 data &= ~ETH_EPCR_EN; 468 bus_space_write_4(gt_memt, gt_memh, ETH_EPCR(i), data); 469 } 470 } 471 472 int 473 gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr) 474 { 475 enaddr[0] = 0x02; 476 enaddr[1] = 0x00; 477 enaddr[2] = 0x04; 478 enaddr[3] = 0x00; 479 enaddr[4] = 0x00; 480 enaddr[5] = 0x04 + macno; 481 482 return 0; 483 } 484 485 void 486 gt_bus_space_init(void) 487 { 488 bus_space_tag_t gt_memt = >_mem_bs_tag; 489 const struct gt_decode_info *di; 490 uint32_t datal, datah; 491 int error; 492 int bs = 0; 493 int j; 494 495 error = bus_space_init(>_mem_bs_tag, "gtmem", 496 ex_storage[bs], sizeof(ex_storage[bs])); 497 498 error = bus_space_map(gt_memt, 0, 0x10000, 0, >_memh); 499 500 for (j = 0, di = &decode_regs[4]; j < 5; j++, di++) { 501 struct powerpc_bus_space *memt = obio_bs_tags[j]; 502 datal = bus_space_read_4(gt_memt, gt_memh, di->low_decode); 503 datah = bus_space_read_4(gt_memt, gt_memh, di->high_decode); 504 505 if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) { 506 obio_bs_tags[j] = NULL; 507 continue; 508 } 509 memt->pbs_offset = GT_LowAddr_GET(datal); 510 memt->pbs_limit = GT_HighAddr_GET(datah) + 1 - 511 memt->pbs_offset; 512 513 error = bus_space_init(memt, "obio2", 514 ex_storage[bs], sizeof(ex_storage[bs])); 515 bs++; 516 } 517 518 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode); 519 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode); 520 gt_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 521 gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 522 523 error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem", 524 ex_storage[bs], sizeof(ex_storage[bs])); 525 bs++; 526 527 /* 528 * Make sure PCI0 Memory is BAT mapped. 529 */ 530 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 531 oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 532 533 /* 534 * Make sure that I/O space start at 0. 535 */ 536 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 537 538 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode); 539 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode); 540 gt_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 541 gt_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 542 gt_pci0_io_bs_tag.pbs_offset; 543 544 error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport", 545 ex_storage[bs], sizeof(ex_storage[bs])); 546 bs++; 547 548 #if 0 549 error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent, 550 0x10000, 0x7F0000, EX_NOWAIT); 551 if (error) 552 panic("gt_bus_space_init: can't block out reserved " 553 "I/O space 0x10000-0x7fffff: error=%d\n", error); 554 #endif 555 556 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode); 557 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode); 558 gt_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal); 559 gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1; 560 561 error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem", 562 ex_storage[bs], sizeof(ex_storage[bs])); 563 bs++; 564 565 /* 566 * Make sure PCI1 Memory is BAT mapped. 567 */ 568 if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal)) 569 oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M); 570 571 /* 572 * Make sure that I/O space start at 0. 573 */ 574 bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0); 575 576 datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode); 577 datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode); 578 gt_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal); 579 gt_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 - 580 gt_pci1_io_bs_tag.pbs_offset; 581 582 error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport", 583 ex_storage[bs], sizeof(ex_storage[bs])); 584 bs++; 585 586 #if 0 587 error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent, 588 0x10000, 0x7F0000, EX_NOWAIT); 589 if (error) 590 panic("gt_bus_space_init: can't block out reserved " 591 "I/O space 0x10000-0x7fffff: error=%d\n", error); 592 #endif 593 } 594
Indexes created Tue Sep 30 20:09:53 GMT 2025