explora_start.S revision 1.1
1 /* $NetBSD: explora_start.S,v 1.1 2003/03/11 10:57:56 hannken Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Juergen Hannken-Illjes. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial state: 41 * 42 * iccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff 43 * dccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff 44 * dcwr = 0x00000000 45 * msr = 0x00001000 ME=machine check enable 46 * 47 */ 48 49 #include "assym.h" 50 51 #include <machine/param.h> 52 #include <machine/psl.h> 53 #include <machine/trap.h> 54 #include <machine/asm.h> 55 56 #include <powerpc/spr.h> 57 #include <powerpc/ibm4xx/dcr403cgx.h> 58 #include <powerpc/ibm4xx/pmap.h> 59 60 #include "opt_ddb.h" 61 #include "opt_ppcparam.h" 62 63 GLOBAL(proc0paddr) 64 .long 0 /* proc0 p_addr */ 65 66 GLOBAL(intrnames) 67 .asciz "irq0", "irq1", "irq2", "irq3" 68 .asciz "irq4", "irq5", "irq6", "irq7" 69 .asciz "irq8", "irq9", "irq10", "irq11" 70 .asciz "irq12", "irq13", "irq14", "irq15" 71 .asciz "irq16", "irq17", "irq18", "softnet" 72 .asciz "softclock", "softserial", "clock", "statclock" 73 .asciz "irq24", "irq25", "irq26", "irq27" 74 .asciz "irq28", "irq29", "irq30", "irq31" 75 GLOBAL(eintrnames) 76 .align 4 77 GLOBAL(intrcnt) 78 .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 79 .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 80 GLOBAL(eintrcnt) 81 82 /* 83 * Initially the dram starts at 0x01000000. This is way too high. 84 * We relocate dram to 0x00000000. We use the video ram at 0xf0000000 85 * as a temporary staging area. 86 */ 87 88 #define STAGE1_BASE 0xf0000000 89 90 .text 91 .globl __start 92 __start: 93 b 1f 94 nop 95 nop 96 .long 0 97 .ascii "XncdPPC\0" 98 .long 0 99 .long 0 100 101 1: 102 /* Disable exceptions, caches, invalidate all TLB's. */ 103 104 li 0,0 105 mtmsr 0 106 mttcr 0 107 mtdccr 0 108 mticcr 0 109 sync 110 isync 111 112 /* Clear caches and invalidate tlbs */ 113 li 7,256 114 mtctr 7 115 li 6,0 116 1: 117 dccci 0,6 118 addi 6,6,16 119 bdnz 1b 120 121 li 7,512 122 mtctr 7 123 li 6,0 124 1: 125 iccci 0,6 126 addi 6,6,16 127 bdnz 1b 128 129 tlbia 130 sync 131 isync 132 133 /* Get current address -- NOT the same as . */ 134 135 bl _next 136 _next: 137 mflr 3 138 subi 3,3,_next-__start 139 lis 4,STAGE1_BASE@h 140 ori 4,4,STAGE1_BASE@l 141 li 5,stage1size 142 143 1: 144 lbz 1,0(3) 145 mr 0,5 146 cmpwi 0,0 147 stb 1,0(4) 148 addi 3,3,1 149 addi 4,4,1 150 addi 5,5,-1 151 bgt 1b 152 153 /* Jump into the staging area so we can remap the dram. */ 154 155 lis 0,stage1reloc@h 156 ori 0,0,stage1reloc@l 157 mtlr 0 158 blr 159 160 stage1reloc = .-__start+STAGE1_BASE 161 162 /* Remap the dram from 0x01000000 to 0x00000000. */ 163 164 #define REMAP(r, tmp1, tmp2) \ 165 mfbr##r tmp1 ; \ 166 lis tmp2,0xff ; \ 167 ori tmp2,tmp2,0xffff ; \ 168 cmplw tmp1,tmp2 ; \ 169 ble 1f ; \ 170 addis tmp1,tmp1,0xf000 ; \ 171 mtbr##r tmp1 ; \ 172 1: 173 174 REMAP(4, 1, 2) 175 REMAP(5, 1, 2) 176 REMAP(6, 1, 2) 177 REMAP(7, 1, 2) 178 179 #undef REMAP 180 181 /* Initial setup. */ 182 183 ba stage2 184 185 stage2: 186 187 #ifdef PPC_4XX_NOCACHE 188 li 0,0 189 #else 190 lis 0,0xfffc 191 #endif 192 mtdccr 0 193 mticcr 0 194 sync 195 isync 196 197 /* get start of bss */ 198 lis 7,_C_LABEL(edata)-4@h 199 ori 7,7,_C_LABEL(edata)-4@l 200 /* get end of kernel */ 201 lis 4,_C_LABEL(end)@h 202 ori 4,4,_C_LABEL(end)@l 203 /* clear bss */ 204 li 3,0 205 1: 206 stwu 3,4(7) 207 cmpw 7,4 208 bne+ 1b 209 210 INIT_CPUINFO(4,1,9,0) 211 212 lis 3,__start@h 213 ori 3,3,__start@l 214 215 /* Run the remaining setup in C. */ 216 bl _C_LABEL(bootstrap) 217 218 bl _C_LABEL(main) 219 220 /* NOTREACHED */ 221 2: nop 222 b 2b 223 224 stage1size = .-__start 225 226 #include <powerpc/ibm4xx/4xx_locore.S> 227
Indexes created Tue Sep 30 20:09:53 GMT 2025