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explora_start.S revision 1.10.2.1 
      1 /*	$NetBSD: explora_start.S,v 1.10.2.1 2014/05/22 11:39:45 yamt Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2003 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Juergen Hannken-Illjes.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Initial state:
     34  *
     35  * iccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff
     36  * dccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff
     37  * dcwr = 0x00000000
     38  * msr  = 0x00001000 ME=machine check enable
     39  *
     40  */
     41 
     42 #include "assym.h"
     43 
     44 #include <machine/param.h>
     45 #include <machine/psl.h>
     46 #include <machine/trap.h>
     47 #include <machine/asm.h>
     48 
     49 #include <powerpc/spr.h>
     50 #include <powerpc/ibm4xx/spr.h>
     51 #include <powerpc/ibm4xx/dcr403cgx.h>
     52 
     53 #include "opt_ddb.h"
     54 #include "opt_ppcparam.h"
     55 
     56 /*
     57  * Initially the dram starts at 0x01000000. This is way too high.
     58  * We relocate dram to 0x00000000. We use the video ram at 0xf0000000
     59  * as a temporary staging area.
     60  */
     61 
     62 #define STAGE1_BASE	0xf0000000
     63 
     64 	.text
     65 	.globl	__start
     66 __start:
     67 	b	1f
     68 	nop
     69 	nop
     70 	.long	0
     71 	.ascii	"XncdPPC\0"
     72 	.long	0
     73 	.long	0
     74 
     75 1:
     76 	/* Disable exceptions, caches, invalidate all TLB's. */
     77 
     78 	li	0,0
     79 	mtmsr	0
     80 	mttcr	0
     81 	mtdccr	0
     82 	mticcr	0
     83 	sync
     84 	isync
     85 
     86 /* Clear caches and invalidate tlbs */
     87 	li	7,256
     88 	mtctr	7
     89 	li	6,0
     90 1:
     91 	dccci	0,6
     92 	addi	6,6,16
     93 	bdnz	1b
     94 
     95 	li	7,512
     96 	mtctr	7
     97 	li	6,0
     98 1:
     99 	iccci	0,6
    100 	addi	6,6,16
    101 	bdnz	1b
    102 
    103 	tlbia
    104 	sync
    105 	isync
    106 
    107 /* Get current address -- NOT the same as . */
    108 
    109 	bl	_next
    110 _next:
    111 	mflr	3
    112 	subi	3,3,_next-__start
    113 	lis	4,STAGE1_BASE@h
    114 	ori	4,4,STAGE1_BASE@l
    115 	li	5,stage1size
    116 
    117 1:
    118 	lbz	1,0(3)
    119 	mr	0,5
    120 	cmpwi	0,0
    121 	stb	1,0(4)
    122 	addi	3,3,1
    123 	addi	4,4,1
    124 	addi	5,5,-1
    125 	bgt	1b
    126 
    127 /* Jump into the staging area so we can remap the dram. */
    128 
    129 #if 0
    130 	lis	0,stage1reloc@h
    131 	ori	0,0,stage1reloc@l
    132 #else
    133 	lis	0,((stage1reloc >> 16) & 0xffff)
    134 	ori	0,0,(stage1reloc & 0xffff)
    135 #endif
    136 	mtlr	0
    137 	blr
    138 
    139 stage1reloc = .-__start+STAGE1_BASE
    140 
    141 /* Remap the dram from 0x01000000 to 0x00000000. */
    142 
    143 #define REMAP(r, tmp1, tmp2) \
    144 	mfbr##r	tmp1 ; \
    145 	lis	tmp2,0xff ; \
    146 	ori	tmp2,tmp2,0xffff ; \
    147 	cmplw	tmp1,tmp2 ; \
    148 	ble	1f ; \
    149 	addis	tmp1,tmp1,0xf000 ; \
    150 	mtbr##r	tmp1 ; \
    151 1:
    152 
    153 	REMAP(4, 1, 2)
    154 	REMAP(5, 1, 2)
    155 	REMAP(6, 1, 2)
    156 	REMAP(7, 1, 2)
    157 
    158 #undef REMAP
    159 
    160 /* Initial setup. */
    161 
    162 	ba	stage2
    163 
    164 stage2:
    165 
    166 #ifdef PPC_4XX_NOCACHE
    167 	li	0,0
    168 #else
    169 	lis	0,0xfffc
    170 #endif
    171 	mtdccr	0
    172 	mticcr	0
    173 	sync
    174 	isync
    175 
    176 /* get start of bss */
    177 	lis	7,_C_LABEL(edata)-4@h
    178 	ori	7,7,_C_LABEL(edata)-4@l
    179 /* get end of kernel */
    180 	lis	4,_C_LABEL(end)@h
    181 	ori	4,4,_C_LABEL(end)@l
    182 /* clear bss */
    183 	li	3,0
    184 1:
    185 	stwu	3,4(7)
    186 	cmpw	7,4
    187 	bne+	1b
    188 
    189 	INIT_CPUINFO(4,1,9,0)
    190 
    191 	lis	3,__start@h
    192 	ori	3,3,__start@l
    193 
    194 /* Run the remaining setup in C. */
    195 	bl	_C_LABEL(initppc)
    196 
    197 	bl	_C_LABEL(main)
    198 
    199 	/* NOTREACHED */
    200 2:	nop
    201 	b	2b
    202 
    203 stage1size = .-__start
    204 
    205 #include <powerpc/ibm4xx/4xx_locore.S>
    206