explora_start.S revision 1.2
1 /* $NetBSD: explora_start.S,v 1.2 2003/08/11 05:13:20 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Juergen Hannken-Illjes. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial state: 41 * 42 * iccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff 43 * dccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff 44 * dcwr = 0x00000000 45 * msr = 0x00001000 ME=machine check enable 46 * 47 */ 48 49 #include "assym.h" 50 51 #define _NOREGNAMES 52 53 #include <machine/param.h> 54 #include <machine/psl.h> 55 #include <machine/trap.h> 56 #include <machine/asm.h> 57 58 #include <powerpc/spr.h> 59 #include <powerpc/ibm4xx/dcr403cgx.h> 60 #include <powerpc/ibm4xx/pmap.h> 61 62 #include "opt_ddb.h" 63 #include "opt_ppcparam.h" 64 65 GLOBAL(proc0paddr) 66 .long 0 /* proc0 p_addr */ 67 68 GLOBAL(intrnames) 69 .asciz "irq0", "irq1", "irq2", "irq3" 70 .asciz "irq4", "irq5", "irq6", "irq7" 71 .asciz "irq8", "irq9", "irq10", "irq11" 72 .asciz "irq12", "irq13", "irq14", "irq15" 73 .asciz "irq16", "irq17", "irq18", "softnet" 74 .asciz "softclock", "softserial", "clock", "statclock" 75 .asciz "irq24", "irq25", "irq26", "irq27" 76 .asciz "irq28", "irq29", "irq30", "irq31" 77 GLOBAL(eintrnames) 78 .align 4 79 GLOBAL(intrcnt) 80 .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 81 .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 82 GLOBAL(eintrcnt) 83 84 /* 85 * Initially the dram starts at 0x01000000. This is way too high. 86 * We relocate dram to 0x00000000. We use the video ram at 0xf0000000 87 * as a temporary staging area. 88 */ 89 90 #define STAGE1_BASE 0xf0000000 91 92 .text 93 .globl __start 94 __start: 95 b 1f 96 nop 97 nop 98 .long 0 99 .ascii "XncdPPC\0" 100 .long 0 101 .long 0 102 103 1: 104 /* Disable exceptions, caches, invalidate all TLB's. */ 105 106 li 0,0 107 mtmsr 0 108 mttcr 0 109 mtdccr 0 110 mticcr 0 111 sync 112 isync 113 114 /* Clear caches and invalidate tlbs */ 115 li 7,256 116 mtctr 7 117 li 6,0 118 1: 119 dccci 0,6 120 addi 6,6,16 121 bdnz 1b 122 123 li 7,512 124 mtctr 7 125 li 6,0 126 1: 127 iccci 0,6 128 addi 6,6,16 129 bdnz 1b 130 131 tlbia 132 sync 133 isync 134 135 /* Get current address -- NOT the same as . */ 136 137 bl _next 138 _next: 139 mflr 3 140 subi 3,3,_next-__start 141 lis 4,STAGE1_BASE@h 142 ori 4,4,STAGE1_BASE@l 143 li 5,stage1size 144 145 1: 146 lbz 1,0(3) 147 mr 0,5 148 cmpwi 0,0 149 stb 1,0(4) 150 addi 3,3,1 151 addi 4,4,1 152 addi 5,5,-1 153 bgt 1b 154 155 /* Jump into the staging area so we can remap the dram. */ 156 157 lis 0,stage1reloc@h 158 ori 0,0,stage1reloc@l 159 mtlr 0 160 blr 161 162 stage1reloc = .-__start+STAGE1_BASE 163 164 /* Remap the dram from 0x01000000 to 0x00000000. */ 165 166 #define REMAP(r, tmp1, tmp2) \ 167 mfbr##r tmp1 ; \ 168 lis tmp2,0xff ; \ 169 ori tmp2,tmp2,0xffff ; \ 170 cmplw tmp1,tmp2 ; \ 171 ble 1f ; \ 172 addis tmp1,tmp1,0xf000 ; \ 173 mtbr##r tmp1 ; \ 174 1: 175 176 REMAP(4, 1, 2) 177 REMAP(5, 1, 2) 178 REMAP(6, 1, 2) 179 REMAP(7, 1, 2) 180 181 #undef REMAP 182 183 /* Initial setup. */ 184 185 ba stage2 186 187 stage2: 188 189 #ifdef PPC_4XX_NOCACHE 190 li 0,0 191 #else 192 lis 0,0xfffc 193 #endif 194 mtdccr 0 195 mticcr 0 196 sync 197 isync 198 199 /* get start of bss */ 200 lis 7,_C_LABEL(edata)-4@h 201 ori 7,7,_C_LABEL(edata)-4@l 202 /* get end of kernel */ 203 lis 4,_C_LABEL(end)@h 204 ori 4,4,_C_LABEL(end)@l 205 /* clear bss */ 206 li 3,0 207 1: 208 stwu 3,4(7) 209 cmpw 7,4 210 bne+ 1b 211 212 INIT_CPUINFO(4,1,9,0) 213 214 lis 3,__start@h 215 ori 3,3,__start@l 216 217 /* Run the remaining setup in C. */ 218 bl _C_LABEL(bootstrap) 219 220 bl _C_LABEL(main) 221 222 /* NOTREACHED */ 223 2: nop 224 b 2b 225 226 stage1size = .-__start 227 228 #include <powerpc/ibm4xx/4xx_locore.S> 229
Indexes created Tue Sep 30 20:09:53 GMT 2025