explora_start.S revision 1.4
1 /* $NetBSD: explora_start.S,v 1.4 2006/06/30 17:54:50 freza Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Juergen Hannken-Illjes. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial state: 41 * 42 * iccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff 43 * dccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff 44 * dcwr = 0x00000000 45 * msr = 0x00001000 ME=machine check enable 46 * 47 */ 48 49 #include "assym.h" 50 51 #define _NOREGNAMES 52 53 #include <machine/param.h> 54 #include <machine/psl.h> 55 #include <machine/trap.h> 56 #include <machine/asm.h> 57 58 #include <powerpc/spr.h> 59 #include <powerpc/ibm4xx/dcr403cgx.h> 60 #include <powerpc/ibm4xx/pmap.h> 61 62 #include "opt_ddb.h" 63 #include "opt_ppcparam.h" 64 65 GLOBAL(proc0paddr) 66 .long 0 /* proc0 p_addr */ 67 68 /* 69 * Initially the dram starts at 0x01000000. This is way too high. 70 * We relocate dram to 0x00000000. We use the video ram at 0xf0000000 71 * as a temporary staging area. 72 */ 73 74 #define STAGE1_BASE 0xf0000000 75 76 .text 77 .globl __start 78 __start: 79 b 1f 80 nop 81 nop 82 .long 0 83 .ascii "XncdPPC\0" 84 .long 0 85 .long 0 86 87 1: 88 /* Disable exceptions, caches, invalidate all TLB's. */ 89 90 li 0,0 91 mtmsr 0 92 mttcr 0 93 mtdccr 0 94 mticcr 0 95 sync 96 isync 97 98 /* Clear caches and invalidate tlbs */ 99 li 7,256 100 mtctr 7 101 li 6,0 102 1: 103 dccci 0,6 104 addi 6,6,16 105 bdnz 1b 106 107 li 7,512 108 mtctr 7 109 li 6,0 110 1: 111 iccci 0,6 112 addi 6,6,16 113 bdnz 1b 114 115 tlbia 116 sync 117 isync 118 119 /* Get current address -- NOT the same as . */ 120 121 bl _next 122 _next: 123 mflr 3 124 subi 3,3,_next-__start 125 lis 4,STAGE1_BASE@h 126 ori 4,4,STAGE1_BASE@l 127 li 5,stage1size 128 129 1: 130 lbz 1,0(3) 131 mr 0,5 132 cmpwi 0,0 133 stb 1,0(4) 134 addi 3,3,1 135 addi 4,4,1 136 addi 5,5,-1 137 bgt 1b 138 139 /* Jump into the staging area so we can remap the dram. */ 140 141 lis 0,stage1reloc@h 142 ori 0,0,stage1reloc@l 143 mtlr 0 144 blr 145 146 stage1reloc = .-__start+STAGE1_BASE 147 148 /* Remap the dram from 0x01000000 to 0x00000000. */ 149 150 #define REMAP(r, tmp1, tmp2) \ 151 mfbr##r tmp1 ; \ 152 lis tmp2,0xff ; \ 153 ori tmp2,tmp2,0xffff ; \ 154 cmplw tmp1,tmp2 ; \ 155 ble 1f ; \ 156 addis tmp1,tmp1,0xf000 ; \ 157 mtbr##r tmp1 ; \ 158 1: 159 160 REMAP(4, 1, 2) 161 REMAP(5, 1, 2) 162 REMAP(6, 1, 2) 163 REMAP(7, 1, 2) 164 165 #undef REMAP 166 167 /* Initial setup. */ 168 169 ba stage2 170 171 stage2: 172 173 #ifdef PPC_4XX_NOCACHE 174 li 0,0 175 #else 176 lis 0,0xfffc 177 #endif 178 mtdccr 0 179 mticcr 0 180 sync 181 isync 182 183 /* get start of bss */ 184 lis 7,_C_LABEL(edata)-4@h 185 ori 7,7,_C_LABEL(edata)-4@l 186 /* get end of kernel */ 187 lis 4,_C_LABEL(end)@h 188 ori 4,4,_C_LABEL(end)@l 189 /* clear bss */ 190 li 3,0 191 1: 192 stwu 3,4(7) 193 cmpw 7,4 194 bne+ 1b 195 196 INIT_CPUINFO(4,1,9,0) 197 198 lis 3,__start@h 199 ori 3,3,__start@l 200 201 /* Run the remaining setup in C. */ 202 bl _C_LABEL(bootstrap) 203 204 bl _C_LABEL(main) 205 206 /* NOTREACHED */ 207 2: nop 208 b 2b 209 210 stage1size = .-__start 211 212 #include <powerpc/ibm4xx/4xx_locore.S> 213
Indexes created Tue Sep 30 20:09:53 GMT 2025