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explora_start.S revision 1.7.2.1 
      1 /*	$NetBSD: explora_start.S,v 1.7.2.1 2011/03/05 20:50:15 rmind Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2003 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Juergen Hannken-Illjes.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Initial state:
     34  *
     35  * iccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff
     36  * dccr = 0x00008001 0x80000000-0x87ffffff 0xf80000000-0xffffffff
     37  * dcwr = 0x00000000
     38  * msr  = 0x00001000 ME=machine check enable
     39  *
     40  */
     41 
     42 #include "assym.h"
     43 
     44 #include <machine/param.h>
     45 #include <machine/psl.h>
     46 #include <machine/trap.h>
     47 #include <machine/asm.h>
     48 
     49 #include <powerpc/spr.h>
     50 #include <powerpc/ibm4xx/spr.h>
     51 #include <powerpc/ibm4xx/dcr403cgx.h>
     52 #include <powerpc/ibm4xx/pmap.h>
     53 
     54 #include "opt_ddb.h"
     55 #include "opt_ppcparam.h"
     56 
     57 /*
     58  * Initially the dram starts at 0x01000000. This is way too high.
     59  * We relocate dram to 0x00000000. We use the video ram at 0xf0000000
     60  * as a temporary staging area.
     61  */
     62 
     63 #define STAGE1_BASE	0xf0000000
     64 
     65 	.text
     66 	.globl	__start
     67 __start:
     68 	b	1f
     69 	nop
     70 	nop
     71 	.long	0
     72 	.ascii	"XncdPPC\0"
     73 	.long	0
     74 	.long	0
     75 
     76 1:
     77 	/* Disable exceptions, caches, invalidate all TLB's. */
     78 
     79 	li	0,0
     80 	mtmsr	0
     81 	mttcr	0
     82 	mtdccr	0
     83 	mticcr	0
     84 	sync
     85 	isync
     86 
     87 /* Clear caches and invalidate tlbs */
     88 	li	7,256
     89 	mtctr	7
     90 	li	6,0
     91 1:
     92 	dccci	0,6
     93 	addi	6,6,16
     94 	bdnz	1b
     95 
     96 	li	7,512
     97 	mtctr	7
     98 	li	6,0
     99 1:
    100 	iccci	0,6
    101 	addi	6,6,16
    102 	bdnz	1b
    103 
    104 	tlbia
    105 	sync
    106 	isync
    107 
    108 /* Get current address -- NOT the same as . */
    109 
    110 	bl	_next
    111 _next:
    112 	mflr	3
    113 	subi	3,3,_next-__start
    114 	lis	4,STAGE1_BASE@h
    115 	ori	4,4,STAGE1_BASE@l
    116 	li	5,stage1size
    117 
    118 1:
    119 	lbz	1,0(3)
    120 	mr	0,5
    121 	cmpwi	0,0
    122 	stb	1,0(4)
    123 	addi	3,3,1
    124 	addi	4,4,1
    125 	addi	5,5,-1
    126 	bgt	1b
    127 
    128 /* Jump into the staging area so we can remap the dram. */
    129 
    130 	lis	0,stage1reloc@h
    131 	ori	0,0,stage1reloc@l
    132 	mtlr	0
    133 	blr
    134 
    135 stage1reloc = .-__start+STAGE1_BASE
    136 
    137 /* Remap the dram from 0x01000000 to 0x00000000. */
    138 
    139 #define REMAP(r, tmp1, tmp2) \
    140 	mfbr##r	tmp1 ; \
    141 	lis	tmp2,0xff ; \
    142 	ori	tmp2,tmp2,0xffff ; \
    143 	cmplw	tmp1,tmp2 ; \
    144 	ble	1f ; \
    145 	addis	tmp1,tmp1,0xf000 ; \
    146 	mtbr##r	tmp1 ; \
    147 1:
    148 
    149 	REMAP(4, 1, 2)
    150 	REMAP(5, 1, 2)
    151 	REMAP(6, 1, 2)
    152 	REMAP(7, 1, 2)
    153 
    154 #undef REMAP
    155 
    156 /* Initial setup. */
    157 
    158 	ba	stage2
    159 
    160 stage2:
    161 
    162 #ifdef PPC_4XX_NOCACHE
    163 	li	0,0
    164 #else
    165 	lis	0,0xfffc
    166 #endif
    167 	mtdccr	0
    168 	mticcr	0
    169 	sync
    170 	isync
    171 
    172 /* get start of bss */
    173 	lis	7,_C_LABEL(edata)-4@h
    174 	ori	7,7,_C_LABEL(edata)-4@l
    175 /* get end of kernel */
    176 	lis	4,_C_LABEL(end)@h
    177 	ori	4,4,_C_LABEL(end)@l
    178 /* clear bss */
    179 	li	3,0
    180 1:
    181 	stwu	3,4(7)
    182 	cmpw	7,4
    183 	bne+	1b
    184 
    185 	INIT_CPUINFO(4,1,9,0)
    186 
    187 	lis	3,__start@h
    188 	ori	3,3,__start@l
    189 
    190 /* Run the remaining setup in C. */
    191 	bl	_C_LABEL(bootstrap)
    192 
    193 	bl	_C_LABEL(main)
    194 
    195 	/* NOTREACHED */
    196 2:	nop
    197 	b	2b
    198 
    199 stage1size = .-__start
    200 
    201 #include <powerpc/ibm4xx/4xx_locore.S>
    202