intr.h revision 1.1
1 /* $NetBSD: intr.h,v 1.1 2002/12/09 12:16:06 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _EVBPPC_INTR_H_ 40 #define _EVBPPC_INTR_H_ 41 42 /* Interrupt priority `levels'. */ 43 #define IPL_NONE 9 /* nothing */ 44 #define IPL_SOFTCLOCK 8 /* software clock interrupt */ 45 #define IPL_SOFTNET 7 /* software network interrupt */ 46 #define IPL_BIO 6 /* block I/O */ 47 #define IPL_NET 5 /* network */ 48 #define IPL_SOFTSERIAL 4 /* software serial interrupt */ 49 #define IPL_TTY 3 /* terminal */ 50 #define IPL_IMP 3 /* memory allocation */ 51 #define IPL_AUDIO 2 /* audio */ 52 #define IPL_CLOCK 1 /* clock */ 53 #define IPL_HIGH 1 /* everything */ 54 #define IPL_SERIAL 0 /* serial */ 55 #define NIPL 10 56 57 /* Interrupt sharing types. */ 58 #define IST_NONE 0 /* none */ 59 #define IST_PULSE 1 /* pulsed */ 60 #define IST_EDGE 2 /* edge-triggered */ 61 #define IST_LEVEL 3 /* level-triggered */ 62 63 #ifndef _LOCORE 64 65 /* 66 * Interrupt handler chains. intr_establish() inserts a handler into 67 * the list. The handler is called with its (single) argument. 68 */ 69 struct intrhand { 70 int (*ih_fun)(void *); 71 void *ih_arg; 72 u_long ih_count; 73 struct intrhand *ih_next; 74 int ih_level; 75 int ih_irq; 76 }; 77 78 void setsoftclock(void); 79 int splsoftclock(void); 80 void setsoftnet(void); 81 int splsoftnet(void); 82 83 void do_pending_int(void); 84 void ext_intr(void); 85 void intr_md_register(void (*)(void *, int), void (*)(void *, int), 86 int (*)(void *), void (*)(void *, int), void *); 87 void *intr_establish(int, int, int, int (*)(void *), void *); 88 void intr_disestablish(void *); 89 void intr_init(void); 90 91 static __inline int splraise(int); 92 static __inline int spllower(int); 93 static __inline void splx(int); 94 static __inline void set_sint(int); 95 96 extern volatile int cpl, ipending, astpending; 97 extern u_long imask[]; 98 extern u_long intrcnt[]; 99 100 /* 101 * Reorder protection in the following inline functions is 102 * achived with the "eieio" instruction which the assembler 103 * seems to detect and then doesn't move instructions past.... 104 */ 105 static __inline int 106 splraise(newcpl) 107 int newcpl; 108 { 109 int oldcpl; 110 111 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 112 oldcpl = cpl; 113 cpl = oldcpl | newcpl; 114 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 115 return(oldcpl); 116 } 117 118 static __inline void 119 splx(newcpl) 120 int newcpl; 121 { 122 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 123 cpl = newcpl; 124 if(ipending & ~newcpl) 125 do_pending_int(); 126 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 127 } 128 129 static __inline int 130 spllower(newcpl) 131 int newcpl; 132 { 133 int oldcpl; 134 135 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 136 oldcpl = cpl; 137 cpl = newcpl; 138 if(ipending & ~newcpl) 139 do_pending_int(); 140 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 141 return(oldcpl); 142 } 143 144 /* Following code should be implemented with lwarx/stwcx to avoid 145 * the disable/enable. i need to read the manual once more.... */ 146 static __inline void 147 set_sint(pending) 148 int pending; 149 { 150 int msrsave; 151 152 __asm__ ("mfmsr %0" : "=r"(msrsave)); 153 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 154 ipending |= pending; 155 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 156 } 157 158 #define ICU_LEN 32 159 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN) 160 #define IRQ_TO_MASK(x) (0x80000000UL >> (x)) 161 162 /* 163 * Interrupt bits 0-18 and 25-31 are used by hardware. This 164 * leaves us bits 19-24 for stoftware. 165 */ 166 #define HWINT_MASK ~0x1fc0 167 168 /* Assign these to unused (reserved) interrupt bits: */ 169 #define CNT_SINT_NET 19 170 #define CNT_SINT_CLOCK 20 171 #define CNT_SINT_SERIAL 21 172 #define CNT_CLOCK 22 173 #define CNT_STATCLOCK 23 174 175 #define SINT_NET IRQ_TO_MASK(CNT_SINT_NET) 176 #define SINT_CLOCK IRQ_TO_MASK(CNT_SINT_CLOCK) 177 #define SINT_SERIAL IRQ_TO_MASK(CNT_SINT_SERIAL) 178 #define SPL_CLOCK IRQ_TO_MASK(CNT_CLOCK) 179 #define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL) 180 181 #define splbio() splraise(imask[IPL_BIO]) 182 #define splnet() splraise(imask[IPL_NET]) 183 #define spltty() splraise(imask[IPL_TTY]) 184 #define splclock() splraise(imask[IPL_CLOCK]) 185 #define splimp() splraise(imask[IPL_IMP]) 186 #define splvm() splraise(imask[IPL_IMP]) 187 #define splserial() splraise(imask[IPL_SERIAL]) 188 #define splstatclock() splclock() 189 #define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 190 #define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 191 #define splsoftnet() splraise(imask[IPL_SOFTNET]) 192 #define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 193 194 #define spllpt() spltty() 195 196 #define setsoftclock() set_sint(SINT_CLOCK); 197 #define setsoftnet() set_sint(SINT_NET); 198 #define setsoftserial() set_sint(SINT_SERIAL); 199 200 #define splhigh() splraise(imask[IPL_HIGH]) 201 #define spl0() spllower(0) 202 203 #define splsched() splhigh() 204 #define spllock() splhigh() 205 206 void softnet(void); 207 void softserial(void); 208 209 #endif /* !_LOCORE */ 210 211 #endif /* !_EVBPPC_INTR_H_ */ 212
Indexes created Tue Sep 23 01:09:51 GMT 2025