machdep.c revision 1.1.2.3
1 /* $NetBSD: machdep.c,v 1.1.2.3 2011/07/26 03:32:45 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/ksyms.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <machine/stdarg.h> 70 #include <powerpc/pcb.h> 71 72 #include <dev/cons.h> 73 74 #include <dev/ic/comreg.h> 75 #include <dev/ic/comvar.h> 76 77 #include <net/if.h> 78 #include <net/if_media.h> 79 #include <dev/mii/miivar.h> 80 81 #include <powerpc/spr.h> 82 #include <powerpc/booke/spr.h> 83 84 #include <powerpc/booke/cpuvar.h> 85 #include <powerpc/booke/e500reg.h> 86 #include <powerpc/booke/e500var.h> 87 #include <powerpc/booke/etsecreg.h> 88 #include <powerpc/booke/openpicreg.h> 89 #ifdef CADMUS 90 #include <evbppc/mpc85xx/cadmusreg.h> 91 #endif 92 #ifdef PIXIS 93 #include <evbppc/mpc85xx/pixisreg.h> 94 #endif 95 96 #include "ksyms.h" 97 98 void initppc(vaddr_t, vaddr_t); 99 100 #define MEMREGIONS 4 101 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 102 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 103 static u_int nmemr; 104 105 #ifndef CONSFREQ 106 # define CONSFREQ -1 /* inherit from firmware */ 107 #endif 108 #ifndef CONSPEED 109 # define CONSPEED 115200 110 #endif 111 #ifndef CONMODE 112 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 113 #endif 114 #ifndef CONSADDR 115 # define CONSADDR DUART2_BASE 116 #endif 117 118 int comcnfreq = CONSFREQ; 119 int comcnspeed = CONSPEED; 120 tcflag_t comcnmode = CONMODE; 121 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 122 123 #if NPCI > 0 124 struct extent *pcimem_ex; 125 struct extent *pciio_ex; 126 #endif 127 128 struct powerpc_bus_space gur_bst = { 129 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 130 .pbs_offset = GUR_BASE, 131 .pbs_limit = GUR_SIZE, 132 }; 133 134 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 135 136 #ifdef CADMUS 137 static uint8_t cadmus_pci; 138 static uint8_t cadmus_csr; 139 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 140 #elif defined(PIXIS) 141 static const uint32_t pixis_spd_map[8] = { 142 [PX_SPD_33MHZ] = 33333333, 143 [PX_SPD_40MHZ] = 40000000, 144 [PX_SPD_50MHZ] = 50000000, 145 [PX_SPD_66MHZ] = 66666666, 146 [PX_SPD_83MHZ] = 83333333, 147 [PX_SPD_100MHZ] = 100000000, 148 [PX_SPD_133MHZ] = 133333333, 149 [PX_SPD_166MHZ] = 166666667, 150 }; 151 static uint8_t pixis_spd; 152 static uint64_t e500_sys_clk; 153 #elif defined(SYS_CLK) 154 static uint64_t e500_sys_clk = SYS_CLK; /* from config file */ 155 #else 156 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 157 #endif 158 159 static int e500_cngetc(dev_t); 160 static void e500_cnputc(dev_t, int); 161 162 static struct consdev e500_earlycons = { 163 .cn_getc = e500_cngetc, 164 .cn_putc = e500_cnputc, 165 .cn_pollc = nullcnpollc, 166 }; 167 168 /* 169 * List of port-specific devices to attach to the processor local bus. 170 */ 171 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 172 { "cpu" }, /* not a real device */ 173 { "wdog" }, /* not a real device */ 174 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 1, 175 { ISOURCE_DUART }, 176 1 + ilog2(DEVDISR_DUART) }, 177 #if defined(MPC8548) || defined(MPC8572) 178 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 3, 179 { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 180 1 + ilog2(DEVDISR_TSEC1) }, 181 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 3, 182 { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 183 1 + ilog2(DEVDISR_TSEC2) }, 184 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 3, 185 { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 186 1 + ilog2(DEVDISR_TSEC3) }, 187 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 3, 188 { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 189 1 + ilog2(DEVDISR_TSEC4) }, 190 #endif 191 #if defined(MPC8544) || defined(MPC8536) 192 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 3, 193 { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 194 1 + ilog2(DEVDISR_TSEC1) }, 195 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 3, 196 { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 197 1 + ilog2(DEVDISR_TSEC2) }, 198 #endif 199 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 1, 200 { ISOURCE_I2C }, 201 1 + ilog2(DEVDISR_TSEC2) }, 202 #ifndef MPC8572 203 /* MPC8572 doesn't have any GPIO */ 204 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 0 }, 205 #endif 206 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 1, 207 { ISOURCE_DDR }, 208 1 + ilog2(DEVDISR_TSEC2) }, 209 #if defined(MPC8544) || defined(MPC8536) 210 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 1, 211 { ISOURCE_PCIEX }, 212 1 + ilog2(DEVDISR_PCIE) }, 213 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 1, 214 { ISOURCE_PCIEX2 }, 215 1 + ilog2(DEVDISR_PCIE3) }, 216 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 1, 217 { ISOURCE_PCIEX3 }, 218 1 + ilog2(DEVDISR_PCIE2) }, 219 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 1, 1, 220 { ISOURCE_PCI1 }, 221 1 + ilog2(DEVDISR_PCI1) }, 222 #endif 223 #ifdef MPC8548 224 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 1, 225 { ISOURCE_PCIEX }, 226 1 + ilog2(DEVDISR_PCIE) }, 227 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 1, 228 { ISOURCE_PCI1 }, 229 1 + ilog2(DEVDISR_PCI1) }, 230 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 1, 231 { ISOURCE_PCI2 }, 232 1 + ilog2(DEVDISR_PCI2) }, 233 #endif 234 #ifdef MPC8536 235 { "ehci", USB1_BASE, USB_SIZE, 1, 1, 236 { ISOURCE_USB1 }, 237 1 + ilog2(DEVDISR_USB1) }, 238 { "ehci", USB2_BASE, USB_SIZE, 2, 1, 239 { ISOURCE_USB2 }, 240 1 + ilog2(DEVDISR_USB2) }, 241 { "ehci", USB3_BASE, USB_SIZE, 3, 1, 242 { ISOURCE_USB3 }, 243 1 + ilog2(DEVDISR_USB3) }, 244 { "sata", SATA1_BASE, SATA_SIZE, 1, 1, 245 { ISOURCE_SATA1 }, 246 1 + ilog2(DEVDISR_SATA1) }, 247 { "sata", SATA2_BASE, SATA_SIZE, 2, 1, 248 { ISOURCE_SATA2 }, 249 1 + ilog2(DEVDISR_SATA2) }, 250 { "spi", SPI_BASE, SPI_SIZE, 0, 1, 251 { ISOURCE_SPI }, 252 1 + ilog2(DEVDISR_SPI) }, 253 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 1, 254 { ISOURCE_ESDHC }, 255 1 + ilog2(DEVDISR_ESDHC) }, 256 #endif 257 { "lbc", LBC_BASE, LBC_SIZE, 0, 1, 258 { ISOURCE_LBC }, 259 1 + ilog2(DEVDISR_LBC) }, 260 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 261 { NULL } 262 }; 263 264 static int 265 e500_cngetc(dev_t dv) 266 { 267 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 268 269 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 270 return -1; 271 272 return com0addr[com_data] & 0xff; 273 } 274 275 static void 276 e500_cnputc(dev_t dv, int c) 277 { 278 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 279 int timo = 150000; 280 281 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 282 ; 283 284 com0addr[com_data] = c; 285 __asm("mbar"); 286 287 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 288 ; 289 } 290 291 static void * 292 gur_tlb_mapiodev(paddr_t pa, psize_t len) 293 { 294 if (pa < gur_bst.pbs_offset) 295 return NULL; 296 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 297 return NULL; 298 return (void *)pa; 299 } 300 301 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 302 303 static void 304 e500_cpu_reset(void) 305 { 306 __asm volatile("sync"); 307 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 308 __asm volatile("msync;isync"); 309 } 310 311 static psize_t 312 memprobe(vaddr_t endkernel) 313 { 314 phys_ram_seg_t *mr; 315 316 /* 317 * First we need to find out how much physical memory we have. 318 * We could let our bootloader tell us, but it's almost as easy 319 * to ask the DDR memory controller. 320 */ 321 mr = physmemr; 322 #if 1 323 for (u_int i = 0; i < 4; i++) { 324 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 325 if (v & CS_CONFIG_EN) { 326 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 327 mr->start = BNDS_SA_GET(v); 328 mr->size = BNDS_SIZE_GET(v); 329 mr++; 330 } 331 } 332 333 if (mr == physmemr) 334 panic("no memory configured!"); 335 #else 336 mr->start = 0; 337 mr->size = 32 << 20; 338 mr++; 339 #endif 340 341 /* 342 * Sort memory regions from low to high and coalesce adjacent regions 343 */ 344 u_int cnt = mr - physmemr; 345 if (cnt > 1) { 346 for (u_int i = 0; i < cnt - 1; i++) { 347 for (u_int j = i + 1; j < cnt; j++) { 348 if (physmemr[j].start < physmemr[i].start) { 349 phys_ram_seg_t tmp = physmemr[i]; 350 physmemr[i] = physmemr[j]; 351 physmemr[j] = tmp; 352 } 353 } 354 } 355 mr = physmemr; 356 for (u_int i = 0; i < cnt; i++, mr++) { 357 if (mr->start + mr->size == mr[1].start) { 358 mr->size += mr[1].size; 359 for (u_int j = 1; j < cnt - i; j++) 360 mr[j] = mr[j+1]; 361 cnt--; 362 } 363 } 364 } 365 366 /* 367 * Copy physical memory to available memory. 368 */ 369 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 370 371 /* 372 * Adjust available memory to skip kernel at start of memory. 373 */ 374 availmemr[0].size -= endkernel - availmemr[0].start; 375 availmemr[0].start = endkernel; 376 377 /* 378 * Steal pages at the end of memory for the kernel message buffer. 379 */ 380 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 381 msgbuf_paddr = 382 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 383 384 /* 385 * Calculate physmem. 386 */ 387 for (u_int i = 0; i < cnt; i++) 388 physmem += atop(physmemr[i].size); 389 390 nmemr = cnt; 391 return physmemr[cnt-1].start + physmemr[cnt-1].size; 392 } 393 394 void 395 consinit(void) 396 { 397 static bool attached = false; 398 399 if (attached) 400 return; 401 attached = true; 402 403 if (comcnfreq == -1) { 404 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 405 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 406 comcnfreq = e500_sys_clk * plat_ratio; 407 printf(" comcnfreq=%u", comcnfreq); 408 } 409 410 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 411 COM_TYPE_NORMAL, comcnmode); 412 } 413 414 void 415 cpu_probe_cache(void) 416 { 417 struct cpu_info * const ci = curcpu(); 418 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 419 420 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 421 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 422 423 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 424 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 425 426 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 427 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 428 } else { 429 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 430 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 431 } 432 433 #ifdef DEBUG 434 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 435 if ((L1CSR_CE & l1csr0) == 0) 436 printf(" DC=off"); 437 438 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 439 if ((L1CSR_CE & l1csr1) == 0) 440 printf(" IC=off"); 441 #endif 442 } 443 444 static const char * 445 socname(uint32_t svr) 446 { 447 svr &= ~0x80000; 448 switch (svr >> 8) { 449 case SVR_MPC8548v2 >> 8: return "MPC8548"; 450 case SVR_MPC8547v2 >> 8: return "MPC8547"; 451 case SVR_MPC8545v2 >> 8: return "MPC8545"; 452 case SVR_MPC8543v2 >> 8: return "MPC8543"; 453 case SVR_MPC8544v1 >> 8: return "MPC8544"; 454 case SVR_MPC8536v1 >> 8: return "MPC8536"; 455 case SVR_MPC8572 >> 8: return "MPC8572"; 456 default: 457 panic("%s: unknown SVR %#x", __func__, svr); 458 } 459 } 460 461 static void 462 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 463 { 464 static const char units[16] = "KKKKKMMMMMGGGGGT"; 465 466 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 467 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 468 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 469 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 470 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 471 472 aprint_normal_dev(self, "%s:", name); 473 474 aprint_normal(" %u", nentries); 475 if (TLBCFG_AVAIL_P(tlbcfg)) { 476 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 477 minsize, maxsize, units[maxsize_log4k]); 478 } else { 479 aprint_normal(" fixed-size (%uKB)", minsize); 480 } 481 if (assoc == 0 || assoc == nentries) 482 aprint_normal(" fully"); 483 else 484 aprint_normal(" %u-way set", assoc); 485 aprint_normal(" associative entries\n"); 486 } 487 488 static void 489 e500_cpu_attach(device_t self, u_int instance) 490 { 491 struct cpu_info * const ci = &cpu_info[instance]; 492 493 KASSERT(instance == 0); 494 self->dv_private = ci; 495 496 ci->ci_cpuid = instance; 497 ci->ci_dev = self; 498 //ci->ci_idlespin = cpu_idlespin; 499 if (instance > 0) { 500 ci->ci_idepth = -1; 501 cpu_probe_cache(); 502 } 503 504 uint64_t freq = board_info_get_number("processor-frequency"); 505 char freqbuf[10]; 506 if (freq >= 999500000) { 507 const uint32_t freq32 = (freq + 500000) / 10000000; 508 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 509 freq32 / 100, freq32 % 100); 510 } else { 511 const uint32_t freq32 = (freq + 500000) / 1000000; 512 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 513 } 514 515 const uint32_t pvr = mfpvr(); 516 const uint32_t svr = mfspr(SPR_SVR); 517 const uint32_t pir = mfspr(SPR_PIR); 518 519 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 520 "ID %u%s\n", 521 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 522 (svr >> 4) & 15, svr & 15, 523 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 524 (pvr >> 4) & 15, pvr & 15, 525 pir, (pir == 0 ? " (Primary)" : "")); 526 527 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 528 aprint_normal_dev(self, 529 "%uKB/%uB %u-way L1 %s cache\n", 530 L1CFG_CSIZE_GET(l1cfg0) >> 10, 531 32 << L1CFG_CBSIZE_GET(l1cfg0), 532 L1CFG_CNWAY_GET(l1cfg0), 533 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 534 ? "data" : "unified"); 535 536 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 537 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 538 aprint_normal_dev(self, 539 "%uKB/%uB %u-way L1 %s cache\n", 540 L1CFG_CSIZE_GET(l1cfg1) >> 10, 541 32 << L1CFG_CBSIZE_GET(l1cfg1), 542 L1CFG_CNWAY_GET(l1cfg1), 543 "instruction"); 544 } 545 546 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 547 aprint_normal_dev(self, 548 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 549 MMUCFG_NTLBS_GET(mmucfg) + 1, 550 MMUCFG_NPIDS_GET(mmucfg), 551 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 552 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 553 554 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 555 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 556 557 intr_cpu_init(ci); 558 cpu_evcnt_attach(ci); 559 } 560 561 static void 562 calltozero(void) 563 { 564 panic("call to 0 from %p", __builtin_return_address(0)); 565 } 566 567 void 568 initppc(vaddr_t startkernel, vaddr_t endkernel) 569 { 570 struct cpu_info * const ci = curcpu(); 571 struct cpu_softc * const cpu = ci->ci_softc; 572 573 cn_tab = &e500_earlycons; 574 printf(" initppc<enter>"); 575 576 const register_t hid0 = mfspr(SPR_HID0); 577 mtspr(SPR_HID0, hid0 | HID0_TBEN | HID0_EMCP); 578 #ifdef CADMUS 579 /* 580 * Need to cache this from cadmus since we need to unmap cadmus since 581 * it falls in the middle of kernel address space. 582 */ 583 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 584 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 585 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 586 printf(" cadmus_pci=%#x", cadmus_pci); 587 printf(" cadmus_csr=%#x", cadmus_csr); 588 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 589 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 590 e500_sys_clk *= 2; 591 } 592 #endif 593 #ifdef PIXIS 594 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 595 printf(" pixis_spd=%#x ", pixis_spd); 596 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 597 #endif 598 printf(" porpllsr=0x%08x", 599 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 600 printf(" sys_clk=%"PRIu64, e500_sys_clk); 601 602 /* 603 * Make sure arguments are page aligned. 604 */ 605 startkernel = trunc_page(startkernel); 606 endkernel = round_page(endkernel); 607 608 /* 609 * Initialize the bus space tag used to access the 85xx general 610 * utility registers. It doesn't need to be extent protected. 611 * We know the GUR is mapped via a TLB1 entry so we add a limited 612 * mapiodev which allows mappings in GUR space. 613 */ 614 CTASSERT(offsetof(struct tlb_md_ops, md_tlb_mapiodev) == 0); 615 cpu_md_ops.md_tlb_ops = (const void *)&early_tlb_mapiodev; 616 bus_space_init(&gur_bst, NULL, NULL, 0); 617 cpu->cpu_bst = &gur_bst; 618 cpu->cpu_bsh = gur_bsh; 619 620 /* 621 * Attach the console early, really early. 622 */ 623 consinit(); 624 625 /* 626 * Reset the PIC to a known state. 627 */ 628 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 629 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 630 ; 631 #if 0 632 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 633 #endif 634 printf(" openpic-reset(ctpr=%u)", 635 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 636 637 /* 638 * fill in with an absolute branch to a routine that will panic. 639 */ 640 *(int *)0 = 0x48000002 | (int) calltozero; 641 642 /* 643 * Get the cache sizes. 644 */ 645 cpu_probe_cache(); 646 printf(" cache(DC=%u/%u,IC=%u/%u)", 647 ci->ci_ci.dcache_size >> 10, 648 ci->ci_ci.dcache_line_size, 649 ci->ci_ci.icache_size >> 10, 650 ci->ci_ci.icache_line_size); 651 652 /* 653 * Now find out how much memory is attached 654 */ 655 pmemsize = memprobe(endkernel); 656 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 657 658 /* 659 * Now we need cleanout the TLB of stuff that we don't need. 660 */ 661 e500_tlb_init(endkernel, pmemsize); 662 printf(" e500_tlbinit(%#lx,%zuMB)", 663 endkernel, (size_t) (pmemsize >> 20)); 664 665 /* 666 * 667 */ 668 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 669 printf(" hid1=%#lx", mfspr(SPR_HID1)); 670 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 671 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 672 673 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 674 675 /* 676 * Initialize the message buffer. 677 */ 678 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 679 printf(" msgbuf=%p", (void *)msgbuf_paddr); 680 681 /* 682 * Initialize exception vectors and interrupts 683 */ 684 exception_init(&e500_intrsw); 685 printf(" exception_init=%p", &e500_intrsw); 686 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 687 688 /* 689 * Set the page size. 690 */ 691 uvm_setpagesize(); 692 693 /* 694 * Initialize the pmap. 695 */ 696 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 697 698 /* 699 * Let's take all the indirect calls via our stubs and patch 700 * them to be direct calls. 701 */ 702 booke_fixup_stubs(); 703 #if 0 704 /* 705 * As a debug measure we can change the TLB entry that maps all of 706 * memory to one that encompasses the 64KB with the kernel vectors. 707 * All other pages will be soft faulted into the TLB as needed. 708 */ 709 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 710 mtspr(SPR_MAS6, 0); 711 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 712 uint32_t mas0 = mfspr(SPR_MAS0); 713 uint32_t mas1 = mfspr(SPR_MAS1); 714 uint32_t mas2 = mfspr(SPR_MAS2); 715 uint32_t mas3 = mfspr(SPR_MAS3); 716 KASSERT(mas3 & MAS3_SW); 717 KASSERT(mas3 & MAS3_SR); 718 KASSERT(mas3 & MAS3_SX); 719 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 720 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 721 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 722 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 723 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 724 #if 1 725 mtspr(SPR_MAS1, mas1); 726 mtspr(SPR_MAS2, mas2); 727 mtspr(SPR_MAS3, mas3); 728 extern void tlbwe(void); 729 tlbwe(); 730 mtspr(SPR_MAS0, saved_mas0); 731 printf("(ok)"); 732 #endif 733 #endif 734 735 /* 736 * Initialize a few things in lwp0. 737 */ 738 lwp0.l_md.md_veccpu = curcpu(); 739 lwp0.l_md.md_fpucpu = curcpu(); 740 { 741 extern void *proc0paddr; 742 lwp0.l_addr = proc0paddr; 743 } 744 lwp0.l_md.md_utf = trapframe(&lwp0); 745 746 /* 747 * Set some more MD helpers 748 */ 749 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 750 cpu_md_ops.md_device_register = e500_device_register; 751 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 752 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 753 #if NGPIO > 0 754 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 755 #endif 756 757 #if NKSYMS || defined(DDB) || defined(LKM) 758 { 759 extern void *startsym, *endsym; 760 ksyms_init((int)((u_int)endsym - (u_int)startsym), 761 startsym, endsym); 762 } 763 #endif 764 765 printf(" initppc done!\n"); 766 } 767 768 #ifdef MPC8548 769 static const char * const mpc8548cds_extirq_names[] = { 770 [0] = "pci inta", 771 [1] = "pci intb", 772 [2] = "pci intc", 773 [3] = "pci intd", 774 [4] = "irq4", 775 [5] = "gige phy", 776 [6] = "atm phy", 777 [7] = "cpld", 778 [8] = "irq8", 779 [9] = "nvram", 780 [10] = "debug", 781 [11] = "pci2 inta", 782 }; 783 #endif 784 785 static const char * const mpc85xx_extirq_names[] = { 786 [0] = "extirq 0", 787 [1] = "extirq 1", 788 [2] = "extirq 2", 789 [3] = "extirq 3", 790 [4] = "extirq 4", 791 [5] = "extirq 5", 792 [6] = "extirq 6", 793 [7] = "extirq 7", 794 [8] = "extirq 8", 795 [9] = "extirq 9", 796 [10] = "extirq 10", 797 [11] = "extirq 11", 798 }; 799 800 static void 801 mpc85xx_extirq_setup(void) 802 { 803 #ifdef MPC8548 804 const char * const * names = mpc8548cds_extirq_names; 805 const size_t n = __arraycount(mpc8548cds_extirq_names); 806 #else 807 const char * const * names = mpc85xx_extirq_names; 808 const size_t n = __arraycount(mpc85xx_extirq_names); 809 #endif 810 prop_array_t extirqs = prop_array_create_with_capacity(n); 811 for (u_int i = 0; i < n; i++) { 812 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 813 prop_array_set(extirqs, i, ps); 814 prop_object_release(ps); 815 } 816 board_info_add_object("external-irqs", extirqs); 817 prop_object_release(extirqs); 818 } 819 820 static void 821 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 822 { 823 prop_dictionary_t pci_intmap = prop_dictionary_create(); 824 KASSERT(pci_intmap != NULL); 825 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 826 KASSERT(mask != NULL); 827 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 828 prop_object_release(mask); 829 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 830 KASSERT(pn_ist != NULL); 831 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 832 KASSERT(pn_intr != NULL); 833 prop_dictionary_t entry = prop_dictionary_create(); 834 KASSERT(entry != NULL); 835 prop_dictionary_set(entry, "interrupt", pn_intr); 836 prop_dictionary_set(entry, "type", pn_ist); 837 prop_dictionary_set(pci_intmap, "000000", entry); 838 prop_object_release(pn_intr); 839 prop_object_release(entry); 840 va_list ap; 841 va_start(ap, inta); 842 u_int intrinc = __LOWEST_SET_BIT(intmask); 843 for (u_int i = 0; i < intmask; i += intrinc) { 844 char prop_name[12]; 845 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 846 entry = prop_dictionary_create(); 847 KASSERT(entry != NULL); 848 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 849 KASSERT(pn_intr != NULL); 850 prop_dictionary_set(entry, "interrupt", pn_intr); 851 prop_dictionary_set(entry, "type", pn_ist); 852 prop_dictionary_set(pci_intmap, prop_name, entry); 853 prop_object_release(pn_intr); 854 prop_object_release(entry); 855 } 856 va_end(ap); 857 prop_object_release(pn_ist); 858 board_info_add_object(name, pci_intmap); 859 prop_object_release(pci_intmap); 860 } 861 862 void 863 cpu_startup(void) 864 { 865 struct cpu_info * const ci = curcpu(); 866 867 booke_cpu_startup(socname(mfspr(SPR_SVR))); 868 869 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 870 uint32_t plat_ratio = PLAT_RATIO_GET(v); 871 uint32_t e500_ratio = E500_RATIO_GET(v); 872 873 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 874 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 875 876 ci->ci_khz = (cpu_freq + 500) / 1000; 877 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 878 879 board_info_add_bool("pq3"); 880 board_info_add_number("mem-size", pmemsize); 881 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 882 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 883 uint32_t l2banks = l2siz >> 16; 884 #ifdef MPC85555 885 if (e500_get_svr() == (MPC8555v1 >> 16)) { 886 l2siz >>= 1; 887 l2banks >>= 1; 888 } 889 #endif 890 board_info_add_number("l2-cache-size", l2siz); 891 board_info_add_number("l2-cache-line-size", 32); 892 board_info_add_number("l2-cache-banks", l2banks); 893 board_info_add_number("l2-cache-ways", 8); 894 895 board_info_add_number("processor-frequency", cpu_freq); 896 board_info_add_number("bus-frequency", ccb_freq); 897 board_info_add_number("pci-frequency", e500_sys_clk); 898 board_info_add_number("timebase-frequency", ccb_freq / 8); 899 900 #ifdef CADMUS 901 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 902 board_info_add_number("tsec1-phy-addr", phy_base + 0); 903 board_info_add_number("tsec2-phy-addr", phy_base + 1); 904 board_info_add_number("tsec3-phy-addr", phy_base + 2); 905 board_info_add_number("tsec4-phy-addr", phy_base + 3); 906 #elif defined(PIXIS) 907 board_info_add_number("tsec1-phy-addr", 1); 908 board_info_add_number("tsec2-phy-addr", 0); 909 #else 910 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 911 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 912 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 913 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 914 #endif 915 916 uint64_t macstnaddr = 917 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 918 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 919 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 920 921 #if NPCI > 0 && defined(PCI_MEMBASE) 922 pcimem_ex = extent_create("pcimem", 923 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 924 M_DEVBUF, NULL, 0, EX_WAITOK); 925 #endif 926 #if NPCI > 0 && defined(PCI_IOBASE) 927 pciio_ex = extent_create("pciio", 928 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 929 M_DEVBUF, NULL, 0, EX_WAITOK); 930 #endif 931 mpc85xx_extirq_setup(); 932 /* 933 * PCI-Express virtual wire interrupts on combined with 934 * External IRQ0/1/2/3. 935 */ 936 #if defined(MPC8548) 937 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 938 #endif 939 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) 940 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 941 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 4, 5, 6, 7); 942 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 8, 9, 10, 11); 943 #endif 944 #if defined(MPC8544) || defined(MPC8548) 945 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 946 #endif 947 #if defined(MPC8536) 948 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1, 2, 3, 4); 949 #endif 950 #if defined(MPC8548) 951 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 11, 1, 2, 3); 952 #endif 953 } 954
Indexes created Sun Oct 19 02:09:48 GMT 2025