machdep.c revision 1.1.2.4
1 /* $NetBSD: machdep.c,v 1.1.2.4 2011/08/02 01:34:36 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/ksyms.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <machine/stdarg.h> 70 #include <powerpc/pcb.h> 71 72 #include <dev/cons.h> 73 74 #include <dev/ic/comreg.h> 75 #include <dev/ic/comvar.h> 76 77 #include <net/if.h> 78 #include <net/if_media.h> 79 #include <dev/mii/miivar.h> 80 81 #include <powerpc/spr.h> 82 #include <powerpc/booke/spr.h> 83 84 #include <powerpc/booke/cpuvar.h> 85 #include <powerpc/booke/e500reg.h> 86 #include <powerpc/booke/e500var.h> 87 #include <powerpc/booke/etsecreg.h> 88 #include <powerpc/booke/openpicreg.h> 89 #ifdef CADMUS 90 #include <evbppc/mpc85xx/cadmusreg.h> 91 #endif 92 #ifdef PIXIS 93 #include <evbppc/mpc85xx/pixisreg.h> 94 #endif 95 96 #include "ksyms.h" 97 98 void initppc(vaddr_t, vaddr_t); 99 100 #define MEMREGIONS 4 101 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 102 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 103 static u_int nmemr; 104 105 #ifndef CONSFREQ 106 # define CONSFREQ -1 /* inherit from firmware */ 107 #endif 108 #ifndef CONSPEED 109 # define CONSPEED 115200 110 #endif 111 #ifndef CONMODE 112 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 113 #endif 114 #ifndef CONSADDR 115 # define CONSADDR DUART2_BASE 116 #endif 117 118 int comcnfreq = CONSFREQ; 119 int comcnspeed = CONSPEED; 120 tcflag_t comcnmode = CONMODE; 121 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 122 123 #if NPCI > 0 124 struct extent *pcimem_ex; 125 struct extent *pciio_ex; 126 #endif 127 128 struct powerpc_bus_space gur_bst = { 129 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 130 .pbs_offset = GUR_BASE, 131 .pbs_limit = GUR_SIZE, 132 }; 133 134 struct powerpc_bus_space gur_le_bst = { 135 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 136 .pbs_offset = GUR_BASE, 137 .pbs_limit = GUR_SIZE, 138 }; 139 140 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 141 142 #ifdef CADMUS 143 static uint8_t cadmus_pci; 144 static uint8_t cadmus_csr; 145 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 146 #elif defined(PIXIS) 147 static const uint32_t pixis_spd_map[8] = { 148 [PX_SPD_33MHZ] = 33333333, 149 [PX_SPD_40MHZ] = 40000000, 150 [PX_SPD_50MHZ] = 50000000, 151 [PX_SPD_66MHZ] = 66666666, 152 [PX_SPD_83MHZ] = 83333333, 153 [PX_SPD_100MHZ] = 100000000, 154 [PX_SPD_133MHZ] = 133333333, 155 [PX_SPD_166MHZ] = 166666667, 156 }; 157 static uint8_t pixis_spd; 158 static uint64_t e500_sys_clk; 159 #elif defined(SYS_CLK) 160 static uint64_t e500_sys_clk = SYS_CLK; /* from config file */ 161 #else 162 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 163 #endif 164 165 static int e500_cngetc(dev_t); 166 static void e500_cnputc(dev_t, int); 167 168 static struct consdev e500_earlycons = { 169 .cn_getc = e500_cngetc, 170 .cn_putc = e500_cnputc, 171 .cn_pollc = nullcnpollc, 172 }; 173 174 /* 175 * List of port-specific devices to attach to the processor local bus. 176 */ 177 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 178 { "cpu" }, /* not a real device */ 179 { "wdog" }, /* not a real device */ 180 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 1, 181 { ISOURCE_DUART }, 182 1 + ilog2(DEVDISR_DUART) }, 183 #if defined(MPC8548) || defined(MPC8572) 184 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 3, 185 { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 186 1 + ilog2(DEVDISR_TSEC1) }, 187 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 3, 188 { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 189 1 + ilog2(DEVDISR_TSEC2) }, 190 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 3, 191 { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 192 1 + ilog2(DEVDISR_TSEC3) }, 193 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 3, 194 { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 195 1 + ilog2(DEVDISR_TSEC4) }, 196 #endif 197 #if defined(MPC8544) || defined(MPC8536) 198 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 3, 199 { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 200 1 + ilog2(DEVDISR_TSEC1) }, 201 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 3, 202 { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 203 1 + ilog2(DEVDISR_TSEC2) }, 204 #endif 205 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 1, 206 { ISOURCE_I2C }, 207 1 + ilog2(DEVDISR_TSEC2) }, 208 #ifndef MPC8572 209 /* MPC8572 doesn't have any GPIO */ 210 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 0 }, 211 #endif 212 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 1, 213 { ISOURCE_DDR }, 214 1 + ilog2(DEVDISR_TSEC2) }, 215 #if defined(MPC8544) || defined(MPC8536) 216 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 1, 217 { ISOURCE_PCIEX }, 218 1 + ilog2(DEVDISR_PCIE) }, 219 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 1, 220 { ISOURCE_PCIEX2 }, 221 1 + ilog2(DEVDISR_PCIE3) }, 222 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 1, 223 { ISOURCE_PCIEX3 }, 224 1 + ilog2(DEVDISR_PCIE2) }, 225 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 1, 1, 226 { ISOURCE_PCI1 }, 227 1 + ilog2(DEVDISR_PCI1) }, 228 #endif 229 #ifdef MPC8548 230 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 1, 231 { ISOURCE_PCIEX }, 232 1 + ilog2(DEVDISR_PCIE) }, 233 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 1, 234 { ISOURCE_PCI1 }, 235 1 + ilog2(DEVDISR_PCI1) }, 236 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 1, 237 { ISOURCE_PCI2 }, 238 1 + ilog2(DEVDISR_PCI2) }, 239 #endif 240 #ifdef MPC8536 241 { "ehci", USB1_BASE, USB_SIZE, 1, 1, 242 { ISOURCE_USB1 }, 243 1 + ilog2(DEVDISR_USB1) }, 244 { "ehci", USB2_BASE, USB_SIZE, 2, 1, 245 { ISOURCE_USB2 }, 246 1 + ilog2(DEVDISR_USB2) }, 247 { "ehci", USB3_BASE, USB_SIZE, 3, 1, 248 { ISOURCE_USB3 }, 249 1 + ilog2(DEVDISR_USB3) }, 250 { "sata", SATA1_BASE, SATA_SIZE, 1, 1, 251 { ISOURCE_SATA1 }, 252 1 + ilog2(DEVDISR_SATA1) }, 253 { "sata", SATA2_BASE, SATA_SIZE, 2, 1, 254 { ISOURCE_SATA2 }, 255 1 + ilog2(DEVDISR_SATA2) }, 256 { "spi", SPI_BASE, SPI_SIZE, 0, 1, 257 { ISOURCE_SPI }, 258 1 + ilog2(DEVDISR_SPI) }, 259 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 1, 260 { ISOURCE_ESDHC }, 261 1 + ilog2(DEVDISR_ESDHC) }, 262 #endif 263 { "lbc", LBC_BASE, LBC_SIZE, 0, 1, 264 { ISOURCE_LBC }, 265 1 + ilog2(DEVDISR_LBC) }, 266 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 267 { NULL } 268 }; 269 270 static int 271 e500_cngetc(dev_t dv) 272 { 273 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 274 275 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 276 return -1; 277 278 return com0addr[com_data] & 0xff; 279 } 280 281 static void 282 e500_cnputc(dev_t dv, int c) 283 { 284 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 285 int timo = 150000; 286 287 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 288 ; 289 290 com0addr[com_data] = c; 291 __asm("mbar"); 292 293 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 294 ; 295 } 296 297 static void * 298 gur_tlb_mapiodev(paddr_t pa, psize_t len) 299 { 300 if (pa < gur_bst.pbs_offset) 301 return NULL; 302 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 303 return NULL; 304 return (void *)pa; 305 } 306 307 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 308 309 static void 310 e500_cpu_reset(void) 311 { 312 __asm volatile("sync"); 313 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 314 __asm volatile("msync;isync"); 315 } 316 317 static psize_t 318 memprobe(vaddr_t endkernel) 319 { 320 phys_ram_seg_t *mr; 321 322 /* 323 * First we need to find out how much physical memory we have. 324 * We could let our bootloader tell us, but it's almost as easy 325 * to ask the DDR memory controller. 326 */ 327 mr = physmemr; 328 #if 1 329 for (u_int i = 0; i < 4; i++) { 330 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 331 if (v & CS_CONFIG_EN) { 332 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 333 mr->start = BNDS_SA_GET(v); 334 mr->size = BNDS_SIZE_GET(v); 335 mr++; 336 } 337 } 338 339 if (mr == physmemr) 340 panic("no memory configured!"); 341 #else 342 mr->start = 0; 343 mr->size = 32 << 20; 344 mr++; 345 #endif 346 347 /* 348 * Sort memory regions from low to high and coalesce adjacent regions 349 */ 350 u_int cnt = mr - physmemr; 351 if (cnt > 1) { 352 for (u_int i = 0; i < cnt - 1; i++) { 353 for (u_int j = i + 1; j < cnt; j++) { 354 if (physmemr[j].start < physmemr[i].start) { 355 phys_ram_seg_t tmp = physmemr[i]; 356 physmemr[i] = physmemr[j]; 357 physmemr[j] = tmp; 358 } 359 } 360 } 361 mr = physmemr; 362 for (u_int i = 0; i < cnt; i++, mr++) { 363 if (mr->start + mr->size == mr[1].start) { 364 mr->size += mr[1].size; 365 for (u_int j = 1; j < cnt - i; j++) 366 mr[j] = mr[j+1]; 367 cnt--; 368 } 369 } 370 } 371 372 /* 373 * Copy physical memory to available memory. 374 */ 375 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 376 377 /* 378 * Adjust available memory to skip kernel at start of memory. 379 */ 380 availmemr[0].size -= endkernel - availmemr[0].start; 381 availmemr[0].start = endkernel; 382 383 /* 384 * Steal pages at the end of memory for the kernel message buffer. 385 */ 386 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 387 msgbuf_paddr = 388 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 389 390 /* 391 * Calculate physmem. 392 */ 393 for (u_int i = 0; i < cnt; i++) 394 physmem += atop(physmemr[i].size); 395 396 nmemr = cnt; 397 return physmemr[cnt-1].start + physmemr[cnt-1].size; 398 } 399 400 void 401 consinit(void) 402 { 403 static bool attached = false; 404 405 if (attached) 406 return; 407 attached = true; 408 409 if (comcnfreq == -1) { 410 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 411 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 412 comcnfreq = e500_sys_clk * plat_ratio; 413 printf(" comcnfreq=%u", comcnfreq); 414 } 415 416 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 417 COM_TYPE_NORMAL, comcnmode); 418 } 419 420 void 421 cpu_probe_cache(void) 422 { 423 struct cpu_info * const ci = curcpu(); 424 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 425 426 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 427 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 428 429 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 430 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 431 432 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 433 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 434 } else { 435 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 436 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 437 } 438 439 #ifdef DEBUG 440 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 441 if ((L1CSR_CE & l1csr0) == 0) 442 printf(" DC=off"); 443 444 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 445 if ((L1CSR_CE & l1csr1) == 0) 446 printf(" IC=off"); 447 #endif 448 } 449 450 static const char * 451 socname(uint32_t svr) 452 { 453 svr &= ~0x80000; 454 switch (svr >> 8) { 455 case SVR_MPC8548v2 >> 8: return "MPC8548"; 456 case SVR_MPC8547v2 >> 8: return "MPC8547"; 457 case SVR_MPC8545v2 >> 8: return "MPC8545"; 458 case SVR_MPC8543v2 >> 8: return "MPC8543"; 459 case SVR_MPC8544v1 >> 8: return "MPC8544"; 460 case SVR_MPC8536v1 >> 8: return "MPC8536"; 461 case SVR_MPC8572 >> 8: return "MPC8572"; 462 default: 463 panic("%s: unknown SVR %#x", __func__, svr); 464 } 465 } 466 467 static void 468 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 469 { 470 static const char units[16] = "KKKKKMMMMMGGGGGT"; 471 472 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 473 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 474 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 475 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 476 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 477 478 aprint_normal_dev(self, "%s:", name); 479 480 aprint_normal(" %u", nentries); 481 if (TLBCFG_AVAIL_P(tlbcfg)) { 482 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 483 minsize, maxsize, units[maxsize_log4k]); 484 } else { 485 aprint_normal(" fixed-size (%uKB)", minsize); 486 } 487 if (assoc == 0 || assoc == nentries) 488 aprint_normal(" fully"); 489 else 490 aprint_normal(" %u-way set", assoc); 491 aprint_normal(" associative entries\n"); 492 } 493 494 static void 495 e500_cpu_attach(device_t self, u_int instance) 496 { 497 struct cpu_info * const ci = &cpu_info[instance]; 498 499 KASSERT(instance == 0); 500 self->dv_private = ci; 501 502 ci->ci_cpuid = instance; 503 ci->ci_dev = self; 504 //ci->ci_idlespin = cpu_idlespin; 505 if (instance > 0) { 506 ci->ci_idepth = -1; 507 cpu_probe_cache(); 508 } 509 510 uint64_t freq = board_info_get_number("processor-frequency"); 511 char freqbuf[10]; 512 if (freq >= 999500000) { 513 const uint32_t freq32 = (freq + 500000) / 10000000; 514 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 515 freq32 / 100, freq32 % 100); 516 } else { 517 const uint32_t freq32 = (freq + 500000) / 1000000; 518 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 519 } 520 521 const uint32_t pvr = mfpvr(); 522 const uint32_t svr = mfspr(SPR_SVR); 523 const uint32_t pir = mfspr(SPR_PIR); 524 525 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 526 "ID %u%s\n", 527 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 528 (svr >> 4) & 15, svr & 15, 529 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 530 (pvr >> 4) & 15, pvr & 15, 531 pir, (pir == 0 ? " (Primary)" : "")); 532 533 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 534 aprint_normal_dev(self, 535 "%uKB/%uB %u-way L1 %s cache\n", 536 L1CFG_CSIZE_GET(l1cfg0) >> 10, 537 32 << L1CFG_CBSIZE_GET(l1cfg0), 538 L1CFG_CNWAY_GET(l1cfg0), 539 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 540 ? "data" : "unified"); 541 542 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 543 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 544 aprint_normal_dev(self, 545 "%uKB/%uB %u-way L1 %s cache\n", 546 L1CFG_CSIZE_GET(l1cfg1) >> 10, 547 32 << L1CFG_CBSIZE_GET(l1cfg1), 548 L1CFG_CNWAY_GET(l1cfg1), 549 "instruction"); 550 } 551 552 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 553 aprint_normal_dev(self, 554 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 555 MMUCFG_NTLBS_GET(mmucfg) + 1, 556 MMUCFG_NPIDS_GET(mmucfg), 557 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 558 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 559 560 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 561 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 562 563 intr_cpu_init(ci); 564 cpu_evcnt_attach(ci); 565 } 566 567 static void 568 calltozero(void) 569 { 570 panic("call to 0 from %p", __builtin_return_address(0)); 571 } 572 573 void 574 initppc(vaddr_t startkernel, vaddr_t endkernel) 575 { 576 struct cpu_info * const ci = curcpu(); 577 struct cpu_softc * const cpu = ci->ci_softc; 578 579 cn_tab = &e500_earlycons; 580 printf(" initppc<enter>"); 581 582 const register_t hid0 = mfspr(SPR_HID0); 583 mtspr(SPR_HID0, hid0 | HID0_TBEN | HID0_EMCP); 584 #ifdef CADMUS 585 /* 586 * Need to cache this from cadmus since we need to unmap cadmus since 587 * it falls in the middle of kernel address space. 588 */ 589 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 590 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 591 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 592 printf(" cadmus_pci=%#x", cadmus_pci); 593 printf(" cadmus_csr=%#x", cadmus_csr); 594 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 595 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 596 e500_sys_clk *= 2; 597 } 598 #endif 599 #ifdef PIXIS 600 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 601 printf(" pixis_spd=%#x ", pixis_spd); 602 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 603 #endif 604 printf(" porpllsr=0x%08x", 605 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 606 printf(" sys_clk=%"PRIu64, e500_sys_clk); 607 608 /* 609 * Make sure arguments are page aligned. 610 */ 611 startkernel = trunc_page(startkernel); 612 endkernel = round_page(endkernel); 613 614 /* 615 * Initialize the bus space tag used to access the 85xx general 616 * utility registers. It doesn't need to be extent protected. 617 * We know the GUR is mapped via a TLB1 entry so we add a limited 618 * mapiodev which allows mappings in GUR space. 619 */ 620 CTASSERT(offsetof(struct tlb_md_ops, md_tlb_mapiodev) == 0); 621 cpu_md_ops.md_tlb_ops = (const void *)&early_tlb_mapiodev; 622 bus_space_init(&gur_bst, NULL, NULL, 0); 623 bus_space_init(&gur_le_bst, NULL, NULL, 0); 624 cpu->cpu_bst = &gur_bst; 625 cpu->cpu_le_bst = &gur_le_bst; 626 cpu->cpu_bsh = gur_bsh; 627 628 /* 629 * Attach the console early, really early. 630 */ 631 consinit(); 632 633 /* 634 * Reset the PIC to a known state. 635 */ 636 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 637 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 638 ; 639 #if 0 640 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 641 #endif 642 printf(" openpic-reset(ctpr=%u)", 643 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 644 645 /* 646 * fill in with an absolute branch to a routine that will panic. 647 */ 648 *(int *)0 = 0x48000002 | (int) calltozero; 649 650 /* 651 * Get the cache sizes. 652 */ 653 cpu_probe_cache(); 654 printf(" cache(DC=%u/%u,IC=%u/%u)", 655 ci->ci_ci.dcache_size >> 10, 656 ci->ci_ci.dcache_line_size, 657 ci->ci_ci.icache_size >> 10, 658 ci->ci_ci.icache_line_size); 659 660 /* 661 * Now find out how much memory is attached 662 */ 663 pmemsize = memprobe(endkernel); 664 cpu->cpu_highmem = pmemsize; 665 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 666 667 /* 668 * Now we need cleanout the TLB of stuff that we don't need. 669 */ 670 e500_tlb_init(endkernel, pmemsize); 671 printf(" e500_tlbinit(%#lx,%zuMB)", 672 endkernel, (size_t) (pmemsize >> 20)); 673 674 /* 675 * 676 */ 677 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 678 printf(" hid1=%#lx", mfspr(SPR_HID1)); 679 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 680 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 681 682 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 683 684 /* 685 * Initialize the message buffer. 686 */ 687 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 688 printf(" msgbuf=%p", (void *)msgbuf_paddr); 689 690 /* 691 * Initialize exception vectors and interrupts 692 */ 693 exception_init(&e500_intrsw); 694 printf(" exception_init=%p", &e500_intrsw); 695 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 696 697 /* 698 * Set the page size. 699 */ 700 uvm_setpagesize(); 701 702 /* 703 * Initialize the pmap. 704 */ 705 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 706 707 /* 708 * Let's take all the indirect calls via our stubs and patch 709 * them to be direct calls. 710 */ 711 booke_fixup_stubs(); 712 #if 0 713 /* 714 * As a debug measure we can change the TLB entry that maps all of 715 * memory to one that encompasses the 64KB with the kernel vectors. 716 * All other pages will be soft faulted into the TLB as needed. 717 */ 718 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 719 mtspr(SPR_MAS6, 0); 720 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 721 uint32_t mas0 = mfspr(SPR_MAS0); 722 uint32_t mas1 = mfspr(SPR_MAS1); 723 uint32_t mas2 = mfspr(SPR_MAS2); 724 uint32_t mas3 = mfspr(SPR_MAS3); 725 KASSERT(mas3 & MAS3_SW); 726 KASSERT(mas3 & MAS3_SR); 727 KASSERT(mas3 & MAS3_SX); 728 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 729 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 730 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 731 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 732 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 733 #if 1 734 mtspr(SPR_MAS1, mas1); 735 mtspr(SPR_MAS2, mas2); 736 mtspr(SPR_MAS3, mas3); 737 extern void tlbwe(void); 738 tlbwe(); 739 mtspr(SPR_MAS0, saved_mas0); 740 printf("(ok)"); 741 #endif 742 #endif 743 744 /* 745 * Initialize a few things in lwp0. 746 */ 747 lwp0.l_md.md_veccpu = curcpu(); 748 lwp0.l_md.md_fpucpu = curcpu(); 749 { 750 extern void *proc0paddr; 751 lwp0.l_addr = proc0paddr; 752 } 753 lwp0.l_md.md_utf = trapframe(&lwp0); 754 755 /* 756 * Set some more MD helpers 757 */ 758 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 759 cpu_md_ops.md_device_register = e500_device_register; 760 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 761 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 762 #if NGPIO > 0 763 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 764 #endif 765 766 #if NKSYMS || defined(DDB) || defined(LKM) 767 { 768 extern void *startsym, *endsym; 769 ksyms_init((int)((u_int)endsym - (u_int)startsym), 770 startsym, endsym); 771 } 772 #endif 773 774 printf(" initppc done!\n"); 775 } 776 777 #ifdef MPC8548 778 static const char * const mpc8548cds_extirq_names[] = { 779 [0] = "pci inta", 780 [1] = "pci intb", 781 [2] = "pci intc", 782 [3] = "pci intd", 783 [4] = "irq4", 784 [5] = "gige phy", 785 [6] = "atm phy", 786 [7] = "cpld", 787 [8] = "irq8", 788 [9] = "nvram", 789 [10] = "debug", 790 [11] = "pci2 inta", 791 }; 792 #endif 793 794 static const char * const mpc85xx_extirq_names[] = { 795 [0] = "extirq 0", 796 [1] = "extirq 1", 797 [2] = "extirq 2", 798 [3] = "extirq 3", 799 [4] = "extirq 4", 800 [5] = "extirq 5", 801 [6] = "extirq 6", 802 [7] = "extirq 7", 803 [8] = "extirq 8", 804 [9] = "extirq 9", 805 [10] = "extirq 10", 806 [11] = "extirq 11", 807 }; 808 809 static void 810 mpc85xx_extirq_setup(void) 811 { 812 #ifdef MPC8548 813 const char * const * names = mpc8548cds_extirq_names; 814 const size_t n = __arraycount(mpc8548cds_extirq_names); 815 #else 816 const char * const * names = mpc85xx_extirq_names; 817 const size_t n = __arraycount(mpc85xx_extirq_names); 818 #endif 819 prop_array_t extirqs = prop_array_create_with_capacity(n); 820 for (u_int i = 0; i < n; i++) { 821 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 822 prop_array_set(extirqs, i, ps); 823 prop_object_release(ps); 824 } 825 board_info_add_object("external-irqs", extirqs); 826 prop_object_release(extirqs); 827 } 828 829 static void 830 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 831 { 832 prop_dictionary_t pci_intmap = prop_dictionary_create(); 833 KASSERT(pci_intmap != NULL); 834 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 835 KASSERT(mask != NULL); 836 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 837 prop_object_release(mask); 838 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 839 KASSERT(pn_ist != NULL); 840 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 841 KASSERT(pn_intr != NULL); 842 prop_dictionary_t entry = prop_dictionary_create(); 843 KASSERT(entry != NULL); 844 prop_dictionary_set(entry, "interrupt", pn_intr); 845 prop_dictionary_set(entry, "type", pn_ist); 846 prop_dictionary_set(pci_intmap, "000000", entry); 847 prop_object_release(pn_intr); 848 prop_object_release(entry); 849 va_list ap; 850 va_start(ap, inta); 851 u_int intrinc = __LOWEST_SET_BIT(intmask); 852 for (u_int i = 0; i < intmask; i += intrinc) { 853 char prop_name[12]; 854 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 855 entry = prop_dictionary_create(); 856 KASSERT(entry != NULL); 857 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 858 KASSERT(pn_intr != NULL); 859 prop_dictionary_set(entry, "interrupt", pn_intr); 860 prop_dictionary_set(entry, "type", pn_ist); 861 prop_dictionary_set(pci_intmap, prop_name, entry); 862 prop_object_release(pn_intr); 863 prop_object_release(entry); 864 } 865 va_end(ap); 866 prop_object_release(pn_ist); 867 board_info_add_object(name, pci_intmap); 868 prop_object_release(pci_intmap); 869 } 870 871 void 872 cpu_startup(void) 873 { 874 struct cpu_info * const ci = curcpu(); 875 876 booke_cpu_startup(socname(mfspr(SPR_SVR))); 877 878 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 879 uint32_t plat_ratio = PLAT_RATIO_GET(v); 880 uint32_t e500_ratio = E500_RATIO_GET(v); 881 882 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 883 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 884 885 ci->ci_khz = (cpu_freq + 500) / 1000; 886 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 887 888 board_info_add_bool("pq3"); 889 board_info_add_number("mem-size", pmemsize); 890 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 891 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 892 uint32_t l2banks = l2siz >> 16; 893 #ifdef MPC85555 894 if (e500_get_svr() == (MPC8555v1 >> 16)) { 895 l2siz >>= 1; 896 l2banks >>= 1; 897 } 898 #endif 899 board_info_add_number("l2-cache-size", l2siz); 900 board_info_add_number("l2-cache-line-size", 32); 901 board_info_add_number("l2-cache-banks", l2banks); 902 board_info_add_number("l2-cache-ways", 8); 903 904 board_info_add_number("processor-frequency", cpu_freq); 905 board_info_add_number("bus-frequency", ccb_freq); 906 board_info_add_number("pci-frequency", e500_sys_clk); 907 board_info_add_number("timebase-frequency", ccb_freq / 8); 908 909 #ifdef CADMUS 910 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 911 board_info_add_number("tsec1-phy-addr", phy_base + 0); 912 board_info_add_number("tsec2-phy-addr", phy_base + 1); 913 board_info_add_number("tsec3-phy-addr", phy_base + 2); 914 board_info_add_number("tsec4-phy-addr", phy_base + 3); 915 #elif defined(PIXIS) 916 board_info_add_number("tsec1-phy-addr", 1); 917 board_info_add_number("tsec2-phy-addr", 0); 918 #else 919 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 920 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 921 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 922 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 923 #endif 924 925 uint64_t macstnaddr = 926 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 927 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 928 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 929 930 #if NPCI > 0 && defined(PCI_MEMBASE) 931 pcimem_ex = extent_create("pcimem", 932 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 933 M_DEVBUF, NULL, 0, EX_WAITOK); 934 #endif 935 #if NPCI > 0 && defined(PCI_IOBASE) 936 pciio_ex = extent_create("pciio", 937 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 938 M_DEVBUF, NULL, 0, EX_WAITOK); 939 #endif 940 mpc85xx_extirq_setup(); 941 /* 942 * PCI-Express virtual wire interrupts on combined with 943 * External IRQ0/1/2/3. 944 */ 945 #if defined(MPC8548) 946 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 947 #endif 948 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) 949 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 950 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 4, 5, 6, 7); 951 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 8, 9, 10, 11); 952 #endif 953 #if defined(MPC8544) || defined(MPC8548) 954 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 955 #endif 956 #if defined(MPC8536) 957 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1, 2, 3, 4); 958 #endif 959 #if defined(MPC8548) 960 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 11, 1, 2, 3); 961 #endif 962 } 963
Indexes created Sun Oct 19 16:10:00 GMT 2025