machdep.c revision 1.11
1 /* $NetBSD: machdep.c,v 1.11 2011/06/15 15:18:20 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <machine/stdarg.h> 70 71 #include <dev/cons.h> 72 73 #include <dev/ic/comreg.h> 74 #include <dev/ic/comvar.h> 75 76 #include <net/if.h> 77 #include <net/if_media.h> 78 #include <dev/mii/miivar.h> 79 80 #include <powerpc/pcb.h> 81 #include <powerpc/spr.h> 82 #include <powerpc/booke/spr.h> 83 84 #include <powerpc/booke/cpuvar.h> 85 #include <powerpc/booke/e500reg.h> 86 #include <powerpc/booke/e500var.h> 87 #include <powerpc/booke/etsecreg.h> 88 #include <powerpc/booke/openpicreg.h> 89 #ifdef CADMUS 90 #include <evbppc/mpc85xx/cadmusreg.h> 91 #endif 92 #ifdef PIXIS 93 #include <evbppc/mpc85xx/pixisreg.h> 94 #endif 95 96 struct uboot_bdinfo { 97 uint32_t bd_memstart; 98 uint32_t bd_memsize; 99 uint32_t bd_flashstart; 100 uint32_t bd_flashsize; 101 /*10*/ uint32_t bd_flashoffset; 102 uint32_t bd_sramstart; 103 uint32_t bd_sramsize; 104 uint32_t bd_immrbase; 105 /*20*/ uint32_t bd_bootflags; 106 uint32_t bd_ipaddr; 107 uint8_t bd_etheraddr[6]; 108 uint16_t bd_ethspeed; 109 /*30*/ uint32_t bd_intfreq; 110 uint32_t bd_cpufreq; 111 uint32_t bd_baudrate; 112 /*3c*/ uint8_t bd_etheraddr1[6]; 113 /*42*/ uint8_t bd_etheraddr2[6]; 114 /*48*/ uint8_t bd_etheraddr3[6]; 115 /*4e*/ uint16_t bd_pad; 116 }; 117 118 /* 119 * booke kernels need to set module_machine to this for modules to work. 120 */ 121 char module_machine_booke[] = "powerpc-booke"; 122 123 void initppc(vaddr_t, vaddr_t, void *, void *, void *, void *); 124 125 #define MEMREGIONS 4 126 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 127 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 128 static u_int nmemr; 129 130 #ifndef CONSFREQ 131 # define CONSFREQ -1 /* inherit from firmware */ 132 #endif 133 #ifndef CONSPEED 134 # define CONSPEED 115200 135 #endif 136 #ifndef CONMODE 137 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 138 #endif 139 #ifndef CONSADDR 140 # define CONSADDR DUART2_BASE 141 #endif 142 143 int comcnfreq = CONSFREQ; 144 int comcnspeed = CONSPEED; 145 tcflag_t comcnmode = CONMODE; 146 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 147 148 #if NPCI > 0 149 struct extent *pcimem_ex; 150 struct extent *pciio_ex; 151 #endif 152 153 struct powerpc_bus_space gur_bst = { 154 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 155 .pbs_offset = GUR_BASE, 156 .pbs_limit = GUR_SIZE, 157 }; 158 159 struct powerpc_bus_space gur_le_bst = { 160 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 161 .pbs_offset = GUR_BASE, 162 .pbs_limit = GUR_SIZE, 163 }; 164 165 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 166 167 #if defined(SYS_CLK) 168 static uint64_t e500_sys_clk = SYS_CLK; 169 #endif 170 #ifdef CADMUS 171 static uint8_t cadmus_pci; 172 static uint8_t cadmus_csr; 173 #ifndef SYS_CLK 174 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 175 #endif 176 #elif defined(PIXIS) 177 static const uint32_t pixis_spd_map[8] = { 178 [PX_SPD_33MHZ] = 33333333, 179 [PX_SPD_40MHZ] = 40000000, 180 [PX_SPD_50MHZ] = 50000000, 181 [PX_SPD_66MHZ] = 66666666, 182 [PX_SPD_83MHZ] = 83333333, 183 [PX_SPD_100MHZ] = 100000000, 184 [PX_SPD_133MHZ] = 133333333, 185 [PX_SPD_166MHZ] = 166666667, 186 }; 187 static uint8_t pixis_spd; 188 #ifndef SYS_CLK 189 static uint64_t e500_sys_clk; 190 #endif 191 #elif !defined(SYS_CLK) 192 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 193 #endif 194 195 static int e500_cngetc(dev_t); 196 static void e500_cnputc(dev_t, int); 197 198 static struct consdev e500_earlycons = { 199 .cn_getc = e500_cngetc, 200 .cn_putc = e500_cnputc, 201 .cn_pollc = nullcnpollc, 202 }; 203 204 /* 205 * List of port-specific devices to attach to the processor local bus. 206 */ 207 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 208 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 209 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 210 #if defined(MPC8572) || defined(P2020) 211 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 212 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 213 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 214 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 215 #endif 216 { "wdog" }, /* not a real device */ 217 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 218 1, { ISOURCE_DUART }, 219 1 + ilog2(DEVDISR_DUART) }, 220 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 221 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 222 1 + ilog2(DEVDISR_TSEC1) }, 223 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 224 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 225 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 226 1 + ilog2(DEVDISR_TSEC2), 227 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 228 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 229 #endif 230 #if defined(MPC8544) || defined(MPC8536) 231 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 232 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 233 1 + ilog2(DEVDISR_TSEC3), 234 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 235 #endif 236 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 237 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 238 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 239 1 + ilog2(DEVDISR_TSEC3), 240 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 241 SVR_P2020v2 >> 16 } }, 242 #endif 243 #if defined(MPC8548) || defined(MPC8572) 244 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 245 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 246 1 + ilog2(DEVDISR_TSEC4), 247 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 248 #endif 249 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 250 1, { ISOURCE_I2C }, 251 1 + ilog2(DEVDISR_I2C) }, 252 /* MPC8572 doesn't have any GPIO */ 253 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 254 1, { ISOURCE_GPIO }, 255 0, 256 { 0xffff, SVR_MPC8572v1 >> 16 } }, 257 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 258 1, { ISOURCE_DDR }, 259 1 + ilog2(DEVDISR_DDR_15), 260 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 261 #if defined(MPC8536) 262 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 263 1, { ISOURCE_DDR }, 264 1 + ilog2(DEVDISR_DDR_16), 265 { SVR_MPC8536v1 >> 16 } }, 266 #endif 267 #if defined(MPC8572) 268 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 269 1, { ISOURCE_DDR }, 270 1 + ilog2(DEVDISR_DDR_15), 271 { SVR_MPC8572v1 >> 16 } }, 272 { "ddrc", DDRC1_BASE, DDRC_SIZE, 2, 273 1, { ISOURCE_DDR }, 274 1 + ilog2(DEVDISR_DDR2_14), 275 { SVR_MPC8572v1 >> 16 } }, 276 #endif 277 { "lbc", LBC_BASE, LBC_SIZE, 0, 278 1, { ISOURCE_LBC }, 279 1 + ilog2(DEVDISR_LBC) }, 280 #if defined(MPC8544) || defined(MPC8536) 281 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 282 1, { ISOURCE_PCIEX }, 283 1 + ilog2(DEVDISR_PCIE), 284 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 285 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 286 1, { ISOURCE_PCIEX2 }, 287 1 + ilog2(DEVDISR_PCIE2), 288 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 289 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 290 1, { ISOURCE_PCIEX3 }, 291 1 + ilog2(DEVDISR_PCIE3), 292 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 293 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 294 1, { ISOURCE_PCI1 }, 295 1 + ilog2(DEVDISR_PCI1), 296 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 297 #endif 298 #ifdef MPC8548 299 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 300 1, { ISOURCE_PCIEX }, 301 1 + ilog2(DEVDISR_PCIE), 302 { SVR_MPC8548v1 >> 16 }, }, 303 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 304 1, { ISOURCE_PCI1 }, 305 1 + ilog2(DEVDISR_PCI1), 306 { SVR_MPC8548v1 >> 16 }, }, 307 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 308 1, { ISOURCE_PCI2 }, 309 1 + ilog2(DEVDISR_PCI2), 310 { SVR_MPC8548v1 >> 16 }, }, 311 #endif 312 #if defined(MPC8572) || defined(P2020) 313 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 314 1, { ISOURCE_PCIEX }, 315 1 + ilog2(DEVDISR_PCIE), 316 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 317 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 318 1, { ISOURCE_PCIEX2 }, 319 1 + ilog2(DEVDISR_PCIE2), 320 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 321 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 322 1, { ISOURCE_PCIEX3_MPC8572 }, 323 1 + ilog2(DEVDISR_PCIE3), 324 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 325 #endif 326 #if defined(MPC8536) || defined(P2020) 327 { "ehci", USB1_BASE, USB_SIZE, 1, 328 1, { ISOURCE_USB1 }, 329 1 + ilog2(DEVDISR_USB1), 330 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 331 #endif 332 #ifdef MPC8536 333 { "ehci", USB2_BASE, USB_SIZE, 2, 334 1, { ISOURCE_USB2 }, 335 1 + ilog2(DEVDISR_USB2), 336 { SVR_MPC8536v1 >> 16 }, }, 337 { "ehci", USB3_BASE, USB_SIZE, 3, 338 1, { ISOURCE_USB3 }, 339 1 + ilog2(DEVDISR_USB3), 340 { SVR_MPC8536v1 >> 16 }, }, 341 { "sata", SATA1_BASE, SATA_SIZE, 1, 342 1, { ISOURCE_SATA1 }, 343 1 + ilog2(DEVDISR_SATA1), 344 { SVR_MPC8536v1 >> 16 }, }, 345 { "sata", SATA2_BASE, SATA_SIZE, 2, 346 1, { ISOURCE_SATA2 }, 347 1 + ilog2(DEVDISR_SATA2), 348 { SVR_MPC8536v1 >> 16 }, }, 349 { "spi", SPI_BASE, SPI_SIZE, 0, 350 1, { ISOURCE_SPI }, 351 1 + ilog2(DEVDISR_SPI_15), 352 { SVR_MPC8536v1 >> 16 }, }, 353 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 354 1, { ISOURCE_ESDHC }, 355 1 + ilog2(DEVDISR_ESDHC_12), 356 { SVR_MPC8536v1 >> 16 }, }, 357 #endif 358 #if defined(P2020) 359 { "spi", SPI_BASE, SPI_SIZE, 0, 360 1, { ISOURCE_SPI }, 361 1 + ilog2(DEVDISR_SPI_28), 362 { SVR_P2020v2 >> 16 }, }, 363 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 364 1, { ISOURCE_ESDHC }, 365 1 + ilog2(DEVDISR_ESDHC_10), 366 { SVR_P2020v2 >> 16 }, }, 367 #endif 368 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 369 { NULL } 370 }; 371 372 static int 373 e500_cngetc(dev_t dv) 374 { 375 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 376 377 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 378 return -1; 379 380 return com0addr[com_data] & 0xff; 381 } 382 383 static void 384 e500_cnputc(dev_t dv, int c) 385 { 386 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 387 int timo = 150000; 388 389 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 390 ; 391 392 com0addr[com_data] = c; 393 __asm("mbar"); 394 395 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 396 ; 397 } 398 399 static void * 400 gur_tlb_mapiodev(paddr_t pa, psize_t len) 401 { 402 if (pa < gur_bst.pbs_offset) 403 return NULL; 404 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 405 return NULL; 406 return (void *)pa; 407 } 408 409 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 410 411 static void 412 e500_cpu_reset(void) 413 { 414 __asm volatile("sync"); 415 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 416 __asm volatile("msync;isync"); 417 } 418 419 static psize_t 420 memprobe(vaddr_t endkernel) 421 { 422 phys_ram_seg_t *mr; 423 paddr_t boot_page = cpu_read_4(GUR_BPTR); 424 printf(" bptr=%"PRIxPADDR, boot_page); 425 if (boot_page & BPTR_EN) { 426 /* 427 * shift it to an address 428 */ 429 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 430 } else { 431 boot_page = ~(paddr_t)0; 432 } 433 434 /* 435 * First we need to find out how much physical memory we have. 436 * We could let our bootloader tell us, but it's almost as easy 437 * to ask the DDR memory controller. 438 */ 439 mr = physmemr; 440 #if 1 441 for (u_int i = 0; i < 4; i++) { 442 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 443 if (v & CS_CONFIG_EN) { 444 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 445 if (v == 0) 446 continue; 447 mr->start = BNDS_SA_GET(v); 448 mr->size = BNDS_SIZE_GET(v); 449 #if 0 450 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 451 mr - physmemr, mr->size, mr->start); 452 #endif 453 mr++; 454 } 455 } 456 457 if (mr == physmemr) 458 panic("no memory configured!"); 459 #else 460 mr->start = 0; 461 mr->size = 32 << 20; 462 mr++; 463 #endif 464 465 /* 466 * Sort memory regions from low to high and coalesce adjacent regions 467 */ 468 u_int cnt = mr - physmemr; 469 if (cnt > 1) { 470 for (u_int i = 0; i < cnt - 1; i++) { 471 for (u_int j = i + 1; j < cnt; j++) { 472 if (physmemr[j].start < physmemr[i].start) { 473 phys_ram_seg_t tmp = physmemr[i]; 474 physmemr[i] = physmemr[j]; 475 physmemr[j] = tmp; 476 } 477 } 478 } 479 mr = physmemr; 480 for (u_int i = 0; i < cnt; i++, mr++) { 481 if (mr->start + mr->size == mr[1].start) { 482 mr->size += mr[1].size; 483 for (u_int j = 1; j < cnt - i; j++) 484 mr[j] = mr[j+1]; 485 cnt--; 486 } 487 } 488 } 489 490 /* 491 * Copy physical memory to available memory. 492 */ 493 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 494 495 /* 496 * Adjust available memory to skip kernel at start of memory. 497 */ 498 availmemr[0].size -= endkernel - availmemr[0].start; 499 availmemr[0].start = endkernel; 500 501 mr = availmemr; 502 for (u_int i = 0; i < cnt; i++, mr++) { 503 /* 504 * U-boot reserves a boot-page on multi-core chips. 505 * We need to make sure that we never disturb it. 506 */ 507 const paddr_t mr_end = mr->start + mr->size; 508 if (mr_end > boot_page && boot_page >= mr->start) { 509 /* 510 * Normally u-boot will put in at the end 511 * of memory. But in case it doesn't, deal 512 * with all possibilities. 513 */ 514 if (boot_page + PAGE_SIZE == mr_end) { 515 mr->size -= PAGE_SIZE; 516 } else if (boot_page == mr->start) { 517 mr->start += PAGE_SIZE; 518 mr->size -= PAGE_SIZE; 519 } else { 520 mr->size = boot_page - mr->start; 521 mr++; 522 for (u_int j = cnt; j > i + 1; j--) { 523 availmemr[j] = availmemr[j-1]; 524 } 525 cnt++; 526 mr->start = boot_page + PAGE_SIZE; 527 mr->size = mr_end - mr->start; 528 } 529 break; 530 } 531 } 532 533 /* 534 * Steal pages at the end of memory for the kernel message buffer. 535 */ 536 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 537 msgbuf_paddr = 538 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 539 540 /* 541 * Calculate physmem. 542 */ 543 for (u_int i = 0; i < cnt; i++) 544 physmem += atop(physmemr[i].size); 545 546 nmemr = cnt; 547 return physmemr[cnt-1].start + physmemr[cnt-1].size; 548 } 549 550 void 551 consinit(void) 552 { 553 static bool attached = false; 554 555 if (attached) 556 return; 557 attached = true; 558 559 if (comcnfreq == -1) { 560 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 561 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 562 comcnfreq = e500_sys_clk * plat_ratio; 563 printf(" comcnfreq=%u", comcnfreq); 564 } 565 566 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 567 COM_TYPE_NORMAL, comcnmode); 568 } 569 570 void 571 cpu_probe_cache(void) 572 { 573 struct cpu_info * const ci = curcpu(); 574 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 575 576 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 577 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 578 579 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 580 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 581 582 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 583 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 584 } else { 585 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 586 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 587 } 588 589 #ifdef DEBUG 590 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 591 if ((L1CSR_CE & l1csr0) == 0) 592 printf(" DC=off"); 593 594 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 595 if ((L1CSR_CE & l1csr1) == 0) 596 printf(" IC=off"); 597 #endif 598 } 599 600 static uint16_t 601 getsvr(void) 602 { 603 uint16_t svr = mfspr(SPR_SVR) >> 16; 604 605 svr &= ~0x8; /* clear security bit */ 606 switch (svr) { 607 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 608 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 609 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 610 default: return svr; 611 } 612 } 613 614 static const char * 615 socname(uint32_t svr) 616 { 617 svr &= ~0x80000; /* clear security bit */ 618 switch (svr >> 8) { 619 case SVR_MPC8533 >> 8: return "MPC8533"; 620 case SVR_MPC8536v1 >> 8: return "MPC8536"; 621 case SVR_MPC8541v1 >> 8: return "MPC8541"; 622 case SVR_MPC8543v2 >> 8: return "MPC8543"; 623 case SVR_MPC8544v1 >> 8: return "MPC8544"; 624 case SVR_MPC8545v2 >> 8: return "MPC8545"; 625 case SVR_MPC8547v2 >> 8: return "MPC8547"; 626 case SVR_MPC8548v2 >> 8: return "MPC8548"; 627 case SVR_MPC8555v1 >> 8: return "MPC8555"; 628 case SVR_MPC8568v1 >> 8: return "MPC8568"; 629 case SVR_MPC8567v1 >> 8: return "MPC8567"; 630 case SVR_MPC8572v1 >> 8: return "MPC8572"; 631 case SVR_P2020v2 >> 8: return "P2020"; 632 case SVR_P2010v2 >> 8: return "P2010"; 633 default: 634 panic("%s: unknown SVR %#x", __func__, svr); 635 } 636 } 637 638 static void 639 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 640 { 641 static const char units[16] = "KKKKKMMMMMGGGGGT"; 642 643 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 644 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 645 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 646 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 647 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 648 649 aprint_normal_dev(self, "%s:", name); 650 651 aprint_normal(" %u", nentries); 652 if (TLBCFG_AVAIL_P(tlbcfg)) { 653 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 654 minsize, maxsize, units[maxsize_log4k]); 655 } else { 656 aprint_normal(" fixed-size (%uKB)", minsize); 657 } 658 if (assoc == 0 || assoc == nentries) 659 aprint_normal(" fully"); 660 else 661 aprint_normal(" %u-way set", assoc); 662 aprint_normal(" associative entries\n"); 663 } 664 665 static void 666 e500_cpu_attach(device_t self, u_int instance) 667 { 668 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 669 670 if (instance > 1) { 671 #ifdef MULTIPROCESSOR 672 #error still needs to be written 673 ci->ci_idepth = -1; 674 cpu_probe_cache(); 675 #else 676 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 677 return; 678 #endif 679 } 680 681 self->dv_private = ci; 682 683 ci->ci_cpuid = instance - (instance > 0); 684 ci->ci_dev = self; 685 //ci->ci_idlespin = cpu_idlespin; 686 uint64_t freq = board_info_get_number("processor-frequency"); 687 688 char freqbuf[10]; 689 if (freq >= 999500000) { 690 const uint32_t freq32 = (freq + 500000) / 10000000; 691 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 692 freq32 / 100, freq32 % 100); 693 } else { 694 const uint32_t freq32 = (freq + 500000) / 1000000; 695 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 696 } 697 698 const uint32_t pvr = mfpvr(); 699 const uint32_t svr = mfspr(SPR_SVR); 700 const uint32_t pir = mfspr(SPR_PIR); 701 702 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 703 "ID %u%s\n", 704 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 705 (svr >> 4) & 15, svr & 15, 706 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 707 (pvr >> 4) & 15, pvr & 15, 708 pir, (pir == 0 ? " (Primary)" : "")); 709 710 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 711 aprint_normal_dev(self, 712 "%uKB/%uB %u-way L1 %s cache\n", 713 L1CFG_CSIZE_GET(l1cfg0) >> 10, 714 32 << L1CFG_CBSIZE_GET(l1cfg0), 715 L1CFG_CNWAY_GET(l1cfg0), 716 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 717 ? "data" : "unified"); 718 719 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 720 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 721 aprint_normal_dev(self, 722 "%uKB/%uB %u-way L1 %s cache\n", 723 L1CFG_CSIZE_GET(l1cfg1) >> 10, 724 32 << L1CFG_CBSIZE_GET(l1cfg1), 725 L1CFG_CNWAY_GET(l1cfg1), 726 "instruction"); 727 } 728 729 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 730 aprint_normal_dev(self, 731 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 732 MMUCFG_NTLBS_GET(mmucfg) + 1, 733 MMUCFG_NPIDS_GET(mmucfg), 734 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 735 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 736 737 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 738 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 739 740 intr_cpu_attach(ci); 741 cpu_evcnt_attach(ci); 742 743 if (ci == curcpu()) 744 intr_cpu_hatch(ci); 745 } 746 747 void 748 e500_ipi_halt(void) 749 { 750 register_t msr, hid0; 751 752 msr = wrtee(0); 753 754 hid0 = mfspr(SPR_HID0); 755 hid0 = (hid0 & ~HID0_TBEN) | HID0_DOZE; 756 mtspr(SPR_HID0, hid0); 757 758 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 759 mtmsr(msr); 760 for (;;); /* loop forever */ 761 } 762 763 764 static void 765 calltozero(void) 766 { 767 panic("call to 0 from %p", __builtin_return_address(0)); 768 } 769 770 void 771 initppc(vaddr_t startkernel, vaddr_t endkernel, 772 void *a0, void *a1, void *a2, void *a3) 773 { 774 struct cpu_info * const ci = curcpu(); 775 struct cpu_softc * const cpu = ci->ci_softc; 776 777 cn_tab = &e500_earlycons; 778 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 779 startkernel, endkernel, a0, a1, a2, a3); 780 781 const register_t hid0 = mfspr(SPR_HID0); 782 mtspr(SPR_HID0, hid0 | HID0_TBEN | HID0_EMCP); 783 #ifdef CADMUS 784 /* 785 * Need to cache this from cadmus since we need to unmap cadmus since 786 * it falls in the middle of kernel address space. 787 */ 788 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 789 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 790 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 791 printf(" cadmus_pci=%#x", cadmus_pci); 792 printf(" cadmus_csr=%#x", cadmus_csr); 793 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 794 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 795 e500_sys_clk *= 2; 796 } 797 #endif 798 #ifdef PIXIS 799 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 800 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 801 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 802 #ifndef SYS_CLK 803 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 804 #else 805 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 806 #endif 807 #endif 808 printf(" porpllsr=0x%08x", 809 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 810 printf(" sys_clk=%"PRIu64, e500_sys_clk); 811 812 /* 813 * Make sure arguments are page aligned. 814 */ 815 startkernel = trunc_page(startkernel); 816 endkernel = round_page(endkernel); 817 818 /* 819 * Initialize the bus space tag used to access the 85xx general 820 * utility registers. It doesn't need to be extent protected. 821 * We know the GUR is mapped via a TLB1 entry so we add a limited 822 * mapiodev which allows mappings in GUR space. 823 */ 824 CTASSERT(offsetof(struct tlb_md_ops, md_tlb_mapiodev) == 0); 825 cpu_md_ops.md_tlb_ops = (const void *)&early_tlb_mapiodev; 826 bus_space_init(&gur_bst, NULL, NULL, 0); 827 bus_space_init(&gur_le_bst, NULL, NULL, 0); 828 cpu->cpu_bst = &gur_bst; 829 cpu->cpu_le_bst = &gur_le_bst; 830 cpu->cpu_bsh = gur_bsh; 831 832 /* 833 * Attach the console early, really early. 834 */ 835 consinit(); 836 837 /* 838 * Reset the PIC to a known state. 839 */ 840 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 841 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 842 ; 843 #if 0 844 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 845 #endif 846 printf(" openpic-reset(ctpr=%u)", 847 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 848 849 /* 850 * fill in with an absolute branch to a routine that will panic. 851 */ 852 *(int *)0 = 0x48000002 | (int) calltozero; 853 854 /* 855 * Get the cache sizes. 856 */ 857 cpu_probe_cache(); 858 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 859 ci->ci_ci.dcache_size >> 10, 860 ci->ci_ci.dcache_line_size, 861 ci->ci_ci.icache_size >> 10, 862 ci->ci_ci.icache_line_size); 863 864 /* 865 * Now find out how much memory is attached 866 */ 867 pmemsize = memprobe(endkernel); 868 cpu->cpu_highmem = pmemsize; 869 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 870 871 /* 872 * Now we need cleanout the TLB of stuff that we don't need. 873 */ 874 e500_tlb_init(endkernel, pmemsize); 875 printf(" e500_tlbinit(%#lx,%zuMB)", 876 endkernel, (size_t) (pmemsize >> 20)); 877 878 /* 879 * 880 */ 881 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 882 printf(" hid1=%#lx", mfspr(SPR_HID1)); 883 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 884 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 885 886 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 887 888 /* 889 * Initialize the message buffer. 890 */ 891 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 892 printf(" msgbuf=%p", (void *)msgbuf_paddr); 893 894 /* 895 * Initialize exception vectors and interrupts 896 */ 897 exception_init(&e500_intrsw); 898 printf(" exception_init=%p", &e500_intrsw); 899 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 900 901 /* 902 * Set the page size. 903 */ 904 uvm_setpagesize(); 905 906 /* 907 * Initialize the pmap. 908 */ 909 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 910 911 /* 912 * Let's take all the indirect calls via our stubs and patch 913 * them to be direct calls. 914 */ 915 cpu_fixup_stubs(); 916 #if 0 917 /* 918 * As a debug measure we can change the TLB entry that maps all of 919 * memory to one that encompasses the 64KB with the kernel vectors. 920 * All other pages will be soft faulted into the TLB as needed. 921 */ 922 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 923 mtspr(SPR_MAS6, 0); 924 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 925 uint32_t mas0 = mfspr(SPR_MAS0); 926 uint32_t mas1 = mfspr(SPR_MAS1); 927 uint32_t mas2 = mfspr(SPR_MAS2); 928 uint32_t mas3 = mfspr(SPR_MAS3); 929 KASSERT(mas3 & MAS3_SW); 930 KASSERT(mas3 & MAS3_SR); 931 KASSERT(mas3 & MAS3_SX); 932 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 933 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 934 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 935 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 936 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 937 #if 1 938 mtspr(SPR_MAS1, mas1); 939 mtspr(SPR_MAS2, mas2); 940 mtspr(SPR_MAS3, mas3); 941 extern void tlbwe(void); 942 tlbwe(); 943 mtspr(SPR_MAS0, saved_mas0); 944 printf("(ok)"); 945 #endif 946 #endif 947 948 /* 949 * Set some more MD helpers 950 */ 951 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 952 cpu_md_ops.md_device_register = e500_device_register; 953 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 954 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 955 #if NGPIO > 0 956 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 957 #endif 958 959 printf(" initppc done!\n"); 960 961 /* 962 * Look for the Book-E modules in the right place. 963 */ 964 module_machine = module_machine_booke; 965 } 966 967 #ifdef MPC8548 968 static const char * const mpc8548cds_extirq_names[] = { 969 [0] = "pci inta", 970 [1] = "pci intb", 971 [2] = "pci intc", 972 [3] = "pci intd", 973 [4] = "irq4", 974 [5] = "gige phy", 975 [6] = "atm phy", 976 [7] = "cpld", 977 [8] = "irq8", 978 [9] = "nvram", 979 [10] = "debug", 980 [11] = "pci2 inta", 981 }; 982 #endif 983 984 static const char * const mpc85xx_extirq_names[] = { 985 [0] = "extirq 0", 986 [1] = "extirq 1", 987 [2] = "extirq 2", 988 [3] = "extirq 3", 989 [4] = "extirq 4", 990 [5] = "extirq 5", 991 [6] = "extirq 6", 992 [7] = "extirq 7", 993 [8] = "extirq 8", 994 [9] = "extirq 9", 995 [10] = "extirq 10", 996 [11] = "extirq 11", 997 }; 998 999 static void 1000 mpc85xx_extirq_setup(void) 1001 { 1002 #ifdef MPC8548 1003 const char * const * names = mpc8548cds_extirq_names; 1004 const size_t n = __arraycount(mpc8548cds_extirq_names); 1005 #else 1006 const char * const * names = mpc85xx_extirq_names; 1007 const size_t n = __arraycount(mpc85xx_extirq_names); 1008 #endif 1009 prop_array_t extirqs = prop_array_create_with_capacity(n); 1010 for (u_int i = 0; i < n; i++) { 1011 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1012 prop_array_set(extirqs, i, ps); 1013 prop_object_release(ps); 1014 } 1015 board_info_add_object("external-irqs", extirqs); 1016 prop_object_release(extirqs); 1017 } 1018 1019 static void 1020 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1021 { 1022 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1023 KASSERT(pci_intmap != NULL); 1024 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1025 KASSERT(mask != NULL); 1026 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1027 prop_object_release(mask); 1028 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1029 KASSERT(pn_ist != NULL); 1030 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1031 KASSERT(pn_intr != NULL); 1032 prop_dictionary_t entry = prop_dictionary_create(); 1033 KASSERT(entry != NULL); 1034 prop_dictionary_set(entry, "interrupt", pn_intr); 1035 prop_dictionary_set(entry, "type", pn_ist); 1036 prop_dictionary_set(pci_intmap, "000000", entry); 1037 prop_object_release(pn_intr); 1038 prop_object_release(entry); 1039 va_list ap; 1040 va_start(ap, inta); 1041 u_int intrinc = __LOWEST_SET_BIT(intmask); 1042 for (u_int i = 0; i < intmask; i += intrinc) { 1043 char prop_name[12]; 1044 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1045 entry = prop_dictionary_create(); 1046 KASSERT(entry != NULL); 1047 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1048 KASSERT(pn_intr != NULL); 1049 prop_dictionary_set(entry, "interrupt", pn_intr); 1050 prop_dictionary_set(entry, "type", pn_ist); 1051 prop_dictionary_set(pci_intmap, prop_name, entry); 1052 prop_object_release(pn_intr); 1053 prop_object_release(entry); 1054 } 1055 va_end(ap); 1056 prop_object_release(pn_ist); 1057 board_info_add_object(name, pci_intmap); 1058 prop_object_release(pci_intmap); 1059 } 1060 1061 void 1062 cpu_startup(void) 1063 { 1064 struct cpu_info * const ci = curcpu(); 1065 const uint16_t svr = getsvr(); 1066 1067 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1068 1069 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1070 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1071 uint32_t e500_ratio = E500_RATIO_GET(v); 1072 1073 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1074 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1075 1076 ci->ci_khz = (cpu_freq + 500) / 1000; 1077 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1078 1079 board_info_add_number("my-id", svr); 1080 board_info_add_bool("pq3"); 1081 board_info_add_number("mem-size", pmemsize); 1082 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1083 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1084 uint32_t l2banks = l2siz >> 16; 1085 #ifdef MPC85555 1086 if (svr == (MPC8555v1 >> 16)) { 1087 l2siz >>= 1; 1088 l2banks >>= 1; 1089 } 1090 #endif 1091 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1092 if (boot_page & BPTR_EN) { 1093 bool found = false; 1094 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1095 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1096 * const bp = (void *)boot_page; 1097 bp <= dp; dp--) { 1098 if (*dp == boot_page) { 1099 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1100 spinup_table_addr = 1101 roundup2(spinup_table_addr, 32); 1102 board_info_add_number("mp-boot-page", 1103 boot_page); 1104 board_info_add_number("mp-spin-up-table", 1105 spinup_table_addr); 1106 printf("Found MP boot page @ %#"PRIxPADDR". " 1107 "Spin-up table @ %#"PRIxPTR"\n", 1108 boot_page, spinup_table_addr); 1109 found = true; 1110 break; 1111 } 1112 } 1113 if (!found) 1114 printf("Found MP boot page @ %#"PRIxPADDR 1115 " with missing U-boot signature!\n", boot_page); 1116 } 1117 board_info_add_number("l2-cache-size", l2siz); 1118 board_info_add_number("l2-cache-line-size", 32); 1119 board_info_add_number("l2-cache-banks", l2banks); 1120 board_info_add_number("l2-cache-ways", 8); 1121 1122 board_info_add_number("processor-frequency", cpu_freq); 1123 board_info_add_number("bus-frequency", ccb_freq); 1124 board_info_add_number("pci-frequency", e500_sys_clk); 1125 board_info_add_number("timebase-frequency", ccb_freq / 8); 1126 1127 #ifdef CADMUS 1128 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1129 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1130 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1131 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1132 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1133 #else 1134 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1135 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1136 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1137 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1138 #endif 1139 1140 uint64_t macstnaddr = 1141 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1142 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1143 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1144 1145 #if NPCI > 0 && defined(PCI_MEMBASE) 1146 pcimem_ex = extent_create("pcimem", 1147 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1148 M_DEVBUF, NULL, 0, EX_WAITOK); 1149 #endif 1150 #if NPCI > 0 && defined(PCI_IOBASE) 1151 pciio_ex = extent_create("pciio", 1152 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1153 M_DEVBUF, NULL, 0, EX_WAITOK); 1154 #endif 1155 mpc85xx_extirq_setup(); 1156 /* 1157 * PCI-Express virtual wire interrupts on combined with 1158 * External IRQ0/1/2/3. 1159 */ 1160 switch (svr) { 1161 #if defined(MPC8548) 1162 case SVR_MPC8548v1 >> 16: 1163 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1164 IST_LEVEL, 0, 1, 2, 3); 1165 break; 1166 #endif 1167 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1168 case SVR_MPC8536v1 >> 16: 1169 case SVR_MPC8544v1 >> 16: 1170 case SVR_MPC8572v1 >> 16: 1171 case SVR_P2010v2 >> 16: 1172 case SVR_P2020v2 >> 16: 1173 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1174 0, 1, 2, 3); 1175 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1176 4, 5, 6, 7); 1177 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1178 8, 9, 10, 11); 1179 break; 1180 #endif 1181 } 1182 switch (svr) { 1183 #if defined(MPC8536) 1184 case SVR_MPC8536v1 >> 16: 1185 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1186 1, 2, 3, 4); 1187 break; 1188 #endif 1189 #if defined(MPC8544) 1190 case SVR_MPC8544v1 >> 16: 1191 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1192 0, 1, 2, 3); 1193 break; 1194 #endif 1195 #if defined(MPC8548) 1196 case SVR_MPC8548v1 >> 16: 1197 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1198 0, 1, 2, 3); 1199 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1200 11, 1, 2, 3); 1201 break; 1202 #endif 1203 } 1204 } 1205
Indexes created Mon Sep 29 21:09:56 GMT 2025