machdep.c revision 1.14
1 /* $NetBSD: machdep.c,v 1.14 2011/06/29 05:53:05 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <powerpc/stdarg.h> 70 71 #include <dev/cons.h> 72 73 #include <dev/ic/comreg.h> 74 #include <dev/ic/comvar.h> 75 76 #include <net/if.h> 77 #include <net/if_media.h> 78 #include <dev/mii/miivar.h> 79 80 #include <powerpc/cpuset.h> 81 #include <powerpc/pcb.h> 82 #include <powerpc/spr.h> 83 #include <powerpc/booke/spr.h> 84 85 #include <powerpc/booke/cpuvar.h> 86 #include <powerpc/booke/e500reg.h> 87 #include <powerpc/booke/e500var.h> 88 #include <powerpc/booke/etsecreg.h> 89 #include <powerpc/booke/openpicreg.h> 90 #ifdef CADMUS 91 #include <evbppc/mpc85xx/cadmusreg.h> 92 #endif 93 #ifdef PIXIS 94 #include <evbppc/mpc85xx/pixisreg.h> 95 #endif 96 97 struct uboot_bdinfo { 98 uint32_t bd_memstart; 99 uint32_t bd_memsize; 100 uint32_t bd_flashstart; 101 uint32_t bd_flashsize; 102 /*10*/ uint32_t bd_flashoffset; 103 uint32_t bd_sramstart; 104 uint32_t bd_sramsize; 105 uint32_t bd_immrbase; 106 /*20*/ uint32_t bd_bootflags; 107 uint32_t bd_ipaddr; 108 uint8_t bd_etheraddr[6]; 109 uint16_t bd_ethspeed; 110 /*30*/ uint32_t bd_intfreq; 111 uint32_t bd_cpufreq; 112 uint32_t bd_baudrate; 113 /*3c*/ uint8_t bd_etheraddr1[6]; 114 /*42*/ uint8_t bd_etheraddr2[6]; 115 /*48*/ uint8_t bd_etheraddr3[6]; 116 /*4e*/ uint16_t bd_pad; 117 }; 118 119 /* 120 * booke kernels need to set module_machine to this for modules to work. 121 */ 122 char module_machine_booke[] = "powerpc-booke"; 123 124 void initppc(vaddr_t, vaddr_t, void *, void *, void *, void *); 125 126 #define MEMREGIONS 4 127 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 128 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 129 static u_int nmemr; 130 131 #ifndef CONSFREQ 132 # define CONSFREQ -1 /* inherit from firmware */ 133 #endif 134 #ifndef CONSPEED 135 # define CONSPEED 115200 136 #endif 137 #ifndef CONMODE 138 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 139 #endif 140 #ifndef CONSADDR 141 # define CONSADDR DUART2_BASE 142 #endif 143 144 int comcnfreq = CONSFREQ; 145 int comcnspeed = CONSPEED; 146 tcflag_t comcnmode = CONMODE; 147 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 148 149 #if NPCI > 0 150 struct extent *pcimem_ex; 151 struct extent *pciio_ex; 152 #endif 153 154 struct powerpc_bus_space gur_bst = { 155 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 156 .pbs_offset = GUR_BASE, 157 .pbs_limit = GUR_SIZE, 158 }; 159 160 struct powerpc_bus_space gur_le_bst = { 161 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 162 .pbs_offset = GUR_BASE, 163 .pbs_limit = GUR_SIZE, 164 }; 165 166 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 167 168 #if defined(SYS_CLK) 169 static uint64_t e500_sys_clk = SYS_CLK; 170 #endif 171 #ifdef CADMUS 172 static uint8_t cadmus_pci; 173 static uint8_t cadmus_csr; 174 #ifndef SYS_CLK 175 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 176 #endif 177 #elif defined(PIXIS) 178 static const uint32_t pixis_spd_map[8] = { 179 [PX_SPD_33MHZ] = 33333333, 180 [PX_SPD_40MHZ] = 40000000, 181 [PX_SPD_50MHZ] = 50000000, 182 [PX_SPD_66MHZ] = 66666666, 183 [PX_SPD_83MHZ] = 83333333, 184 [PX_SPD_100MHZ] = 100000000, 185 [PX_SPD_133MHZ] = 133333333, 186 [PX_SPD_166MHZ] = 166666667, 187 }; 188 static uint8_t pixis_spd; 189 #ifndef SYS_CLK 190 static uint64_t e500_sys_clk; 191 #endif 192 #elif !defined(SYS_CLK) 193 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 194 #endif 195 196 static int e500_cngetc(dev_t); 197 static void e500_cnputc(dev_t, int); 198 199 static struct consdev e500_earlycons = { 200 .cn_getc = e500_cngetc, 201 .cn_putc = e500_cnputc, 202 .cn_pollc = nullcnpollc, 203 }; 204 205 /* 206 * List of port-specific devices to attach to the processor local bus. 207 */ 208 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 209 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 210 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 211 #if defined(MPC8572) || defined(P2020) 212 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 213 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 214 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 215 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 216 #endif 217 { "wdog" }, /* not a real device */ 218 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 219 1, { ISOURCE_DUART }, 220 1 + ilog2(DEVDISR_DUART) }, 221 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 222 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 223 1 + ilog2(DEVDISR_TSEC1) }, 224 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 225 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 226 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 227 1 + ilog2(DEVDISR_TSEC2), 228 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 229 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 230 #endif 231 #if defined(MPC8544) || defined(MPC8536) 232 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 233 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 234 1 + ilog2(DEVDISR_TSEC3), 235 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 236 #endif 237 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 238 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 239 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 240 1 + ilog2(DEVDISR_TSEC3), 241 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 242 SVR_P2020v2 >> 16 } }, 243 #endif 244 #if defined(MPC8548) || defined(MPC8572) 245 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 246 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 247 1 + ilog2(DEVDISR_TSEC4), 248 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 249 #endif 250 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 251 1, { ISOURCE_I2C }, 252 1 + ilog2(DEVDISR_I2C) }, 253 /* MPC8572 doesn't have any GPIO */ 254 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 255 1, { ISOURCE_GPIO }, 256 0, 257 { 0xffff, SVR_MPC8572v1 >> 16 } }, 258 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 259 1, { ISOURCE_DDR }, 260 1 + ilog2(DEVDISR_DDR_15), 261 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 262 #if defined(MPC8536) 263 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 264 1, { ISOURCE_DDR }, 265 1 + ilog2(DEVDISR_DDR_16), 266 { SVR_MPC8536v1 >> 16 } }, 267 #endif 268 #if defined(MPC8572) 269 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 270 1, { ISOURCE_DDR }, 271 1 + ilog2(DEVDISR_DDR_15), 272 { SVR_MPC8572v1 >> 16 } }, 273 { "ddrc", DDRC1_BASE, DDRC_SIZE, 2, 274 1, { ISOURCE_DDR }, 275 1 + ilog2(DEVDISR_DDR2_14), 276 { SVR_MPC8572v1 >> 16 } }, 277 #endif 278 { "lbc", LBC_BASE, LBC_SIZE, 0, 279 1, { ISOURCE_LBC }, 280 1 + ilog2(DEVDISR_LBC) }, 281 #if defined(MPC8544) || defined(MPC8536) 282 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 283 1, { ISOURCE_PCIEX }, 284 1 + ilog2(DEVDISR_PCIE), 285 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 286 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 287 1, { ISOURCE_PCIEX2 }, 288 1 + ilog2(DEVDISR_PCIE2), 289 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 290 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 291 1, { ISOURCE_PCIEX3 }, 292 1 + ilog2(DEVDISR_PCIE3), 293 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 294 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 295 1, { ISOURCE_PCI1 }, 296 1 + ilog2(DEVDISR_PCI1), 297 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 298 #endif 299 #ifdef MPC8548 300 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 301 1, { ISOURCE_PCIEX }, 302 1 + ilog2(DEVDISR_PCIE), 303 { SVR_MPC8548v1 >> 16 }, }, 304 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 305 1, { ISOURCE_PCI1 }, 306 1 + ilog2(DEVDISR_PCI1), 307 { SVR_MPC8548v1 >> 16 }, }, 308 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 309 1, { ISOURCE_PCI2 }, 310 1 + ilog2(DEVDISR_PCI2), 311 { SVR_MPC8548v1 >> 16 }, }, 312 #endif 313 #if defined(MPC8572) || defined(P2020) 314 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 315 1, { ISOURCE_PCIEX }, 316 1 + ilog2(DEVDISR_PCIE), 317 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 318 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 319 1, { ISOURCE_PCIEX2 }, 320 1 + ilog2(DEVDISR_PCIE2), 321 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 322 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 323 1, { ISOURCE_PCIEX3_MPC8572 }, 324 1 + ilog2(DEVDISR_PCIE3), 325 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 326 #endif 327 #if defined(MPC8536) || defined(P2020) 328 { "ehci", USB1_BASE, USB_SIZE, 1, 329 1, { ISOURCE_USB1 }, 330 1 + ilog2(DEVDISR_USB1), 331 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 332 #endif 333 #ifdef MPC8536 334 { "ehci", USB2_BASE, USB_SIZE, 2, 335 1, { ISOURCE_USB2 }, 336 1 + ilog2(DEVDISR_USB2), 337 { SVR_MPC8536v1 >> 16 }, }, 338 { "ehci", USB3_BASE, USB_SIZE, 3, 339 1, { ISOURCE_USB3 }, 340 1 + ilog2(DEVDISR_USB3), 341 { SVR_MPC8536v1 >> 16 }, }, 342 { "sata", SATA1_BASE, SATA_SIZE, 1, 343 1, { ISOURCE_SATA1 }, 344 1 + ilog2(DEVDISR_SATA1), 345 { SVR_MPC8536v1 >> 16 }, }, 346 { "sata", SATA2_BASE, SATA_SIZE, 2, 347 1, { ISOURCE_SATA2 }, 348 1 + ilog2(DEVDISR_SATA2), 349 { SVR_MPC8536v1 >> 16 }, }, 350 { "spi", SPI_BASE, SPI_SIZE, 0, 351 1, { ISOURCE_SPI }, 352 1 + ilog2(DEVDISR_SPI_15), 353 { SVR_MPC8536v1 >> 16 }, }, 354 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 355 1, { ISOURCE_ESDHC }, 356 1 + ilog2(DEVDISR_ESDHC_12), 357 { SVR_MPC8536v1 >> 16 }, }, 358 #endif 359 #if defined(P2020) 360 { "spi", SPI_BASE, SPI_SIZE, 0, 361 1, { ISOURCE_SPI }, 362 1 + ilog2(DEVDISR_SPI_28), 363 { SVR_P2020v2 >> 16 }, }, 364 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 365 1, { ISOURCE_ESDHC }, 366 1 + ilog2(DEVDISR_ESDHC_10), 367 { SVR_P2020v2 >> 16 }, }, 368 #endif 369 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 370 { NULL } 371 }; 372 373 static int 374 e500_cngetc(dev_t dv) 375 { 376 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 377 378 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 379 return -1; 380 381 return com0addr[com_data] & 0xff; 382 } 383 384 static void 385 e500_cnputc(dev_t dv, int c) 386 { 387 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 388 int timo = 150000; 389 390 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 391 ; 392 393 com0addr[com_data] = c; 394 __asm("mbar"); 395 396 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 397 ; 398 } 399 400 static void * 401 gur_tlb_mapiodev(paddr_t pa, psize_t len) 402 { 403 if (pa < gur_bst.pbs_offset) 404 return NULL; 405 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 406 return NULL; 407 return (void *)pa; 408 } 409 410 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 411 412 static void 413 e500_cpu_reset(void) 414 { 415 __asm volatile("sync"); 416 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 417 __asm volatile("msync;isync"); 418 } 419 420 static psize_t 421 memprobe(vaddr_t endkernel) 422 { 423 phys_ram_seg_t *mr; 424 paddr_t boot_page = cpu_read_4(GUR_BPTR); 425 printf(" bptr=%"PRIxPADDR, boot_page); 426 if (boot_page & BPTR_EN) { 427 /* 428 * shift it to an address 429 */ 430 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 431 } else { 432 boot_page = ~(paddr_t)0; 433 } 434 435 /* 436 * First we need to find out how much physical memory we have. 437 * We could let our bootloader tell us, but it's almost as easy 438 * to ask the DDR memory controller. 439 */ 440 mr = physmemr; 441 #if 1 442 for (u_int i = 0; i < 4; i++) { 443 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 444 if (v & CS_CONFIG_EN) { 445 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 446 if (v == 0) 447 continue; 448 mr->start = BNDS_SA_GET(v); 449 mr->size = BNDS_SIZE_GET(v); 450 #if 0 451 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 452 mr - physmemr, mr->size, mr->start); 453 #endif 454 mr++; 455 } 456 } 457 458 if (mr == physmemr) 459 panic("no memory configured!"); 460 #else 461 mr->start = 0; 462 mr->size = 32 << 20; 463 mr++; 464 #endif 465 466 /* 467 * Sort memory regions from low to high and coalesce adjacent regions 468 */ 469 u_int cnt = mr - physmemr; 470 if (cnt > 1) { 471 for (u_int i = 0; i < cnt - 1; i++) { 472 for (u_int j = i + 1; j < cnt; j++) { 473 if (physmemr[j].start < physmemr[i].start) { 474 phys_ram_seg_t tmp = physmemr[i]; 475 physmemr[i] = physmemr[j]; 476 physmemr[j] = tmp; 477 } 478 } 479 } 480 mr = physmemr; 481 for (u_int i = 0; i < cnt; i++, mr++) { 482 if (mr->start + mr->size == mr[1].start) { 483 mr->size += mr[1].size; 484 for (u_int j = 1; j < cnt - i; j++) 485 mr[j] = mr[j+1]; 486 cnt--; 487 } 488 } 489 } 490 491 /* 492 * Copy physical memory to available memory. 493 */ 494 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 495 496 /* 497 * Adjust available memory to skip kernel at start of memory. 498 */ 499 availmemr[0].size -= endkernel - availmemr[0].start; 500 availmemr[0].start = endkernel; 501 502 mr = availmemr; 503 for (u_int i = 0; i < cnt; i++, mr++) { 504 /* 505 * U-boot reserves a boot-page on multi-core chips. 506 * We need to make sure that we never disturb it. 507 */ 508 const paddr_t mr_end = mr->start + mr->size; 509 if (mr_end > boot_page && boot_page >= mr->start) { 510 /* 511 * Normally u-boot will put in at the end 512 * of memory. But in case it doesn't, deal 513 * with all possibilities. 514 */ 515 if (boot_page + PAGE_SIZE == mr_end) { 516 mr->size -= PAGE_SIZE; 517 } else if (boot_page == mr->start) { 518 mr->start += PAGE_SIZE; 519 mr->size -= PAGE_SIZE; 520 } else { 521 mr->size = boot_page - mr->start; 522 mr++; 523 for (u_int j = cnt; j > i + 1; j--) { 524 availmemr[j] = availmemr[j-1]; 525 } 526 cnt++; 527 mr->start = boot_page + PAGE_SIZE; 528 mr->size = mr_end - mr->start; 529 } 530 break; 531 } 532 } 533 534 /* 535 * Steal pages at the end of memory for the kernel message buffer. 536 */ 537 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 538 msgbuf_paddr = 539 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 540 541 /* 542 * Calculate physmem. 543 */ 544 for (u_int i = 0; i < cnt; i++) 545 physmem += atop(physmemr[i].size); 546 547 nmemr = cnt; 548 return physmemr[cnt-1].start + physmemr[cnt-1].size; 549 } 550 551 void 552 consinit(void) 553 { 554 static bool attached = false; 555 556 if (attached) 557 return; 558 attached = true; 559 560 if (comcnfreq == -1) { 561 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 562 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 563 comcnfreq = e500_sys_clk * plat_ratio; 564 printf(" comcnfreq=%u", comcnfreq); 565 } 566 567 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 568 COM_TYPE_NORMAL, comcnmode); 569 } 570 571 void 572 cpu_probe_cache(void) 573 { 574 struct cpu_info * const ci = curcpu(); 575 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 576 577 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 578 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 579 580 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 581 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 582 583 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 584 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 585 } else { 586 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 587 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 588 } 589 590 #ifdef DEBUG 591 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 592 if ((L1CSR_CE & l1csr0) == 0) 593 printf(" DC=off"); 594 595 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 596 if ((L1CSR_CE & l1csr1) == 0) 597 printf(" IC=off"); 598 #endif 599 } 600 601 static uint16_t 602 getsvr(void) 603 { 604 uint16_t svr = mfspr(SPR_SVR) >> 16; 605 606 svr &= ~0x8; /* clear security bit */ 607 switch (svr) { 608 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 609 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 610 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 611 default: return svr; 612 } 613 } 614 615 static const char * 616 socname(uint32_t svr) 617 { 618 svr &= ~0x80000; /* clear security bit */ 619 switch (svr >> 8) { 620 case SVR_MPC8533 >> 8: return "MPC8533"; 621 case SVR_MPC8536v1 >> 8: return "MPC8536"; 622 case SVR_MPC8541v1 >> 8: return "MPC8541"; 623 case SVR_MPC8543v2 >> 8: return "MPC8543"; 624 case SVR_MPC8544v1 >> 8: return "MPC8544"; 625 case SVR_MPC8545v2 >> 8: return "MPC8545"; 626 case SVR_MPC8547v2 >> 8: return "MPC8547"; 627 case SVR_MPC8548v2 >> 8: return "MPC8548"; 628 case SVR_MPC8555v1 >> 8: return "MPC8555"; 629 case SVR_MPC8568v1 >> 8: return "MPC8568"; 630 case SVR_MPC8567v1 >> 8: return "MPC8567"; 631 case SVR_MPC8572v1 >> 8: return "MPC8572"; 632 case SVR_P2020v2 >> 8: return "P2020"; 633 case SVR_P2010v2 >> 8: return "P2010"; 634 default: 635 panic("%s: unknown SVR %#x", __func__, svr); 636 } 637 } 638 639 static void 640 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 641 { 642 static const char units[16] = "KKKKKMMMMMGGGGGT"; 643 644 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 645 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 646 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 647 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 648 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 649 650 aprint_normal_dev(self, "%s:", name); 651 652 aprint_normal(" %u", nentries); 653 if (TLBCFG_AVAIL_P(tlbcfg)) { 654 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 655 minsize, maxsize, units[maxsize_log4k]); 656 } else { 657 aprint_normal(" fixed-size (%uKB)", minsize); 658 } 659 if (assoc == 0 || assoc == nentries) 660 aprint_normal(" fully"); 661 else 662 aprint_normal(" %u-way set", assoc); 663 aprint_normal(" associative entries\n"); 664 } 665 666 static void 667 cpu_print_info(struct cpu_info *ci) 668 { 669 uint64_t freq = board_info_get_number("processor-frequency"); 670 device_t self = ci->ci_dev; 671 672 char freqbuf[10]; 673 if (freq >= 999500000) { 674 const uint32_t freq32 = (freq + 500000) / 10000000; 675 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 676 freq32 / 100, freq32 % 100); 677 } else { 678 const uint32_t freq32 = (freq + 500000) / 1000000; 679 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 680 } 681 682 const uint32_t pvr = mfpvr(); 683 const uint32_t svr = mfspr(SPR_SVR); 684 const uint32_t pir = mfspr(SPR_PIR); 685 686 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 687 "ID %u%s\n", 688 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 689 (svr >> 4) & 15, svr & 15, 690 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 691 (pvr >> 4) & 15, pvr & 15, 692 pir, (pir == 0 ? " (Primary)" : "")); 693 694 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 695 aprint_normal_dev(self, 696 "%uKB/%uB %u-way L1 %s cache\n", 697 L1CFG_CSIZE_GET(l1cfg0) >> 10, 698 32 << L1CFG_CBSIZE_GET(l1cfg0), 699 L1CFG_CNWAY_GET(l1cfg0), 700 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 701 ? "data" : "unified"); 702 703 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 704 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 705 aprint_normal_dev(self, 706 "%uKB/%uB %u-way L1 %s cache\n", 707 L1CFG_CSIZE_GET(l1cfg1) >> 10, 708 32 << L1CFG_CBSIZE_GET(l1cfg1), 709 L1CFG_CNWAY_GET(l1cfg1), 710 "instruction"); 711 } 712 713 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 714 aprint_normal_dev(self, 715 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 716 MMUCFG_NTLBS_GET(mmucfg) + 1, 717 MMUCFG_NPIDS_GET(mmucfg), 718 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 719 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 720 721 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 722 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 723 } 724 725 #ifdef MULTIPROCESSOR 726 static void 727 e500_cpu_spinup(device_t self, struct cpu_info *ci) 728 { 729 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 730 struct pglist splist; 731 732 if (spinup_table_addr == 0) { 733 aprint_error_dev(self, "hatch failed (no spin-up table)"); 734 return; 735 } 736 737 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 738 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 739 const size_t id = cpu_index(ci); 740 volatile __cpuset_t * const hatchlings = &cpuset_info.cpus_hatched; 741 742 if (h->hatch_sp == 0) { 743 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 744 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 745 if (error) { 746 aprint_error_dev(self, 747 "unable to allocate hatch stack\n"); 748 return; 749 } 750 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 751 + PAGE_SIZE - CALLFRAMELEN; 752 } 753 754 755 for (size_t i = 1; e[i].entry_pir != 0; i++) { 756 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 757 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 758 if (e[i].entry_pir == ci->ci_cpuid) { 759 760 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 761 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 762 ci->ci_curpm = pmap_kernel(); 763 ci->ci_lasttb = cpu_info[0].ci_lasttb; 764 ci->ci_data.cpu_cc_freq = 765 cpu_info[0].ci_data.cpu_cc_freq; 766 767 h->hatch_self = self; 768 h->hatch_ci = ci; 769 h->hatch_running = -1; 770 h->hatch_pir = e[i].entry_pir; 771 h->hatch_hid0 = mfspr(SPR_HID0); 772 KASSERT(h->hatch_sp != 0); 773 /* 774 * Get new timebase. We don't want to deal with 775 * timebase crossing a 32-bit boundary so make sure 776 * that we have enough headroom to do the timebase 777 * synchronization. 778 */ 779 #define TBSYNC_SLOP 2000 780 uint32_t tbl; 781 uint32_t tbu; 782 do { 783 tbu = mfspr(SPR_RTBU); 784 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 785 } while (tbl < TBSYNC_SLOP); 786 787 h->hatch_tbu = tbu; 788 h->hatch_tbl = tbl; 789 __asm("sync;isync"); 790 dcache_wbinv((vaddr_t)h, sizeof(*h)); 791 792 #if 1 793 /* 794 * And here we go... 795 */ 796 e[i].entry_addr_lower = 797 (uint32_t)e500_spinup_trampoline; 798 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 799 __asm __volatile("sync;isync"); 800 __insn_barrier(); 801 802 for (u_int timo = 0; timo++ < 10000; ) { 803 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 804 if (e[i].entry_addr_lower == 3) { 805 printf( 806 "%s: cpu%u started in %u spins\n", 807 __func__, cpu_index(ci), timo); 808 break; 809 } 810 } 811 for (u_int timo = 0; timo++ < 10000; ) { 812 dcache_inv((vaddr_t)h, sizeof(*h)); 813 if (h->hatch_running == 0) { 814 printf( 815 "%s: cpu%u cracked in %u spins: (running=%d)\n", 816 __func__, cpu_index(ci), 817 timo, h->hatch_running); 818 break; 819 } 820 } 821 if (h->hatch_running == -1) { 822 aprint_error_dev(self, 823 "hatch failed (timeout): running=%d" 824 ", entry=%#x\n", 825 h->hatch_running, e[i].entry_addr_lower); 826 goto out; 827 } 828 #endif 829 830 /* 831 * First then we do is to synchronize timebases. 832 * TBSYNC_SLOP*16 should be more than enough 833 * instructions. 834 */ 835 while (tbl != mftbl()) 836 continue; 837 h->hatch_running = 1; 838 dcache_wbinv((vaddr_t)h, sizeof(*h)); 839 __asm("sync;isync"); 840 __insn_barrier(); 841 842 for (u_int timo = 10000; timo-- > 0; ) { 843 dcache_inv((vaddr_t)h, sizeof(*h)); 844 if (h->hatch_running > 1) 845 break; 846 } 847 if (h->hatch_running == 1) { 848 printf( 849 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 850 __func__, 851 ((int64_t)tbu << 32) + tbl, 852 (int64_t) 853 (((uint64_t)h->hatch_tbu << 32) 854 + (uint64_t)h->hatch_tbl), 855 h->hatch_running); 856 goto out; 857 } 858 printf( 859 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 860 __func__, 861 (int64_t) 862 (((uint64_t)h->hatch_tbu << 32) 863 + (uint64_t)h->hatch_tbl), 864 h->hatch_running); 865 /* 866 * Now we wait for the hatching to complete. 10ms 867 * should be long enough. 868 */ 869 for (u_int timo = 10000; timo-- > 0; ) { 870 if (CPUSET_HAS_P(*hatchlings, id)) { 871 aprint_normal_dev(self, 872 "hatch successful (%u spins, " 873 "timebase adjusted by %"PRId64")\n", 874 10000 - timo, 875 (int64_t) 876 (((uint64_t)h->hatch_tbu << 32) 877 + (uint64_t)h->hatch_tbl)); 878 goto out; 879 } 880 DELAY(1); 881 } 882 883 aprint_error_dev(self, 884 "hatch failed (timeout): running=%u\n", 885 h->hatch_running); 886 goto out; 887 } 888 } 889 890 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 891 ci->ci_cpuid); 892 out: 893 if (h->hatch_sp == 0) 894 uvm_pglistfree(&splist); 895 } 896 #endif 897 898 void 899 e500_cpu_hatch(struct cpu_info *ci) 900 { 901 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 902 903 /* 904 * Make sure interrupts are blocked. 905 */ 906 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 907 908 intr_cpu_hatch(ci); 909 910 cpu_print_info(ci); 911 912 /* 913 */ 914 } 915 916 static void 917 e500_cpu_attach(device_t self, u_int instance) 918 { 919 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 920 921 if (instance > 1) { 922 #if defined(MULTIPROCESSOR) 923 ci->ci_idepth = -1; 924 self->dv_private = ci; 925 926 ci->ci_cpuid = instance - (instance > 0); 927 ci->ci_dev = self; 928 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 929 930 mi_cpu_attach(ci); 931 932 intr_cpu_attach(ci); 933 cpu_evcnt_attach(ci); 934 935 e500_cpu_spinup(self, ci); 936 return; 937 #else 938 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 939 return; 940 #endif 941 } 942 943 self->dv_private = ci; 944 945 ci->ci_cpuid = instance - (instance > 0); 946 ci->ci_dev = self; 947 948 intr_cpu_attach(ci); 949 cpu_evcnt_attach(ci); 950 951 KASSERT(ci == curcpu()); 952 intr_cpu_hatch(ci); 953 954 cpu_print_info(ci); 955 } 956 957 void 958 e500_ipi_halt(void) 959 { 960 register_t msr, hid0; 961 962 msr = wrtee(0); 963 964 hid0 = mfspr(SPR_HID0); 965 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 966 mtspr(SPR_HID0, hid0); 967 968 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 969 mtmsr(msr); 970 for (;;); /* loop forever */ 971 } 972 973 974 static void 975 calltozero(void) 976 { 977 panic("call to 0 from %p", __builtin_return_address(0)); 978 } 979 980 void 981 initppc(vaddr_t startkernel, vaddr_t endkernel, 982 void *a0, void *a1, void *a2, void *a3) 983 { 984 struct cpu_info * const ci = curcpu(); 985 struct cpu_softc * const cpu = ci->ci_softc; 986 987 cn_tab = &e500_earlycons; 988 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 989 startkernel, endkernel, a0, a1, a2, a3); 990 991 /* 992 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 993 * DOZE is ok. 994 */ 995 const register_t hid0 = mfspr(SPR_HID0); 996 mtspr(SPR_HID0, 997 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 998 #ifdef CADMUS 999 /* 1000 * Need to cache this from cadmus since we need to unmap cadmus since 1001 * it falls in the middle of kernel address space. 1002 */ 1003 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1004 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1005 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1006 printf(" cadmus_pci=%#x", cadmus_pci); 1007 printf(" cadmus_csr=%#x", cadmus_csr); 1008 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1009 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1010 e500_sys_clk *= 2; 1011 } 1012 #endif 1013 #ifdef PIXIS 1014 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1015 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1016 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1017 #ifndef SYS_CLK 1018 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1019 #else 1020 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1021 #endif 1022 #endif 1023 printf(" porpllsr=0x%08x", 1024 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1025 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1026 1027 /* 1028 * Make sure arguments are page aligned. 1029 */ 1030 startkernel = trunc_page(startkernel); 1031 endkernel = round_page(endkernel); 1032 1033 /* 1034 * Initialize the bus space tag used to access the 85xx general 1035 * utility registers. It doesn't need to be extent protected. 1036 * We know the GUR is mapped via a TLB1 entry so we add a limited 1037 * mapiodev which allows mappings in GUR space. 1038 */ 1039 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1040 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1041 bus_space_init(&gur_bst, NULL, NULL, 0); 1042 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1043 cpu->cpu_bst = &gur_bst; 1044 cpu->cpu_le_bst = &gur_le_bst; 1045 cpu->cpu_bsh = gur_bsh; 1046 1047 /* 1048 * Attach the console early, really early. 1049 */ 1050 consinit(); 1051 1052 /* 1053 * Reset the PIC to a known state. 1054 */ 1055 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1056 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1057 ; 1058 #if 0 1059 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1060 #endif 1061 printf(" openpic-reset(ctpr=%u)", 1062 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1063 1064 /* 1065 * fill in with an absolute branch to a routine that will panic. 1066 */ 1067 *(int *)0 = 0x48000002 | (int) calltozero; 1068 1069 /* 1070 * Get the cache sizes. 1071 */ 1072 cpu_probe_cache(); 1073 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1074 ci->ci_ci.dcache_size >> 10, 1075 ci->ci_ci.dcache_line_size, 1076 ci->ci_ci.icache_size >> 10, 1077 ci->ci_ci.icache_line_size); 1078 1079 /* 1080 * Now find out how much memory is attached 1081 */ 1082 pmemsize = memprobe(endkernel); 1083 cpu->cpu_highmem = pmemsize; 1084 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1085 1086 /* 1087 * Now we need cleanout the TLB of stuff that we don't need. 1088 */ 1089 e500_tlb_init(endkernel, pmemsize); 1090 printf(" e500_tlbinit(%#lx,%zuMB)", 1091 endkernel, (size_t) (pmemsize >> 20)); 1092 1093 /* 1094 * 1095 */ 1096 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1097 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1098 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1099 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1100 1101 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1102 1103 /* 1104 * Initialize the message buffer. 1105 */ 1106 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1107 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1108 1109 /* 1110 * Initialize exception vectors and interrupts 1111 */ 1112 exception_init(&e500_intrsw); 1113 1114 printf(" exception_init=%p", &e500_intrsw); 1115 1116 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1117 1118 /* 1119 * Set the page size. 1120 */ 1121 uvm_setpagesize(); 1122 1123 /* 1124 * Initialize the pmap. 1125 */ 1126 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1127 1128 /* 1129 * Let's take all the indirect calls via our stubs and patch 1130 * them to be direct calls. 1131 */ 1132 cpu_fixup_stubs(); 1133 #if 0 1134 /* 1135 * As a debug measure we can change the TLB entry that maps all of 1136 * memory to one that encompasses the 64KB with the kernel vectors. 1137 * All other pages will be soft faulted into the TLB as needed. 1138 */ 1139 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 1140 mtspr(SPR_MAS6, 0); 1141 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 1142 uint32_t mas0 = mfspr(SPR_MAS0); 1143 uint32_t mas1 = mfspr(SPR_MAS1); 1144 uint32_t mas2 = mfspr(SPR_MAS2); 1145 uint32_t mas3 = mfspr(SPR_MAS3); 1146 KASSERT(mas3 & MAS3_SW); 1147 KASSERT(mas3 & MAS3_SR); 1148 KASSERT(mas3 & MAS3_SX); 1149 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 1150 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 1151 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 1152 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 1153 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 1154 #if 1 1155 mtspr(SPR_MAS1, mas1); 1156 mtspr(SPR_MAS2, mas2); 1157 mtspr(SPR_MAS3, mas3); 1158 extern void tlbwe(void); 1159 tlbwe(); 1160 mtspr(SPR_MAS0, saved_mas0); 1161 printf("(ok)"); 1162 #endif 1163 #endif 1164 1165 /* 1166 * Set some more MD helpers 1167 */ 1168 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1169 cpu_md_ops.md_device_register = e500_device_register; 1170 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1171 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1172 #if NGPIO > 0 1173 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1174 #endif 1175 1176 printf(" initppc done!\n"); 1177 1178 /* 1179 * Look for the Book-E modules in the right place. 1180 */ 1181 module_machine = module_machine_booke; 1182 } 1183 1184 #ifdef MPC8548 1185 static const char * const mpc8548cds_extirq_names[] = { 1186 [0] = "pci inta", 1187 [1] = "pci intb", 1188 [2] = "pci intc", 1189 [3] = "pci intd", 1190 [4] = "irq4", 1191 [5] = "gige phy", 1192 [6] = "atm phy", 1193 [7] = "cpld", 1194 [8] = "irq8", 1195 [9] = "nvram", 1196 [10] = "debug", 1197 [11] = "pci2 inta", 1198 }; 1199 #endif 1200 1201 static const char * const mpc85xx_extirq_names[] = { 1202 [0] = "extirq 0", 1203 [1] = "extirq 1", 1204 [2] = "extirq 2", 1205 [3] = "extirq 3", 1206 [4] = "extirq 4", 1207 [5] = "extirq 5", 1208 [6] = "extirq 6", 1209 [7] = "extirq 7", 1210 [8] = "extirq 8", 1211 [9] = "extirq 9", 1212 [10] = "extirq 10", 1213 [11] = "extirq 11", 1214 }; 1215 1216 static void 1217 mpc85xx_extirq_setup(void) 1218 { 1219 #ifdef MPC8548 1220 const char * const * names = mpc8548cds_extirq_names; 1221 const size_t n = __arraycount(mpc8548cds_extirq_names); 1222 #else 1223 const char * const * names = mpc85xx_extirq_names; 1224 const size_t n = __arraycount(mpc85xx_extirq_names); 1225 #endif 1226 prop_array_t extirqs = prop_array_create_with_capacity(n); 1227 for (u_int i = 0; i < n; i++) { 1228 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1229 prop_array_set(extirqs, i, ps); 1230 prop_object_release(ps); 1231 } 1232 board_info_add_object("external-irqs", extirqs); 1233 prop_object_release(extirqs); 1234 } 1235 1236 static void 1237 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1238 { 1239 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1240 KASSERT(pci_intmap != NULL); 1241 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1242 KASSERT(mask != NULL); 1243 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1244 prop_object_release(mask); 1245 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1246 KASSERT(pn_ist != NULL); 1247 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1248 KASSERT(pn_intr != NULL); 1249 prop_dictionary_t entry = prop_dictionary_create(); 1250 KASSERT(entry != NULL); 1251 prop_dictionary_set(entry, "interrupt", pn_intr); 1252 prop_dictionary_set(entry, "type", pn_ist); 1253 prop_dictionary_set(pci_intmap, "000000", entry); 1254 prop_object_release(pn_intr); 1255 prop_object_release(entry); 1256 va_list ap; 1257 va_start(ap, inta); 1258 u_int intrinc = __LOWEST_SET_BIT(intmask); 1259 for (u_int i = 0; i < intmask; i += intrinc) { 1260 char prop_name[12]; 1261 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1262 entry = prop_dictionary_create(); 1263 KASSERT(entry != NULL); 1264 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1265 KASSERT(pn_intr != NULL); 1266 prop_dictionary_set(entry, "interrupt", pn_intr); 1267 prop_dictionary_set(entry, "type", pn_ist); 1268 prop_dictionary_set(pci_intmap, prop_name, entry); 1269 prop_object_release(pn_intr); 1270 prop_object_release(entry); 1271 } 1272 va_end(ap); 1273 prop_object_release(pn_ist); 1274 board_info_add_object(name, pci_intmap); 1275 prop_object_release(pci_intmap); 1276 } 1277 1278 void 1279 cpu_startup(void) 1280 { 1281 struct cpu_info * const ci = curcpu(); 1282 const uint16_t svr = getsvr(); 1283 1284 powersave = 0; /* we can do it but turn it on by default */ 1285 1286 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1287 1288 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1289 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1290 uint32_t e500_ratio = E500_RATIO_GET(v); 1291 1292 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1293 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1294 1295 ci->ci_khz = (cpu_freq + 500) / 1000; 1296 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1297 1298 board_info_add_number("my-id", svr); 1299 board_info_add_bool("pq3"); 1300 board_info_add_number("mem-size", pmemsize); 1301 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1302 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1303 uint32_t l2banks = l2siz >> 16; 1304 #ifdef MPC85555 1305 if (svr == (MPC8555v1 >> 16)) { 1306 l2siz >>= 1; 1307 l2banks >>= 1; 1308 } 1309 #endif 1310 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1311 if (boot_page & BPTR_EN) { 1312 bool found = false; 1313 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1314 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1315 * const bp = (void *)boot_page; 1316 bp <= dp; dp--) { 1317 if (*dp == boot_page) { 1318 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1319 spinup_table_addr = 1320 roundup2(spinup_table_addr, 32); 1321 board_info_add_number("mp-boot-page", 1322 boot_page); 1323 board_info_add_number("mp-spin-up-table", 1324 spinup_table_addr); 1325 printf("Found MP boot page @ %#"PRIxPADDR". " 1326 "Spin-up table @ %#"PRIxPTR"\n", 1327 boot_page, spinup_table_addr); 1328 found = true; 1329 break; 1330 } 1331 } 1332 if (!found) { 1333 printf("Found MP boot page @ %#"PRIxPADDR 1334 " with missing U-boot signature!\n", boot_page); 1335 board_info_add_number("mp-spin-up-table", 0); 1336 } 1337 } 1338 board_info_add_number("l2-cache-size", l2siz); 1339 board_info_add_number("l2-cache-line-size", 32); 1340 board_info_add_number("l2-cache-banks", l2banks); 1341 board_info_add_number("l2-cache-ways", 8); 1342 1343 board_info_add_number("processor-frequency", cpu_freq); 1344 board_info_add_number("bus-frequency", ccb_freq); 1345 board_info_add_number("pci-frequency", e500_sys_clk); 1346 board_info_add_number("timebase-frequency", ccb_freq / 8); 1347 1348 #ifdef CADMUS 1349 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1350 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1351 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1352 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1353 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1354 #else 1355 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1356 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1357 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1358 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1359 #endif 1360 1361 uint64_t macstnaddr = 1362 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1363 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1364 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1365 1366 #if NPCI > 0 && defined(PCI_MEMBASE) 1367 pcimem_ex = extent_create("pcimem", 1368 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1369 M_DEVBUF, NULL, 0, EX_WAITOK); 1370 #endif 1371 #if NPCI > 0 && defined(PCI_IOBASE) 1372 pciio_ex = extent_create("pciio", 1373 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1374 M_DEVBUF, NULL, 0, EX_WAITOK); 1375 #endif 1376 mpc85xx_extirq_setup(); 1377 /* 1378 * PCI-Express virtual wire interrupts on combined with 1379 * External IRQ0/1/2/3. 1380 */ 1381 switch (svr) { 1382 #if defined(MPC8548) 1383 case SVR_MPC8548v1 >> 16: 1384 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1385 IST_LEVEL, 0, 1, 2, 3); 1386 break; 1387 #endif 1388 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1389 case SVR_MPC8536v1 >> 16: 1390 case SVR_MPC8544v1 >> 16: 1391 case SVR_MPC8572v1 >> 16: 1392 case SVR_P2010v2 >> 16: 1393 case SVR_P2020v2 >> 16: 1394 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1395 0, 1, 2, 3); 1396 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1397 4, 5, 6, 7); 1398 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1399 8, 9, 10, 11); 1400 break; 1401 #endif 1402 } 1403 switch (svr) { 1404 #if defined(MPC8536) 1405 case SVR_MPC8536v1 >> 16: 1406 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1407 1, 2, 3, 4); 1408 break; 1409 #endif 1410 #if defined(MPC8544) 1411 case SVR_MPC8544v1 >> 16: 1412 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1413 0, 1, 2, 3); 1414 break; 1415 #endif 1416 #if defined(MPC8548) 1417 case SVR_MPC8548v1 >> 16: 1418 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1419 0, 1, 2, 3); 1420 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1421 11, 1, 2, 3); 1422 break; 1423 #endif 1424 } 1425 } 1426
Indexes created Sun Oct 19 02:09:48 GMT 2025