machdep.c revision 1.17
1 /* $NetBSD: machdep.c,v 1.17 2011/07/16 21:36:18 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <powerpc/stdarg.h> 70 71 #include <dev/cons.h> 72 73 #include <dev/ic/comreg.h> 74 #include <dev/ic/comvar.h> 75 76 #include <net/if.h> 77 #include <net/if_media.h> 78 #include <dev/mii/miivar.h> 79 80 #include <powerpc/cpuset.h> 81 #include <powerpc/pcb.h> 82 #include <powerpc/spr.h> 83 #include <powerpc/booke/spr.h> 84 85 #include <powerpc/booke/cpuvar.h> 86 #include <powerpc/booke/e500reg.h> 87 #include <powerpc/booke/e500var.h> 88 #include <powerpc/booke/etsecreg.h> 89 #include <powerpc/booke/openpicreg.h> 90 #ifdef CADMUS 91 #include <evbppc/mpc85xx/cadmusreg.h> 92 #endif 93 #ifdef PIXIS 94 #include <evbppc/mpc85xx/pixisreg.h> 95 #endif 96 97 struct uboot_bdinfo { 98 uint32_t bd_memstart; 99 uint32_t bd_memsize; 100 uint32_t bd_flashstart; 101 uint32_t bd_flashsize; 102 /*10*/ uint32_t bd_flashoffset; 103 uint32_t bd_sramstart; 104 uint32_t bd_sramsize; 105 uint32_t bd_immrbase; 106 /*20*/ uint32_t bd_bootflags; 107 uint32_t bd_ipaddr; 108 uint8_t bd_etheraddr[6]; 109 uint16_t bd_ethspeed; 110 /*30*/ uint32_t bd_intfreq; 111 uint32_t bd_cpufreq; 112 uint32_t bd_baudrate; 113 /*3c*/ uint8_t bd_etheraddr1[6]; 114 /*42*/ uint8_t bd_etheraddr2[6]; 115 /*48*/ uint8_t bd_etheraddr3[6]; 116 /*4e*/ uint16_t bd_pad; 117 }; 118 119 /* 120 * booke kernels need to set module_machine to this for modules to work. 121 */ 122 char module_machine_booke[] = "powerpc-booke"; 123 124 void initppc(vaddr_t, vaddr_t, void *, void *, void *, void *); 125 126 #define MEMREGIONS 4 127 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 128 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 129 static u_int nmemr; 130 131 #ifndef CONSFREQ 132 # define CONSFREQ -1 /* inherit from firmware */ 133 #endif 134 #ifndef CONSPEED 135 # define CONSPEED 115200 136 #endif 137 #ifndef CONMODE 138 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 139 #endif 140 #ifndef CONSADDR 141 # define CONSADDR DUART2_BASE 142 #endif 143 144 int comcnfreq = CONSFREQ; 145 int comcnspeed = CONSPEED; 146 tcflag_t comcnmode = CONMODE; 147 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 148 149 #if NPCI > 0 150 struct extent *pcimem_ex; 151 struct extent *pciio_ex; 152 #endif 153 154 struct powerpc_bus_space gur_bst = { 155 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 156 .pbs_offset = GUR_BASE, 157 .pbs_limit = GUR_SIZE, 158 }; 159 160 struct powerpc_bus_space gur_le_bst = { 161 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 162 .pbs_offset = GUR_BASE, 163 .pbs_limit = GUR_SIZE, 164 }; 165 166 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 167 168 #if defined(SYS_CLK) 169 static uint64_t e500_sys_clk = SYS_CLK; 170 #endif 171 #ifdef CADMUS 172 static uint8_t cadmus_pci; 173 static uint8_t cadmus_csr; 174 #ifndef SYS_CLK 175 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 176 #endif 177 #elif defined(PIXIS) 178 static const uint32_t pixis_spd_map[8] = { 179 [PX_SPD_33MHZ] = 33333333, 180 [PX_SPD_40MHZ] = 40000000, 181 [PX_SPD_50MHZ] = 50000000, 182 [PX_SPD_66MHZ] = 66666666, 183 [PX_SPD_83MHZ] = 83333333, 184 [PX_SPD_100MHZ] = 100000000, 185 [PX_SPD_133MHZ] = 133333333, 186 [PX_SPD_166MHZ] = 166666667, 187 }; 188 static uint8_t pixis_spd; 189 #ifndef SYS_CLK 190 static uint64_t e500_sys_clk; 191 #endif 192 #elif !defined(SYS_CLK) 193 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 194 #endif 195 196 static int e500_cngetc(dev_t); 197 static void e500_cnputc(dev_t, int); 198 199 static struct consdev e500_earlycons = { 200 .cn_getc = e500_cngetc, 201 .cn_putc = e500_cnputc, 202 .cn_pollc = nullcnpollc, 203 }; 204 205 /* 206 * List of port-specific devices to attach to the processor local bus. 207 */ 208 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 209 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 210 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 211 #if defined(MPC8572) || defined(P2020) 212 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 213 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 214 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 215 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 216 #endif 217 { "wdog" }, /* not a real device */ 218 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 219 1, { ISOURCE_DUART }, 220 1 + ilog2(DEVDISR_DUART) }, 221 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 222 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 223 1 + ilog2(DEVDISR_TSEC1) }, 224 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 225 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 226 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 227 1 + ilog2(DEVDISR_TSEC2), 228 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 229 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 230 #endif 231 #if defined(MPC8544) || defined(MPC8536) 232 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 233 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 234 1 + ilog2(DEVDISR_TSEC3), 235 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 236 #endif 237 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 238 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 239 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 240 1 + ilog2(DEVDISR_TSEC3), 241 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 242 SVR_P2020v2 >> 16 } }, 243 #endif 244 #if defined(MPC8548) || defined(MPC8572) 245 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 246 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 247 1 + ilog2(DEVDISR_TSEC4), 248 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 249 #endif 250 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 251 1, { ISOURCE_I2C }, 252 1 + ilog2(DEVDISR_I2C) }, 253 /* MPC8572 doesn't have any GPIO */ 254 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 255 1, { ISOURCE_GPIO }, 256 0, 257 { 0xffff, SVR_MPC8572v1 >> 16 } }, 258 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 259 1, { ISOURCE_DDR }, 260 1 + ilog2(DEVDISR_DDR_15), 261 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 262 #if defined(MPC8536) 263 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 264 1, { ISOURCE_DDR }, 265 1 + ilog2(DEVDISR_DDR_16), 266 { SVR_MPC8536v1 >> 16 } }, 267 #endif 268 #if defined(MPC8572) 269 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 270 1, { ISOURCE_DDR }, 271 1 + ilog2(DEVDISR_DDR_15), 272 { SVR_MPC8572v1 >> 16 } }, 273 { "ddrc", DDRC1_BASE, DDRC_SIZE, 2, 274 1, { ISOURCE_DDR }, 275 1 + ilog2(DEVDISR_DDR2_14), 276 { SVR_MPC8572v1 >> 16 } }, 277 #endif 278 { "lbc", LBC_BASE, LBC_SIZE, 0, 279 1, { ISOURCE_LBC }, 280 1 + ilog2(DEVDISR_LBC) }, 281 #if defined(MPC8544) || defined(MPC8536) 282 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 283 1, { ISOURCE_PCIEX }, 284 1 + ilog2(DEVDISR_PCIE), 285 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 286 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 287 1, { ISOURCE_PCIEX2 }, 288 1 + ilog2(DEVDISR_PCIE2), 289 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 290 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 291 1, { ISOURCE_PCIEX3 }, 292 1 + ilog2(DEVDISR_PCIE3), 293 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 294 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 295 1, { ISOURCE_PCI1 }, 296 1 + ilog2(DEVDISR_PCI1), 297 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 298 #endif 299 #ifdef MPC8548 300 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 301 1, { ISOURCE_PCIEX }, 302 1 + ilog2(DEVDISR_PCIE), 303 { SVR_MPC8548v1 >> 16 }, }, 304 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 305 1, { ISOURCE_PCI1 }, 306 1 + ilog2(DEVDISR_PCI1), 307 { SVR_MPC8548v1 >> 16 }, }, 308 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 309 1, { ISOURCE_PCI2 }, 310 1 + ilog2(DEVDISR_PCI2), 311 { SVR_MPC8548v1 >> 16 }, }, 312 #endif 313 #if defined(MPC8572) || defined(P2020) 314 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 315 1, { ISOURCE_PCIEX }, 316 1 + ilog2(DEVDISR_PCIE), 317 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 318 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 319 1, { ISOURCE_PCIEX2 }, 320 1 + ilog2(DEVDISR_PCIE2), 321 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 322 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 323 1, { ISOURCE_PCIEX3_MPC8572 }, 324 1 + ilog2(DEVDISR_PCIE3), 325 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 326 #endif 327 #if defined(MPC8536) || defined(P2020) 328 { "ehci", USB1_BASE, USB_SIZE, 1, 329 1, { ISOURCE_USB1 }, 330 1 + ilog2(DEVDISR_USB1), 331 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 332 #endif 333 #ifdef MPC8536 334 { "ehci", USB2_BASE, USB_SIZE, 2, 335 1, { ISOURCE_USB2 }, 336 1 + ilog2(DEVDISR_USB2), 337 { SVR_MPC8536v1 >> 16 }, }, 338 { "ehci", USB3_BASE, USB_SIZE, 3, 339 1, { ISOURCE_USB3 }, 340 1 + ilog2(DEVDISR_USB3), 341 { SVR_MPC8536v1 >> 16 }, }, 342 { "sata", SATA1_BASE, SATA_SIZE, 1, 343 1, { ISOURCE_SATA1 }, 344 1 + ilog2(DEVDISR_SATA1), 345 { SVR_MPC8536v1 >> 16 }, }, 346 { "sata", SATA2_BASE, SATA_SIZE, 2, 347 1, { ISOURCE_SATA2 }, 348 1 + ilog2(DEVDISR_SATA2), 349 { SVR_MPC8536v1 >> 16 }, }, 350 { "spi", SPI_BASE, SPI_SIZE, 0, 351 1, { ISOURCE_SPI }, 352 1 + ilog2(DEVDISR_SPI_15), 353 { SVR_MPC8536v1 >> 16 }, }, 354 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 355 1, { ISOURCE_ESDHC }, 356 1 + ilog2(DEVDISR_ESDHC_12), 357 { SVR_MPC8536v1 >> 16 }, }, 358 #endif 359 #if defined(P2020) 360 { "spi", SPI_BASE, SPI_SIZE, 0, 361 1, { ISOURCE_SPI }, 362 1 + ilog2(DEVDISR_SPI_28), 363 { SVR_P2020v2 >> 16 }, }, 364 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 365 1, { ISOURCE_ESDHC }, 366 1 + ilog2(DEVDISR_ESDHC_10), 367 { SVR_P2020v2 >> 16 }, }, 368 #endif 369 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 370 { NULL } 371 }; 372 373 static int 374 e500_cngetc(dev_t dv) 375 { 376 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 377 378 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 379 return -1; 380 381 return com0addr[com_data] & 0xff; 382 } 383 384 static void 385 e500_cnputc(dev_t dv, int c) 386 { 387 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 388 int timo = 150000; 389 390 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 391 ; 392 393 com0addr[com_data] = c; 394 __asm("mbar"); 395 396 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 397 ; 398 } 399 400 static void * 401 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 402 { 403 if (prefetchable) 404 return NULL; 405 if (pa < gur_bst.pbs_offset) 406 return NULL; 407 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 408 return NULL; 409 return (void *)pa; 410 } 411 412 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 413 414 static void 415 e500_cpu_reset(void) 416 { 417 __asm volatile("sync"); 418 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 419 __asm volatile("msync;isync"); 420 } 421 422 static psize_t 423 memprobe(vaddr_t endkernel) 424 { 425 phys_ram_seg_t *mr; 426 paddr_t boot_page = cpu_read_4(GUR_BPTR); 427 printf(" bptr=%"PRIxPADDR, boot_page); 428 if (boot_page & BPTR_EN) { 429 /* 430 * shift it to an address 431 */ 432 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 433 } else { 434 boot_page = ~(paddr_t)0; 435 } 436 437 /* 438 * First we need to find out how much physical memory we have. 439 * We could let our bootloader tell us, but it's almost as easy 440 * to ask the DDR memory controller. 441 */ 442 mr = physmemr; 443 #if 1 444 for (u_int i = 0; i < 4; i++) { 445 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 446 if (v & CS_CONFIG_EN) { 447 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 448 if (v == 0) 449 continue; 450 mr->start = BNDS_SA_GET(v); 451 mr->size = BNDS_SIZE_GET(v); 452 #if 0 453 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 454 mr - physmemr, mr->size, mr->start); 455 #endif 456 mr++; 457 } 458 } 459 460 if (mr == physmemr) 461 panic("no memory configured!"); 462 #else 463 mr->start = 0; 464 mr->size = 32 << 20; 465 mr++; 466 #endif 467 468 /* 469 * Sort memory regions from low to high and coalesce adjacent regions 470 */ 471 u_int cnt = mr - physmemr; 472 if (cnt > 1) { 473 for (u_int i = 0; i < cnt - 1; i++) { 474 for (u_int j = i + 1; j < cnt; j++) { 475 if (physmemr[j].start < physmemr[i].start) { 476 phys_ram_seg_t tmp = physmemr[i]; 477 physmemr[i] = physmemr[j]; 478 physmemr[j] = tmp; 479 } 480 } 481 } 482 mr = physmemr; 483 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 484 if (mr->start + mr->size == mr[1].start) { 485 mr->size += mr[1].size; 486 for (u_int j = 1; i + j + 1 < cnt; j++) 487 mr[j] = mr[j+1]; 488 cnt--; 489 } 490 } 491 } else if (cnt == 0) { 492 panic("%s: no memory found", __func__); 493 } 494 495 /* 496 * Copy physical memory to available memory. 497 */ 498 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 499 500 /* 501 * Adjust available memory to skip kernel at start of memory. 502 */ 503 availmemr[0].size -= endkernel - availmemr[0].start; 504 availmemr[0].start = endkernel; 505 506 mr = availmemr; 507 for (u_int i = 0; i < cnt; i++, mr++) { 508 /* 509 * U-boot reserves a boot-page on multi-core chips. 510 * We need to make sure that we never disturb it. 511 */ 512 const paddr_t mr_end = mr->start + mr->size; 513 if (mr_end > boot_page && boot_page >= mr->start) { 514 /* 515 * Normally u-boot will put in at the end 516 * of memory. But in case it doesn't, deal 517 * with all possibilities. 518 */ 519 if (boot_page + PAGE_SIZE == mr_end) { 520 mr->size -= PAGE_SIZE; 521 } else if (boot_page == mr->start) { 522 mr->start += PAGE_SIZE; 523 mr->size -= PAGE_SIZE; 524 } else { 525 mr->size = boot_page - mr->start; 526 mr++; 527 for (u_int j = cnt; j > i + 1; j--) { 528 availmemr[j] = availmemr[j-1]; 529 } 530 cnt++; 531 mr->start = boot_page + PAGE_SIZE; 532 mr->size = mr_end - mr->start; 533 } 534 break; 535 } 536 } 537 538 /* 539 * Steal pages at the end of memory for the kernel message buffer. 540 */ 541 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 542 msgbuf_paddr = 543 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 544 545 /* 546 * Calculate physmem. 547 */ 548 for (u_int i = 0; i < cnt; i++) 549 physmem += atop(physmemr[i].size); 550 551 nmemr = cnt; 552 return physmemr[cnt-1].start + physmemr[cnt-1].size; 553 } 554 555 void 556 consinit(void) 557 { 558 static bool attached = false; 559 560 if (attached) 561 return; 562 attached = true; 563 564 if (comcnfreq == -1) { 565 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 566 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 567 comcnfreq = e500_sys_clk * plat_ratio; 568 printf(" comcnfreq=%u", comcnfreq); 569 } 570 571 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 572 COM_TYPE_NORMAL, comcnmode); 573 } 574 575 void 576 cpu_probe_cache(void) 577 { 578 struct cpu_info * const ci = curcpu(); 579 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 580 581 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 582 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 583 584 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 585 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 586 587 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 588 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 589 } else { 590 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 591 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 592 } 593 594 #ifdef DEBUG 595 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 596 if ((L1CSR_CE & l1csr0) == 0) 597 printf(" DC=off"); 598 599 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 600 if ((L1CSR_CE & l1csr1) == 0) 601 printf(" IC=off"); 602 #endif 603 } 604 605 static uint16_t 606 getsvr(void) 607 { 608 uint16_t svr = mfspr(SPR_SVR) >> 16; 609 610 svr &= ~0x8; /* clear security bit */ 611 switch (svr) { 612 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 613 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 614 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 615 default: return svr; 616 } 617 } 618 619 static const char * 620 socname(uint32_t svr) 621 { 622 svr &= ~0x80000; /* clear security bit */ 623 switch (svr >> 8) { 624 case SVR_MPC8533 >> 8: return "MPC8533"; 625 case SVR_MPC8536v1 >> 8: return "MPC8536"; 626 case SVR_MPC8541v1 >> 8: return "MPC8541"; 627 case SVR_MPC8543v2 >> 8: return "MPC8543"; 628 case SVR_MPC8544v1 >> 8: return "MPC8544"; 629 case SVR_MPC8545v2 >> 8: return "MPC8545"; 630 case SVR_MPC8547v2 >> 8: return "MPC8547"; 631 case SVR_MPC8548v2 >> 8: return "MPC8548"; 632 case SVR_MPC8555v1 >> 8: return "MPC8555"; 633 case SVR_MPC8568v1 >> 8: return "MPC8568"; 634 case SVR_MPC8567v1 >> 8: return "MPC8567"; 635 case SVR_MPC8572v1 >> 8: return "MPC8572"; 636 case SVR_P2020v2 >> 8: return "P2020"; 637 case SVR_P2010v2 >> 8: return "P2010"; 638 default: 639 panic("%s: unknown SVR %#x", __func__, svr); 640 } 641 } 642 643 static void 644 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 645 { 646 static const char units[16] = "KKKKKMMMMMGGGGGT"; 647 648 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 649 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 650 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 651 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 652 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 653 654 aprint_normal_dev(self, "%s:", name); 655 656 aprint_normal(" %u", nentries); 657 if (TLBCFG_AVAIL_P(tlbcfg)) { 658 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 659 minsize, maxsize, units[maxsize_log4k]); 660 } else { 661 aprint_normal(" fixed-size (%uKB)", minsize); 662 } 663 if (assoc == 0 || assoc == nentries) 664 aprint_normal(" fully"); 665 else 666 aprint_normal(" %u-way set", assoc); 667 aprint_normal(" associative entries\n"); 668 } 669 670 static void 671 cpu_print_info(struct cpu_info *ci) 672 { 673 uint64_t freq = board_info_get_number("processor-frequency"); 674 device_t self = ci->ci_dev; 675 676 char freqbuf[10]; 677 if (freq >= 999500000) { 678 const uint32_t freq32 = (freq + 500000) / 10000000; 679 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 680 freq32 / 100, freq32 % 100); 681 } else { 682 const uint32_t freq32 = (freq + 500000) / 1000000; 683 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 684 } 685 686 const uint32_t pvr = mfpvr(); 687 const uint32_t svr = mfspr(SPR_SVR); 688 const uint32_t pir = mfspr(SPR_PIR); 689 690 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 691 "ID %u%s\n", 692 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 693 (svr >> 4) & 15, svr & 15, 694 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 695 (pvr >> 4) & 15, pvr & 15, 696 pir, (pir == 0 ? " (Primary)" : "")); 697 698 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 699 aprint_normal_dev(self, 700 "%uKB/%uB %u-way L1 %s cache\n", 701 L1CFG_CSIZE_GET(l1cfg0) >> 10, 702 32 << L1CFG_CBSIZE_GET(l1cfg0), 703 L1CFG_CNWAY_GET(l1cfg0), 704 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 705 ? "data" : "unified"); 706 707 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 708 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 709 aprint_normal_dev(self, 710 "%uKB/%uB %u-way L1 %s cache\n", 711 L1CFG_CSIZE_GET(l1cfg1) >> 10, 712 32 << L1CFG_CBSIZE_GET(l1cfg1), 713 L1CFG_CNWAY_GET(l1cfg1), 714 "instruction"); 715 } 716 717 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 718 aprint_normal_dev(self, 719 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 720 MMUCFG_NTLBS_GET(mmucfg) + 1, 721 MMUCFG_NPIDS_GET(mmucfg), 722 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 723 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 724 725 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 726 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 727 } 728 729 #ifdef MULTIPROCESSOR 730 static void 731 e500_cpu_spinup(device_t self, struct cpu_info *ci) 732 { 733 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 734 struct pglist splist; 735 736 if (spinup_table_addr == 0) { 737 aprint_error_dev(self, "hatch failed (no spin-up table)"); 738 return; 739 } 740 741 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 742 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 743 const size_t id = cpu_index(ci); 744 volatile __cpuset_t * const hatchlings = &cpuset_info.cpus_hatched; 745 746 if (h->hatch_sp == 0) { 747 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 748 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 749 if (error) { 750 aprint_error_dev(self, 751 "unable to allocate hatch stack\n"); 752 return; 753 } 754 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 755 + PAGE_SIZE - CALLFRAMELEN; 756 } 757 758 759 for (size_t i = 1; e[i].entry_pir != 0; i++) { 760 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 761 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 762 if (e[i].entry_pir == ci->ci_cpuid) { 763 764 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 765 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 766 ci->ci_curpm = pmap_kernel(); 767 ci->ci_lasttb = cpu_info[0].ci_lasttb; 768 ci->ci_data.cpu_cc_freq = 769 cpu_info[0].ci_data.cpu_cc_freq; 770 771 h->hatch_self = self; 772 h->hatch_ci = ci; 773 h->hatch_running = -1; 774 h->hatch_pir = e[i].entry_pir; 775 h->hatch_hid0 = mfspr(SPR_HID0); 776 KASSERT(h->hatch_sp != 0); 777 /* 778 * Get new timebase. We don't want to deal with 779 * timebase crossing a 32-bit boundary so make sure 780 * that we have enough headroom to do the timebase 781 * synchronization. 782 */ 783 #define TBSYNC_SLOP 2000 784 uint32_t tbl; 785 uint32_t tbu; 786 do { 787 tbu = mfspr(SPR_RTBU); 788 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 789 } while (tbl < TBSYNC_SLOP); 790 791 h->hatch_tbu = tbu; 792 h->hatch_tbl = tbl; 793 __asm("sync;isync"); 794 dcache_wbinv((vaddr_t)h, sizeof(*h)); 795 796 #if 1 797 /* 798 * And here we go... 799 */ 800 e[i].entry_addr_lower = 801 (uint32_t)e500_spinup_trampoline; 802 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 803 __asm __volatile("sync;isync"); 804 __insn_barrier(); 805 806 for (u_int timo = 0; timo++ < 10000; ) { 807 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 808 if (e[i].entry_addr_lower == 3) { 809 printf( 810 "%s: cpu%u started in %u spins\n", 811 __func__, cpu_index(ci), timo); 812 break; 813 } 814 } 815 for (u_int timo = 0; timo++ < 10000; ) { 816 dcache_inv((vaddr_t)h, sizeof(*h)); 817 if (h->hatch_running == 0) { 818 printf( 819 "%s: cpu%u cracked in %u spins: (running=%d)\n", 820 __func__, cpu_index(ci), 821 timo, h->hatch_running); 822 break; 823 } 824 } 825 if (h->hatch_running == -1) { 826 aprint_error_dev(self, 827 "hatch failed (timeout): running=%d" 828 ", entry=%#x\n", 829 h->hatch_running, e[i].entry_addr_lower); 830 goto out; 831 } 832 #endif 833 834 /* 835 * First then we do is to synchronize timebases. 836 * TBSYNC_SLOP*16 should be more than enough 837 * instructions. 838 */ 839 while (tbl != mftbl()) 840 continue; 841 h->hatch_running = 1; 842 dcache_wbinv((vaddr_t)h, sizeof(*h)); 843 __asm("sync;isync"); 844 __insn_barrier(); 845 846 for (u_int timo = 10000; timo-- > 0; ) { 847 dcache_inv((vaddr_t)h, sizeof(*h)); 848 if (h->hatch_running > 1) 849 break; 850 } 851 if (h->hatch_running == 1) { 852 printf( 853 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 854 __func__, 855 ((int64_t)tbu << 32) + tbl, 856 (int64_t) 857 (((uint64_t)h->hatch_tbu << 32) 858 + (uint64_t)h->hatch_tbl), 859 h->hatch_running); 860 goto out; 861 } 862 printf( 863 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 864 __func__, 865 (int64_t) 866 (((uint64_t)h->hatch_tbu << 32) 867 + (uint64_t)h->hatch_tbl), 868 h->hatch_running); 869 /* 870 * Now we wait for the hatching to complete. 10ms 871 * should be long enough. 872 */ 873 for (u_int timo = 10000; timo-- > 0; ) { 874 if (CPUSET_HAS_P(*hatchlings, id)) { 875 aprint_normal_dev(self, 876 "hatch successful (%u spins, " 877 "timebase adjusted by %"PRId64")\n", 878 10000 - timo, 879 (int64_t) 880 (((uint64_t)h->hatch_tbu << 32) 881 + (uint64_t)h->hatch_tbl)); 882 goto out; 883 } 884 DELAY(1); 885 } 886 887 aprint_error_dev(self, 888 "hatch failed (timeout): running=%u\n", 889 h->hatch_running); 890 goto out; 891 } 892 } 893 894 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 895 ci->ci_cpuid); 896 out: 897 if (h->hatch_sp == 0) 898 uvm_pglistfree(&splist); 899 } 900 #endif 901 902 void 903 e500_cpu_hatch(struct cpu_info *ci) 904 { 905 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 906 907 /* 908 * Make sure interrupts are blocked. 909 */ 910 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 911 912 intr_cpu_hatch(ci); 913 914 cpu_print_info(ci); 915 916 /* 917 */ 918 } 919 920 static void 921 e500_cpu_attach(device_t self, u_int instance) 922 { 923 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 924 925 if (instance > 1) { 926 #if defined(MULTIPROCESSOR) 927 ci->ci_idepth = -1; 928 self->dv_private = ci; 929 930 ci->ci_cpuid = instance - (instance > 0); 931 ci->ci_dev = self; 932 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 933 934 mi_cpu_attach(ci); 935 936 intr_cpu_attach(ci); 937 cpu_evcnt_attach(ci); 938 939 e500_cpu_spinup(self, ci); 940 return; 941 #else 942 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 943 return; 944 #endif 945 } 946 947 self->dv_private = ci; 948 949 ci->ci_cpuid = instance - (instance > 0); 950 ci->ci_dev = self; 951 952 intr_cpu_attach(ci); 953 cpu_evcnt_attach(ci); 954 955 KASSERT(ci == curcpu()); 956 intr_cpu_hatch(ci); 957 958 cpu_print_info(ci); 959 } 960 961 void 962 e500_ipi_halt(void) 963 { 964 register_t msr, hid0; 965 966 msr = wrtee(0); 967 968 hid0 = mfspr(SPR_HID0); 969 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 970 mtspr(SPR_HID0, hid0); 971 972 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 973 mtmsr(msr); 974 for (;;); /* loop forever */ 975 } 976 977 978 static void 979 calltozero(void) 980 { 981 panic("call to 0 from %p", __builtin_return_address(0)); 982 } 983 984 void 985 initppc(vaddr_t startkernel, vaddr_t endkernel, 986 void *a0, void *a1, void *a2, void *a3) 987 { 988 struct cpu_info * const ci = curcpu(); 989 struct cpu_softc * const cpu = ci->ci_softc; 990 991 cn_tab = &e500_earlycons; 992 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 993 startkernel, endkernel, a0, a1, a2, a3); 994 995 /* 996 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 997 * DOZE is ok. 998 */ 999 const register_t hid0 = mfspr(SPR_HID0); 1000 mtspr(SPR_HID0, 1001 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1002 #ifdef CADMUS 1003 /* 1004 * Need to cache this from cadmus since we need to unmap cadmus since 1005 * it falls in the middle of kernel address space. 1006 */ 1007 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1008 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1009 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1010 printf(" cadmus_pci=%#x", cadmus_pci); 1011 printf(" cadmus_csr=%#x", cadmus_csr); 1012 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1013 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1014 e500_sys_clk *= 2; 1015 } 1016 #endif 1017 #ifdef PIXIS 1018 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1019 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1020 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1021 #ifndef SYS_CLK 1022 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1023 #else 1024 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1025 #endif 1026 #endif 1027 printf(" porpllsr=0x%08x", 1028 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1029 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1030 1031 /* 1032 * Make sure arguments are page aligned. 1033 */ 1034 startkernel = trunc_page(startkernel); 1035 endkernel = round_page(endkernel); 1036 1037 /* 1038 * Initialize the bus space tag used to access the 85xx general 1039 * utility registers. It doesn't need to be extent protected. 1040 * We know the GUR is mapped via a TLB1 entry so we add a limited 1041 * mapiodev which allows mappings in GUR space. 1042 */ 1043 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1044 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1045 bus_space_init(&gur_bst, NULL, NULL, 0); 1046 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1047 cpu->cpu_bst = &gur_bst; 1048 cpu->cpu_le_bst = &gur_le_bst; 1049 cpu->cpu_bsh = gur_bsh; 1050 1051 /* 1052 * Attach the console early, really early. 1053 */ 1054 consinit(); 1055 1056 /* 1057 * Reset the PIC to a known state. 1058 */ 1059 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1060 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1061 ; 1062 #if 0 1063 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1064 #endif 1065 printf(" openpic-reset(ctpr=%u)", 1066 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1067 1068 /* 1069 * fill in with an absolute branch to a routine that will panic. 1070 */ 1071 *(int *)0 = 0x48000002 | (int) calltozero; 1072 1073 /* 1074 * Get the cache sizes. 1075 */ 1076 cpu_probe_cache(); 1077 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1078 ci->ci_ci.dcache_size >> 10, 1079 ci->ci_ci.dcache_line_size, 1080 ci->ci_ci.icache_size >> 10, 1081 ci->ci_ci.icache_line_size); 1082 1083 /* 1084 * Now find out how much memory is attached 1085 */ 1086 pmemsize = memprobe(endkernel); 1087 cpu->cpu_highmem = pmemsize; 1088 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1089 1090 /* 1091 * Now we need cleanout the TLB of stuff that we don't need. 1092 */ 1093 e500_tlb_init(endkernel, pmemsize); 1094 printf(" e500_tlbinit(%#lx,%zuMB)", 1095 endkernel, (size_t) (pmemsize >> 20)); 1096 1097 /* 1098 * 1099 */ 1100 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1101 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1102 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1103 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1104 1105 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1106 1107 /* 1108 * Initialize the message buffer. 1109 */ 1110 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1111 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1112 1113 /* 1114 * Initialize exception vectors and interrupts 1115 */ 1116 exception_init(&e500_intrsw); 1117 1118 printf(" exception_init=%p", &e500_intrsw); 1119 1120 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1121 1122 /* 1123 * Set the page size. 1124 */ 1125 uvm_setpagesize(); 1126 1127 /* 1128 * Initialize the pmap. 1129 */ 1130 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1131 1132 /* 1133 * Let's take all the indirect calls via our stubs and patch 1134 * them to be direct calls. 1135 */ 1136 cpu_fixup_stubs(); 1137 #if 0 1138 /* 1139 * As a debug measure we can change the TLB entry that maps all of 1140 * memory to one that encompasses the 64KB with the kernel vectors. 1141 * All other pages will be soft faulted into the TLB as needed. 1142 */ 1143 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 1144 mtspr(SPR_MAS6, 0); 1145 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 1146 uint32_t mas0 = mfspr(SPR_MAS0); 1147 uint32_t mas1 = mfspr(SPR_MAS1); 1148 uint32_t mas2 = mfspr(SPR_MAS2); 1149 uint32_t mas3 = mfspr(SPR_MAS3); 1150 KASSERT(mas3 & MAS3_SW); 1151 KASSERT(mas3 & MAS3_SR); 1152 KASSERT(mas3 & MAS3_SX); 1153 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 1154 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 1155 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 1156 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 1157 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 1158 #if 1 1159 mtspr(SPR_MAS1, mas1); 1160 mtspr(SPR_MAS2, mas2); 1161 mtspr(SPR_MAS3, mas3); 1162 extern void tlbwe(void); 1163 tlbwe(); 1164 mtspr(SPR_MAS0, saved_mas0); 1165 printf("(ok)"); 1166 #endif 1167 #endif 1168 1169 /* 1170 * Set some more MD helpers 1171 */ 1172 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1173 cpu_md_ops.md_device_register = e500_device_register; 1174 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1175 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1176 #if NGPIO > 0 1177 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1178 #endif 1179 1180 printf(" initppc done!\n"); 1181 1182 /* 1183 * Look for the Book-E modules in the right place. 1184 */ 1185 module_machine = module_machine_booke; 1186 } 1187 1188 #ifdef MPC8548 1189 static const char * const mpc8548cds_extirq_names[] = { 1190 [0] = "pci inta", 1191 [1] = "pci intb", 1192 [2] = "pci intc", 1193 [3] = "pci intd", 1194 [4] = "irq4", 1195 [5] = "gige phy", 1196 [6] = "atm phy", 1197 [7] = "cpld", 1198 [8] = "irq8", 1199 [9] = "nvram", 1200 [10] = "debug", 1201 [11] = "pci2 inta", 1202 }; 1203 #endif 1204 1205 static const char * const mpc85xx_extirq_names[] = { 1206 [0] = "extirq 0", 1207 [1] = "extirq 1", 1208 [2] = "extirq 2", 1209 [3] = "extirq 3", 1210 [4] = "extirq 4", 1211 [5] = "extirq 5", 1212 [6] = "extirq 6", 1213 [7] = "extirq 7", 1214 [8] = "extirq 8", 1215 [9] = "extirq 9", 1216 [10] = "extirq 10", 1217 [11] = "extirq 11", 1218 }; 1219 1220 static void 1221 mpc85xx_extirq_setup(void) 1222 { 1223 #ifdef MPC8548 1224 const char * const * names = mpc8548cds_extirq_names; 1225 const size_t n = __arraycount(mpc8548cds_extirq_names); 1226 #else 1227 const char * const * names = mpc85xx_extirq_names; 1228 const size_t n = __arraycount(mpc85xx_extirq_names); 1229 #endif 1230 prop_array_t extirqs = prop_array_create_with_capacity(n); 1231 for (u_int i = 0; i < n; i++) { 1232 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1233 prop_array_set(extirqs, i, ps); 1234 prop_object_release(ps); 1235 } 1236 board_info_add_object("external-irqs", extirqs); 1237 prop_object_release(extirqs); 1238 } 1239 1240 static void 1241 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1242 { 1243 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1244 KASSERT(pci_intmap != NULL); 1245 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1246 KASSERT(mask != NULL); 1247 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1248 prop_object_release(mask); 1249 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1250 KASSERT(pn_ist != NULL); 1251 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1252 KASSERT(pn_intr != NULL); 1253 prop_dictionary_t entry = prop_dictionary_create(); 1254 KASSERT(entry != NULL); 1255 prop_dictionary_set(entry, "interrupt", pn_intr); 1256 prop_dictionary_set(entry, "type", pn_ist); 1257 prop_dictionary_set(pci_intmap, "000000", entry); 1258 prop_object_release(pn_intr); 1259 prop_object_release(entry); 1260 va_list ap; 1261 va_start(ap, inta); 1262 u_int intrinc = __LOWEST_SET_BIT(intmask); 1263 for (u_int i = 0; i < intmask; i += intrinc) { 1264 char prop_name[12]; 1265 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1266 entry = prop_dictionary_create(); 1267 KASSERT(entry != NULL); 1268 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1269 KASSERT(pn_intr != NULL); 1270 prop_dictionary_set(entry, "interrupt", pn_intr); 1271 prop_dictionary_set(entry, "type", pn_ist); 1272 prop_dictionary_set(pci_intmap, prop_name, entry); 1273 prop_object_release(pn_intr); 1274 prop_object_release(entry); 1275 } 1276 va_end(ap); 1277 prop_object_release(pn_ist); 1278 board_info_add_object(name, pci_intmap); 1279 prop_object_release(pci_intmap); 1280 } 1281 1282 void 1283 cpu_startup(void) 1284 { 1285 struct cpu_info * const ci = curcpu(); 1286 const uint16_t svr = getsvr(); 1287 1288 powersave = 0; /* we can do it but turn it on by default */ 1289 1290 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1291 1292 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1293 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1294 uint32_t e500_ratio = E500_RATIO_GET(v); 1295 1296 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1297 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1298 1299 ci->ci_khz = (cpu_freq + 500) / 1000; 1300 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1301 1302 board_info_add_number("my-id", svr); 1303 board_info_add_bool("pq3"); 1304 board_info_add_number("mem-size", pmemsize); 1305 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1306 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1307 uint32_t l2banks = l2siz >> 16; 1308 #ifdef MPC85555 1309 if (svr == (MPC8555v1 >> 16)) { 1310 l2siz >>= 1; 1311 l2banks >>= 1; 1312 } 1313 #endif 1314 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1315 if (boot_page & BPTR_EN) { 1316 bool found = false; 1317 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1318 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1319 * const bp = (void *)boot_page; 1320 bp <= dp; dp--) { 1321 if (*dp == boot_page) { 1322 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1323 spinup_table_addr = 1324 roundup2(spinup_table_addr, 32); 1325 board_info_add_number("mp-boot-page", 1326 boot_page); 1327 board_info_add_number("mp-spin-up-table", 1328 spinup_table_addr); 1329 printf("Found MP boot page @ %#"PRIxPADDR". " 1330 "Spin-up table @ %#"PRIxPTR"\n", 1331 boot_page, spinup_table_addr); 1332 found = true; 1333 break; 1334 } 1335 } 1336 if (!found) { 1337 printf("Found MP boot page @ %#"PRIxPADDR 1338 " with missing U-boot signature!\n", boot_page); 1339 board_info_add_number("mp-spin-up-table", 0); 1340 } 1341 } 1342 board_info_add_number("l2-cache-size", l2siz); 1343 board_info_add_number("l2-cache-line-size", 32); 1344 board_info_add_number("l2-cache-banks", l2banks); 1345 board_info_add_number("l2-cache-ways", 8); 1346 1347 board_info_add_number("processor-frequency", cpu_freq); 1348 board_info_add_number("bus-frequency", ccb_freq); 1349 board_info_add_number("pci-frequency", e500_sys_clk); 1350 board_info_add_number("timebase-frequency", ccb_freq / 8); 1351 1352 #ifdef CADMUS 1353 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1354 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1355 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1356 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1357 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1358 #else 1359 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1360 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1361 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1362 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1363 #endif 1364 1365 uint64_t macstnaddr = 1366 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1367 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1368 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1369 1370 #if NPCI > 0 && defined(PCI_MEMBASE) 1371 pcimem_ex = extent_create("pcimem", 1372 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1373 M_DEVBUF, NULL, 0, EX_WAITOK); 1374 #endif 1375 #if NPCI > 0 && defined(PCI_IOBASE) 1376 pciio_ex = extent_create("pciio", 1377 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1378 M_DEVBUF, NULL, 0, EX_WAITOK); 1379 #endif 1380 mpc85xx_extirq_setup(); 1381 /* 1382 * PCI-Express virtual wire interrupts on combined with 1383 * External IRQ0/1/2/3. 1384 */ 1385 switch (svr) { 1386 #if defined(MPC8548) 1387 case SVR_MPC8548v1 >> 16: 1388 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1389 IST_LEVEL, 0, 1, 2, 3); 1390 break; 1391 #endif 1392 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1393 case SVR_MPC8536v1 >> 16: 1394 case SVR_MPC8544v1 >> 16: 1395 case SVR_MPC8572v1 >> 16: 1396 case SVR_P2010v2 >> 16: 1397 case SVR_P2020v2 >> 16: 1398 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1399 0, 1, 2, 3); 1400 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1401 4, 5, 6, 7); 1402 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1403 8, 9, 10, 11); 1404 break; 1405 #endif 1406 } 1407 switch (svr) { 1408 #if defined(MPC8536) 1409 case SVR_MPC8536v1 >> 16: 1410 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1411 1, 2, 3, 4); 1412 break; 1413 #endif 1414 #if defined(MPC8544) 1415 case SVR_MPC8544v1 >> 16: 1416 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1417 0, 1, 2, 3); 1418 break; 1419 #endif 1420 #if defined(MPC8548) 1421 case SVR_MPC8548v1 >> 16: 1422 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1423 0, 1, 2, 3); 1424 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1425 11, 1, 2, 3); 1426 break; 1427 #endif 1428 } 1429 } 1430
Indexes created Mon Sep 29 21:09:56 GMT 2025