machdep.c revision 1.18
1 /* $NetBSD: machdep.c,v 1.18 2011/07/17 20:54:39 joerg Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <dev/cons.h> 70 71 #include <dev/ic/comreg.h> 72 #include <dev/ic/comvar.h> 73 74 #include <net/if.h> 75 #include <net/if_media.h> 76 #include <dev/mii/miivar.h> 77 78 #include <powerpc/cpuset.h> 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 struct uboot_bdinfo { 96 uint32_t bd_memstart; 97 uint32_t bd_memsize; 98 uint32_t bd_flashstart; 99 uint32_t bd_flashsize; 100 /*10*/ uint32_t bd_flashoffset; 101 uint32_t bd_sramstart; 102 uint32_t bd_sramsize; 103 uint32_t bd_immrbase; 104 /*20*/ uint32_t bd_bootflags; 105 uint32_t bd_ipaddr; 106 uint8_t bd_etheraddr[6]; 107 uint16_t bd_ethspeed; 108 /*30*/ uint32_t bd_intfreq; 109 uint32_t bd_cpufreq; 110 uint32_t bd_baudrate; 111 /*3c*/ uint8_t bd_etheraddr1[6]; 112 /*42*/ uint8_t bd_etheraddr2[6]; 113 /*48*/ uint8_t bd_etheraddr3[6]; 114 /*4e*/ uint16_t bd_pad; 115 }; 116 117 /* 118 * booke kernels need to set module_machine to this for modules to work. 119 */ 120 char module_machine_booke[] = "powerpc-booke"; 121 122 void initppc(vaddr_t, vaddr_t, void *, void *, void *, void *); 123 124 #define MEMREGIONS 4 125 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 126 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 127 static u_int nmemr; 128 129 #ifndef CONSFREQ 130 # define CONSFREQ -1 /* inherit from firmware */ 131 #endif 132 #ifndef CONSPEED 133 # define CONSPEED 115200 134 #endif 135 #ifndef CONMODE 136 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 137 #endif 138 #ifndef CONSADDR 139 # define CONSADDR DUART2_BASE 140 #endif 141 142 int comcnfreq = CONSFREQ; 143 int comcnspeed = CONSPEED; 144 tcflag_t comcnmode = CONMODE; 145 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 146 147 #if NPCI > 0 148 struct extent *pcimem_ex; 149 struct extent *pciio_ex; 150 #endif 151 152 struct powerpc_bus_space gur_bst = { 153 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 154 .pbs_offset = GUR_BASE, 155 .pbs_limit = GUR_SIZE, 156 }; 157 158 struct powerpc_bus_space gur_le_bst = { 159 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 160 .pbs_offset = GUR_BASE, 161 .pbs_limit = GUR_SIZE, 162 }; 163 164 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 165 166 #if defined(SYS_CLK) 167 static uint64_t e500_sys_clk = SYS_CLK; 168 #endif 169 #ifdef CADMUS 170 static uint8_t cadmus_pci; 171 static uint8_t cadmus_csr; 172 #ifndef SYS_CLK 173 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 174 #endif 175 #elif defined(PIXIS) 176 static const uint32_t pixis_spd_map[8] = { 177 [PX_SPD_33MHZ] = 33333333, 178 [PX_SPD_40MHZ] = 40000000, 179 [PX_SPD_50MHZ] = 50000000, 180 [PX_SPD_66MHZ] = 66666666, 181 [PX_SPD_83MHZ] = 83333333, 182 [PX_SPD_100MHZ] = 100000000, 183 [PX_SPD_133MHZ] = 133333333, 184 [PX_SPD_166MHZ] = 166666667, 185 }; 186 static uint8_t pixis_spd; 187 #ifndef SYS_CLK 188 static uint64_t e500_sys_clk; 189 #endif 190 #elif !defined(SYS_CLK) 191 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 192 #endif 193 194 static int e500_cngetc(dev_t); 195 static void e500_cnputc(dev_t, int); 196 197 static struct consdev e500_earlycons = { 198 .cn_getc = e500_cngetc, 199 .cn_putc = e500_cnputc, 200 .cn_pollc = nullcnpollc, 201 }; 202 203 /* 204 * List of port-specific devices to attach to the processor local bus. 205 */ 206 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 207 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 208 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 209 #if defined(MPC8572) || defined(P2020) 210 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 211 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 212 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 213 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 214 #endif 215 { "wdog" }, /* not a real device */ 216 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 217 1, { ISOURCE_DUART }, 218 1 + ilog2(DEVDISR_DUART) }, 219 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 220 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 221 1 + ilog2(DEVDISR_TSEC1) }, 222 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 223 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 224 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 225 1 + ilog2(DEVDISR_TSEC2), 226 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 227 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 228 #endif 229 #if defined(MPC8544) || defined(MPC8536) 230 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 231 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 232 1 + ilog2(DEVDISR_TSEC3), 233 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 234 #endif 235 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 236 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 237 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 238 1 + ilog2(DEVDISR_TSEC3), 239 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 240 SVR_P2020v2 >> 16 } }, 241 #endif 242 #if defined(MPC8548) || defined(MPC8572) 243 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 244 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 245 1 + ilog2(DEVDISR_TSEC4), 246 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 247 #endif 248 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 249 1, { ISOURCE_I2C }, 250 1 + ilog2(DEVDISR_I2C) }, 251 /* MPC8572 doesn't have any GPIO */ 252 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 253 1, { ISOURCE_GPIO }, 254 0, 255 { 0xffff, SVR_MPC8572v1 >> 16 } }, 256 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 257 1, { ISOURCE_DDR }, 258 1 + ilog2(DEVDISR_DDR_15), 259 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 260 #if defined(MPC8536) 261 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 262 1, { ISOURCE_DDR }, 263 1 + ilog2(DEVDISR_DDR_16), 264 { SVR_MPC8536v1 >> 16 } }, 265 #endif 266 #if defined(MPC8572) 267 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 268 1, { ISOURCE_DDR }, 269 1 + ilog2(DEVDISR_DDR_15), 270 { SVR_MPC8572v1 >> 16 } }, 271 { "ddrc", DDRC1_BASE, DDRC_SIZE, 2, 272 1, { ISOURCE_DDR }, 273 1 + ilog2(DEVDISR_DDR2_14), 274 { SVR_MPC8572v1 >> 16 } }, 275 #endif 276 { "lbc", LBC_BASE, LBC_SIZE, 0, 277 1, { ISOURCE_LBC }, 278 1 + ilog2(DEVDISR_LBC) }, 279 #if defined(MPC8544) || defined(MPC8536) 280 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 281 1, { ISOURCE_PCIEX }, 282 1 + ilog2(DEVDISR_PCIE), 283 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 284 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 285 1, { ISOURCE_PCIEX2 }, 286 1 + ilog2(DEVDISR_PCIE2), 287 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 288 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 289 1, { ISOURCE_PCIEX3 }, 290 1 + ilog2(DEVDISR_PCIE3), 291 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 292 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 293 1, { ISOURCE_PCI1 }, 294 1 + ilog2(DEVDISR_PCI1), 295 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 296 #endif 297 #ifdef MPC8548 298 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 299 1, { ISOURCE_PCIEX }, 300 1 + ilog2(DEVDISR_PCIE), 301 { SVR_MPC8548v1 >> 16 }, }, 302 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 303 1, { ISOURCE_PCI1 }, 304 1 + ilog2(DEVDISR_PCI1), 305 { SVR_MPC8548v1 >> 16 }, }, 306 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 307 1, { ISOURCE_PCI2 }, 308 1 + ilog2(DEVDISR_PCI2), 309 { SVR_MPC8548v1 >> 16 }, }, 310 #endif 311 #if defined(MPC8572) || defined(P2020) 312 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 313 1, { ISOURCE_PCIEX }, 314 1 + ilog2(DEVDISR_PCIE), 315 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 316 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 317 1, { ISOURCE_PCIEX2 }, 318 1 + ilog2(DEVDISR_PCIE2), 319 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 320 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 321 1, { ISOURCE_PCIEX3_MPC8572 }, 322 1 + ilog2(DEVDISR_PCIE3), 323 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 324 #endif 325 #if defined(MPC8536) || defined(P2020) 326 { "ehci", USB1_BASE, USB_SIZE, 1, 327 1, { ISOURCE_USB1 }, 328 1 + ilog2(DEVDISR_USB1), 329 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 330 #endif 331 #ifdef MPC8536 332 { "ehci", USB2_BASE, USB_SIZE, 2, 333 1, { ISOURCE_USB2 }, 334 1 + ilog2(DEVDISR_USB2), 335 { SVR_MPC8536v1 >> 16 }, }, 336 { "ehci", USB3_BASE, USB_SIZE, 3, 337 1, { ISOURCE_USB3 }, 338 1 + ilog2(DEVDISR_USB3), 339 { SVR_MPC8536v1 >> 16 }, }, 340 { "sata", SATA1_BASE, SATA_SIZE, 1, 341 1, { ISOURCE_SATA1 }, 342 1 + ilog2(DEVDISR_SATA1), 343 { SVR_MPC8536v1 >> 16 }, }, 344 { "sata", SATA2_BASE, SATA_SIZE, 2, 345 1, { ISOURCE_SATA2 }, 346 1 + ilog2(DEVDISR_SATA2), 347 { SVR_MPC8536v1 >> 16 }, }, 348 { "spi", SPI_BASE, SPI_SIZE, 0, 349 1, { ISOURCE_SPI }, 350 1 + ilog2(DEVDISR_SPI_15), 351 { SVR_MPC8536v1 >> 16 }, }, 352 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 353 1, { ISOURCE_ESDHC }, 354 1 + ilog2(DEVDISR_ESDHC_12), 355 { SVR_MPC8536v1 >> 16 }, }, 356 #endif 357 #if defined(P2020) 358 { "spi", SPI_BASE, SPI_SIZE, 0, 359 1, { ISOURCE_SPI }, 360 1 + ilog2(DEVDISR_SPI_28), 361 { SVR_P2020v2 >> 16 }, }, 362 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 363 1, { ISOURCE_ESDHC }, 364 1 + ilog2(DEVDISR_ESDHC_10), 365 { SVR_P2020v2 >> 16 }, }, 366 #endif 367 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 368 { NULL } 369 }; 370 371 static int 372 e500_cngetc(dev_t dv) 373 { 374 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 375 376 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 377 return -1; 378 379 return com0addr[com_data] & 0xff; 380 } 381 382 static void 383 e500_cnputc(dev_t dv, int c) 384 { 385 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 386 int timo = 150000; 387 388 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 389 ; 390 391 com0addr[com_data] = c; 392 __asm("mbar"); 393 394 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 395 ; 396 } 397 398 static void * 399 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 400 { 401 if (prefetchable) 402 return NULL; 403 if (pa < gur_bst.pbs_offset) 404 return NULL; 405 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 406 return NULL; 407 return (void *)pa; 408 } 409 410 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 411 412 static void 413 e500_cpu_reset(void) 414 { 415 __asm volatile("sync"); 416 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 417 __asm volatile("msync;isync"); 418 } 419 420 static psize_t 421 memprobe(vaddr_t endkernel) 422 { 423 phys_ram_seg_t *mr; 424 paddr_t boot_page = cpu_read_4(GUR_BPTR); 425 printf(" bptr=%"PRIxPADDR, boot_page); 426 if (boot_page & BPTR_EN) { 427 /* 428 * shift it to an address 429 */ 430 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 431 } else { 432 boot_page = ~(paddr_t)0; 433 } 434 435 /* 436 * First we need to find out how much physical memory we have. 437 * We could let our bootloader tell us, but it's almost as easy 438 * to ask the DDR memory controller. 439 */ 440 mr = physmemr; 441 #if 1 442 for (u_int i = 0; i < 4; i++) { 443 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 444 if (v & CS_CONFIG_EN) { 445 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 446 if (v == 0) 447 continue; 448 mr->start = BNDS_SA_GET(v); 449 mr->size = BNDS_SIZE_GET(v); 450 #if 0 451 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 452 mr - physmemr, mr->size, mr->start); 453 #endif 454 mr++; 455 } 456 } 457 458 if (mr == physmemr) 459 panic("no memory configured!"); 460 #else 461 mr->start = 0; 462 mr->size = 32 << 20; 463 mr++; 464 #endif 465 466 /* 467 * Sort memory regions from low to high and coalesce adjacent regions 468 */ 469 u_int cnt = mr - physmemr; 470 if (cnt > 1) { 471 for (u_int i = 0; i < cnt - 1; i++) { 472 for (u_int j = i + 1; j < cnt; j++) { 473 if (physmemr[j].start < physmemr[i].start) { 474 phys_ram_seg_t tmp = physmemr[i]; 475 physmemr[i] = physmemr[j]; 476 physmemr[j] = tmp; 477 } 478 } 479 } 480 mr = physmemr; 481 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 482 if (mr->start + mr->size == mr[1].start) { 483 mr->size += mr[1].size; 484 for (u_int j = 1; i + j + 1 < cnt; j++) 485 mr[j] = mr[j+1]; 486 cnt--; 487 } 488 } 489 } else if (cnt == 0) { 490 panic("%s: no memory found", __func__); 491 } 492 493 /* 494 * Copy physical memory to available memory. 495 */ 496 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 497 498 /* 499 * Adjust available memory to skip kernel at start of memory. 500 */ 501 availmemr[0].size -= endkernel - availmemr[0].start; 502 availmemr[0].start = endkernel; 503 504 mr = availmemr; 505 for (u_int i = 0; i < cnt; i++, mr++) { 506 /* 507 * U-boot reserves a boot-page on multi-core chips. 508 * We need to make sure that we never disturb it. 509 */ 510 const paddr_t mr_end = mr->start + mr->size; 511 if (mr_end > boot_page && boot_page >= mr->start) { 512 /* 513 * Normally u-boot will put in at the end 514 * of memory. But in case it doesn't, deal 515 * with all possibilities. 516 */ 517 if (boot_page + PAGE_SIZE == mr_end) { 518 mr->size -= PAGE_SIZE; 519 } else if (boot_page == mr->start) { 520 mr->start += PAGE_SIZE; 521 mr->size -= PAGE_SIZE; 522 } else { 523 mr->size = boot_page - mr->start; 524 mr++; 525 for (u_int j = cnt; j > i + 1; j--) { 526 availmemr[j] = availmemr[j-1]; 527 } 528 cnt++; 529 mr->start = boot_page + PAGE_SIZE; 530 mr->size = mr_end - mr->start; 531 } 532 break; 533 } 534 } 535 536 /* 537 * Steal pages at the end of memory for the kernel message buffer. 538 */ 539 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 540 msgbuf_paddr = 541 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 542 543 /* 544 * Calculate physmem. 545 */ 546 for (u_int i = 0; i < cnt; i++) 547 physmem += atop(physmemr[i].size); 548 549 nmemr = cnt; 550 return physmemr[cnt-1].start + physmemr[cnt-1].size; 551 } 552 553 void 554 consinit(void) 555 { 556 static bool attached = false; 557 558 if (attached) 559 return; 560 attached = true; 561 562 if (comcnfreq == -1) { 563 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 564 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 565 comcnfreq = e500_sys_clk * plat_ratio; 566 printf(" comcnfreq=%u", comcnfreq); 567 } 568 569 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 570 COM_TYPE_NORMAL, comcnmode); 571 } 572 573 void 574 cpu_probe_cache(void) 575 { 576 struct cpu_info * const ci = curcpu(); 577 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 578 579 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 580 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 581 582 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 583 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 584 585 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 586 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 587 } else { 588 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 589 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 590 } 591 592 #ifdef DEBUG 593 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 594 if ((L1CSR_CE & l1csr0) == 0) 595 printf(" DC=off"); 596 597 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 598 if ((L1CSR_CE & l1csr1) == 0) 599 printf(" IC=off"); 600 #endif 601 } 602 603 static uint16_t 604 getsvr(void) 605 { 606 uint16_t svr = mfspr(SPR_SVR) >> 16; 607 608 svr &= ~0x8; /* clear security bit */ 609 switch (svr) { 610 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 611 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 612 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 613 default: return svr; 614 } 615 } 616 617 static const char * 618 socname(uint32_t svr) 619 { 620 svr &= ~0x80000; /* clear security bit */ 621 switch (svr >> 8) { 622 case SVR_MPC8533 >> 8: return "MPC8533"; 623 case SVR_MPC8536v1 >> 8: return "MPC8536"; 624 case SVR_MPC8541v1 >> 8: return "MPC8541"; 625 case SVR_MPC8543v2 >> 8: return "MPC8543"; 626 case SVR_MPC8544v1 >> 8: return "MPC8544"; 627 case SVR_MPC8545v2 >> 8: return "MPC8545"; 628 case SVR_MPC8547v2 >> 8: return "MPC8547"; 629 case SVR_MPC8548v2 >> 8: return "MPC8548"; 630 case SVR_MPC8555v1 >> 8: return "MPC8555"; 631 case SVR_MPC8568v1 >> 8: return "MPC8568"; 632 case SVR_MPC8567v1 >> 8: return "MPC8567"; 633 case SVR_MPC8572v1 >> 8: return "MPC8572"; 634 case SVR_P2020v2 >> 8: return "P2020"; 635 case SVR_P2010v2 >> 8: return "P2010"; 636 default: 637 panic("%s: unknown SVR %#x", __func__, svr); 638 } 639 } 640 641 static void 642 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 643 { 644 static const char units[16] = "KKKKKMMMMMGGGGGT"; 645 646 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 647 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 648 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 649 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 650 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 651 652 aprint_normal_dev(self, "%s:", name); 653 654 aprint_normal(" %u", nentries); 655 if (TLBCFG_AVAIL_P(tlbcfg)) { 656 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 657 minsize, maxsize, units[maxsize_log4k]); 658 } else { 659 aprint_normal(" fixed-size (%uKB)", minsize); 660 } 661 if (assoc == 0 || assoc == nentries) 662 aprint_normal(" fully"); 663 else 664 aprint_normal(" %u-way set", assoc); 665 aprint_normal(" associative entries\n"); 666 } 667 668 static void 669 cpu_print_info(struct cpu_info *ci) 670 { 671 uint64_t freq = board_info_get_number("processor-frequency"); 672 device_t self = ci->ci_dev; 673 674 char freqbuf[10]; 675 if (freq >= 999500000) { 676 const uint32_t freq32 = (freq + 500000) / 10000000; 677 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 678 freq32 / 100, freq32 % 100); 679 } else { 680 const uint32_t freq32 = (freq + 500000) / 1000000; 681 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 682 } 683 684 const uint32_t pvr = mfpvr(); 685 const uint32_t svr = mfspr(SPR_SVR); 686 const uint32_t pir = mfspr(SPR_PIR); 687 688 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 689 "ID %u%s\n", 690 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 691 (svr >> 4) & 15, svr & 15, 692 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 693 (pvr >> 4) & 15, pvr & 15, 694 pir, (pir == 0 ? " (Primary)" : "")); 695 696 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 697 aprint_normal_dev(self, 698 "%uKB/%uB %u-way L1 %s cache\n", 699 L1CFG_CSIZE_GET(l1cfg0) >> 10, 700 32 << L1CFG_CBSIZE_GET(l1cfg0), 701 L1CFG_CNWAY_GET(l1cfg0), 702 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 703 ? "data" : "unified"); 704 705 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 706 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 707 aprint_normal_dev(self, 708 "%uKB/%uB %u-way L1 %s cache\n", 709 L1CFG_CSIZE_GET(l1cfg1) >> 10, 710 32 << L1CFG_CBSIZE_GET(l1cfg1), 711 L1CFG_CNWAY_GET(l1cfg1), 712 "instruction"); 713 } 714 715 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 716 aprint_normal_dev(self, 717 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 718 MMUCFG_NTLBS_GET(mmucfg) + 1, 719 MMUCFG_NPIDS_GET(mmucfg), 720 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 721 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 722 723 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 724 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 725 } 726 727 #ifdef MULTIPROCESSOR 728 static void 729 e500_cpu_spinup(device_t self, struct cpu_info *ci) 730 { 731 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 732 struct pglist splist; 733 734 if (spinup_table_addr == 0) { 735 aprint_error_dev(self, "hatch failed (no spin-up table)"); 736 return; 737 } 738 739 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 740 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 741 const size_t id = cpu_index(ci); 742 volatile __cpuset_t * const hatchlings = &cpuset_info.cpus_hatched; 743 744 if (h->hatch_sp == 0) { 745 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 746 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 747 if (error) { 748 aprint_error_dev(self, 749 "unable to allocate hatch stack\n"); 750 return; 751 } 752 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 753 + PAGE_SIZE - CALLFRAMELEN; 754 } 755 756 757 for (size_t i = 1; e[i].entry_pir != 0; i++) { 758 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 759 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 760 if (e[i].entry_pir == ci->ci_cpuid) { 761 762 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 763 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 764 ci->ci_curpm = pmap_kernel(); 765 ci->ci_lasttb = cpu_info[0].ci_lasttb; 766 ci->ci_data.cpu_cc_freq = 767 cpu_info[0].ci_data.cpu_cc_freq; 768 769 h->hatch_self = self; 770 h->hatch_ci = ci; 771 h->hatch_running = -1; 772 h->hatch_pir = e[i].entry_pir; 773 h->hatch_hid0 = mfspr(SPR_HID0); 774 KASSERT(h->hatch_sp != 0); 775 /* 776 * Get new timebase. We don't want to deal with 777 * timebase crossing a 32-bit boundary so make sure 778 * that we have enough headroom to do the timebase 779 * synchronization. 780 */ 781 #define TBSYNC_SLOP 2000 782 uint32_t tbl; 783 uint32_t tbu; 784 do { 785 tbu = mfspr(SPR_RTBU); 786 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 787 } while (tbl < TBSYNC_SLOP); 788 789 h->hatch_tbu = tbu; 790 h->hatch_tbl = tbl; 791 __asm("sync;isync"); 792 dcache_wbinv((vaddr_t)h, sizeof(*h)); 793 794 #if 1 795 /* 796 * And here we go... 797 */ 798 e[i].entry_addr_lower = 799 (uint32_t)e500_spinup_trampoline; 800 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 801 __asm __volatile("sync;isync"); 802 __insn_barrier(); 803 804 for (u_int timo = 0; timo++ < 10000; ) { 805 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 806 if (e[i].entry_addr_lower == 3) { 807 printf( 808 "%s: cpu%u started in %u spins\n", 809 __func__, cpu_index(ci), timo); 810 break; 811 } 812 } 813 for (u_int timo = 0; timo++ < 10000; ) { 814 dcache_inv((vaddr_t)h, sizeof(*h)); 815 if (h->hatch_running == 0) { 816 printf( 817 "%s: cpu%u cracked in %u spins: (running=%d)\n", 818 __func__, cpu_index(ci), 819 timo, h->hatch_running); 820 break; 821 } 822 } 823 if (h->hatch_running == -1) { 824 aprint_error_dev(self, 825 "hatch failed (timeout): running=%d" 826 ", entry=%#x\n", 827 h->hatch_running, e[i].entry_addr_lower); 828 goto out; 829 } 830 #endif 831 832 /* 833 * First then we do is to synchronize timebases. 834 * TBSYNC_SLOP*16 should be more than enough 835 * instructions. 836 */ 837 while (tbl != mftbl()) 838 continue; 839 h->hatch_running = 1; 840 dcache_wbinv((vaddr_t)h, sizeof(*h)); 841 __asm("sync;isync"); 842 __insn_barrier(); 843 844 for (u_int timo = 10000; timo-- > 0; ) { 845 dcache_inv((vaddr_t)h, sizeof(*h)); 846 if (h->hatch_running > 1) 847 break; 848 } 849 if (h->hatch_running == 1) { 850 printf( 851 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 852 __func__, 853 ((int64_t)tbu << 32) + tbl, 854 (int64_t) 855 (((uint64_t)h->hatch_tbu << 32) 856 + (uint64_t)h->hatch_tbl), 857 h->hatch_running); 858 goto out; 859 } 860 printf( 861 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 862 __func__, 863 (int64_t) 864 (((uint64_t)h->hatch_tbu << 32) 865 + (uint64_t)h->hatch_tbl), 866 h->hatch_running); 867 /* 868 * Now we wait for the hatching to complete. 10ms 869 * should be long enough. 870 */ 871 for (u_int timo = 10000; timo-- > 0; ) { 872 if (CPUSET_HAS_P(*hatchlings, id)) { 873 aprint_normal_dev(self, 874 "hatch successful (%u spins, " 875 "timebase adjusted by %"PRId64")\n", 876 10000 - timo, 877 (int64_t) 878 (((uint64_t)h->hatch_tbu << 32) 879 + (uint64_t)h->hatch_tbl)); 880 goto out; 881 } 882 DELAY(1); 883 } 884 885 aprint_error_dev(self, 886 "hatch failed (timeout): running=%u\n", 887 h->hatch_running); 888 goto out; 889 } 890 } 891 892 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 893 ci->ci_cpuid); 894 out: 895 if (h->hatch_sp == 0) 896 uvm_pglistfree(&splist); 897 } 898 #endif 899 900 void 901 e500_cpu_hatch(struct cpu_info *ci) 902 { 903 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 904 905 /* 906 * Make sure interrupts are blocked. 907 */ 908 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 909 910 intr_cpu_hatch(ci); 911 912 cpu_print_info(ci); 913 914 /* 915 */ 916 } 917 918 static void 919 e500_cpu_attach(device_t self, u_int instance) 920 { 921 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 922 923 if (instance > 1) { 924 #if defined(MULTIPROCESSOR) 925 ci->ci_idepth = -1; 926 self->dv_private = ci; 927 928 ci->ci_cpuid = instance - (instance > 0); 929 ci->ci_dev = self; 930 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 931 932 mi_cpu_attach(ci); 933 934 intr_cpu_attach(ci); 935 cpu_evcnt_attach(ci); 936 937 e500_cpu_spinup(self, ci); 938 return; 939 #else 940 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 941 return; 942 #endif 943 } 944 945 self->dv_private = ci; 946 947 ci->ci_cpuid = instance - (instance > 0); 948 ci->ci_dev = self; 949 950 intr_cpu_attach(ci); 951 cpu_evcnt_attach(ci); 952 953 KASSERT(ci == curcpu()); 954 intr_cpu_hatch(ci); 955 956 cpu_print_info(ci); 957 } 958 959 void 960 e500_ipi_halt(void) 961 { 962 register_t msr, hid0; 963 964 msr = wrtee(0); 965 966 hid0 = mfspr(SPR_HID0); 967 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 968 mtspr(SPR_HID0, hid0); 969 970 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 971 mtmsr(msr); 972 for (;;); /* loop forever */ 973 } 974 975 976 static void 977 calltozero(void) 978 { 979 panic("call to 0 from %p", __builtin_return_address(0)); 980 } 981 982 void 983 initppc(vaddr_t startkernel, vaddr_t endkernel, 984 void *a0, void *a1, void *a2, void *a3) 985 { 986 struct cpu_info * const ci = curcpu(); 987 struct cpu_softc * const cpu = ci->ci_softc; 988 989 cn_tab = &e500_earlycons; 990 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 991 startkernel, endkernel, a0, a1, a2, a3); 992 993 /* 994 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 995 * DOZE is ok. 996 */ 997 const register_t hid0 = mfspr(SPR_HID0); 998 mtspr(SPR_HID0, 999 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1000 #ifdef CADMUS 1001 /* 1002 * Need to cache this from cadmus since we need to unmap cadmus since 1003 * it falls in the middle of kernel address space. 1004 */ 1005 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1006 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1007 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1008 printf(" cadmus_pci=%#x", cadmus_pci); 1009 printf(" cadmus_csr=%#x", cadmus_csr); 1010 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1011 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1012 e500_sys_clk *= 2; 1013 } 1014 #endif 1015 #ifdef PIXIS 1016 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1017 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1018 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1019 #ifndef SYS_CLK 1020 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1021 #else 1022 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1023 #endif 1024 #endif 1025 printf(" porpllsr=0x%08x", 1026 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1027 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1028 1029 /* 1030 * Make sure arguments are page aligned. 1031 */ 1032 startkernel = trunc_page(startkernel); 1033 endkernel = round_page(endkernel); 1034 1035 /* 1036 * Initialize the bus space tag used to access the 85xx general 1037 * utility registers. It doesn't need to be extent protected. 1038 * We know the GUR is mapped via a TLB1 entry so we add a limited 1039 * mapiodev which allows mappings in GUR space. 1040 */ 1041 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1042 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1043 bus_space_init(&gur_bst, NULL, NULL, 0); 1044 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1045 cpu->cpu_bst = &gur_bst; 1046 cpu->cpu_le_bst = &gur_le_bst; 1047 cpu->cpu_bsh = gur_bsh; 1048 1049 /* 1050 * Attach the console early, really early. 1051 */ 1052 consinit(); 1053 1054 /* 1055 * Reset the PIC to a known state. 1056 */ 1057 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1058 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1059 ; 1060 #if 0 1061 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1062 #endif 1063 printf(" openpic-reset(ctpr=%u)", 1064 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1065 1066 /* 1067 * fill in with an absolute branch to a routine that will panic. 1068 */ 1069 *(int *)0 = 0x48000002 | (int) calltozero; 1070 1071 /* 1072 * Get the cache sizes. 1073 */ 1074 cpu_probe_cache(); 1075 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1076 ci->ci_ci.dcache_size >> 10, 1077 ci->ci_ci.dcache_line_size, 1078 ci->ci_ci.icache_size >> 10, 1079 ci->ci_ci.icache_line_size); 1080 1081 /* 1082 * Now find out how much memory is attached 1083 */ 1084 pmemsize = memprobe(endkernel); 1085 cpu->cpu_highmem = pmemsize; 1086 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1087 1088 /* 1089 * Now we need cleanout the TLB of stuff that we don't need. 1090 */ 1091 e500_tlb_init(endkernel, pmemsize); 1092 printf(" e500_tlbinit(%#lx,%zuMB)", 1093 endkernel, (size_t) (pmemsize >> 20)); 1094 1095 /* 1096 * 1097 */ 1098 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1099 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1100 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1101 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1102 1103 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1104 1105 /* 1106 * Initialize the message buffer. 1107 */ 1108 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1109 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1110 1111 /* 1112 * Initialize exception vectors and interrupts 1113 */ 1114 exception_init(&e500_intrsw); 1115 1116 printf(" exception_init=%p", &e500_intrsw); 1117 1118 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1119 1120 /* 1121 * Set the page size. 1122 */ 1123 uvm_setpagesize(); 1124 1125 /* 1126 * Initialize the pmap. 1127 */ 1128 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1129 1130 /* 1131 * Let's take all the indirect calls via our stubs and patch 1132 * them to be direct calls. 1133 */ 1134 cpu_fixup_stubs(); 1135 #if 0 1136 /* 1137 * As a debug measure we can change the TLB entry that maps all of 1138 * memory to one that encompasses the 64KB with the kernel vectors. 1139 * All other pages will be soft faulted into the TLB as needed. 1140 */ 1141 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 1142 mtspr(SPR_MAS6, 0); 1143 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 1144 uint32_t mas0 = mfspr(SPR_MAS0); 1145 uint32_t mas1 = mfspr(SPR_MAS1); 1146 uint32_t mas2 = mfspr(SPR_MAS2); 1147 uint32_t mas3 = mfspr(SPR_MAS3); 1148 KASSERT(mas3 & MAS3_SW); 1149 KASSERT(mas3 & MAS3_SR); 1150 KASSERT(mas3 & MAS3_SX); 1151 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 1152 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 1153 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 1154 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 1155 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 1156 #if 1 1157 mtspr(SPR_MAS1, mas1); 1158 mtspr(SPR_MAS2, mas2); 1159 mtspr(SPR_MAS3, mas3); 1160 extern void tlbwe(void); 1161 tlbwe(); 1162 mtspr(SPR_MAS0, saved_mas0); 1163 printf("(ok)"); 1164 #endif 1165 #endif 1166 1167 /* 1168 * Set some more MD helpers 1169 */ 1170 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1171 cpu_md_ops.md_device_register = e500_device_register; 1172 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1173 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1174 #if NGPIO > 0 1175 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1176 #endif 1177 1178 printf(" initppc done!\n"); 1179 1180 /* 1181 * Look for the Book-E modules in the right place. 1182 */ 1183 module_machine = module_machine_booke; 1184 } 1185 1186 #ifdef MPC8548 1187 static const char * const mpc8548cds_extirq_names[] = { 1188 [0] = "pci inta", 1189 [1] = "pci intb", 1190 [2] = "pci intc", 1191 [3] = "pci intd", 1192 [4] = "irq4", 1193 [5] = "gige phy", 1194 [6] = "atm phy", 1195 [7] = "cpld", 1196 [8] = "irq8", 1197 [9] = "nvram", 1198 [10] = "debug", 1199 [11] = "pci2 inta", 1200 }; 1201 #endif 1202 1203 static const char * const mpc85xx_extirq_names[] = { 1204 [0] = "extirq 0", 1205 [1] = "extirq 1", 1206 [2] = "extirq 2", 1207 [3] = "extirq 3", 1208 [4] = "extirq 4", 1209 [5] = "extirq 5", 1210 [6] = "extirq 6", 1211 [7] = "extirq 7", 1212 [8] = "extirq 8", 1213 [9] = "extirq 9", 1214 [10] = "extirq 10", 1215 [11] = "extirq 11", 1216 }; 1217 1218 static void 1219 mpc85xx_extirq_setup(void) 1220 { 1221 #ifdef MPC8548 1222 const char * const * names = mpc8548cds_extirq_names; 1223 const size_t n = __arraycount(mpc8548cds_extirq_names); 1224 #else 1225 const char * const * names = mpc85xx_extirq_names; 1226 const size_t n = __arraycount(mpc85xx_extirq_names); 1227 #endif 1228 prop_array_t extirqs = prop_array_create_with_capacity(n); 1229 for (u_int i = 0; i < n; i++) { 1230 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1231 prop_array_set(extirqs, i, ps); 1232 prop_object_release(ps); 1233 } 1234 board_info_add_object("external-irqs", extirqs); 1235 prop_object_release(extirqs); 1236 } 1237 1238 static void 1239 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1240 { 1241 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1242 KASSERT(pci_intmap != NULL); 1243 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1244 KASSERT(mask != NULL); 1245 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1246 prop_object_release(mask); 1247 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1248 KASSERT(pn_ist != NULL); 1249 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1250 KASSERT(pn_intr != NULL); 1251 prop_dictionary_t entry = prop_dictionary_create(); 1252 KASSERT(entry != NULL); 1253 prop_dictionary_set(entry, "interrupt", pn_intr); 1254 prop_dictionary_set(entry, "type", pn_ist); 1255 prop_dictionary_set(pci_intmap, "000000", entry); 1256 prop_object_release(pn_intr); 1257 prop_object_release(entry); 1258 va_list ap; 1259 va_start(ap, inta); 1260 u_int intrinc = __LOWEST_SET_BIT(intmask); 1261 for (u_int i = 0; i < intmask; i += intrinc) { 1262 char prop_name[12]; 1263 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1264 entry = prop_dictionary_create(); 1265 KASSERT(entry != NULL); 1266 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1267 KASSERT(pn_intr != NULL); 1268 prop_dictionary_set(entry, "interrupt", pn_intr); 1269 prop_dictionary_set(entry, "type", pn_ist); 1270 prop_dictionary_set(pci_intmap, prop_name, entry); 1271 prop_object_release(pn_intr); 1272 prop_object_release(entry); 1273 } 1274 va_end(ap); 1275 prop_object_release(pn_ist); 1276 board_info_add_object(name, pci_intmap); 1277 prop_object_release(pci_intmap); 1278 } 1279 1280 void 1281 cpu_startup(void) 1282 { 1283 struct cpu_info * const ci = curcpu(); 1284 const uint16_t svr = getsvr(); 1285 1286 powersave = 0; /* we can do it but turn it on by default */ 1287 1288 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1289 1290 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1291 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1292 uint32_t e500_ratio = E500_RATIO_GET(v); 1293 1294 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1295 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1296 1297 ci->ci_khz = (cpu_freq + 500) / 1000; 1298 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1299 1300 board_info_add_number("my-id", svr); 1301 board_info_add_bool("pq3"); 1302 board_info_add_number("mem-size", pmemsize); 1303 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1304 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1305 uint32_t l2banks = l2siz >> 16; 1306 #ifdef MPC85555 1307 if (svr == (MPC8555v1 >> 16)) { 1308 l2siz >>= 1; 1309 l2banks >>= 1; 1310 } 1311 #endif 1312 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1313 if (boot_page & BPTR_EN) { 1314 bool found = false; 1315 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1316 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1317 * const bp = (void *)boot_page; 1318 bp <= dp; dp--) { 1319 if (*dp == boot_page) { 1320 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1321 spinup_table_addr = 1322 roundup2(spinup_table_addr, 32); 1323 board_info_add_number("mp-boot-page", 1324 boot_page); 1325 board_info_add_number("mp-spin-up-table", 1326 spinup_table_addr); 1327 printf("Found MP boot page @ %#"PRIxPADDR". " 1328 "Spin-up table @ %#"PRIxPTR"\n", 1329 boot_page, spinup_table_addr); 1330 found = true; 1331 break; 1332 } 1333 } 1334 if (!found) { 1335 printf("Found MP boot page @ %#"PRIxPADDR 1336 " with missing U-boot signature!\n", boot_page); 1337 board_info_add_number("mp-spin-up-table", 0); 1338 } 1339 } 1340 board_info_add_number("l2-cache-size", l2siz); 1341 board_info_add_number("l2-cache-line-size", 32); 1342 board_info_add_number("l2-cache-banks", l2banks); 1343 board_info_add_number("l2-cache-ways", 8); 1344 1345 board_info_add_number("processor-frequency", cpu_freq); 1346 board_info_add_number("bus-frequency", ccb_freq); 1347 board_info_add_number("pci-frequency", e500_sys_clk); 1348 board_info_add_number("timebase-frequency", ccb_freq / 8); 1349 1350 #ifdef CADMUS 1351 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1352 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1353 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1354 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1355 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1356 #else 1357 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1358 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1359 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1360 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1361 #endif 1362 1363 uint64_t macstnaddr = 1364 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1365 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1366 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1367 1368 #if NPCI > 0 && defined(PCI_MEMBASE) 1369 pcimem_ex = extent_create("pcimem", 1370 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1371 M_DEVBUF, NULL, 0, EX_WAITOK); 1372 #endif 1373 #if NPCI > 0 && defined(PCI_IOBASE) 1374 pciio_ex = extent_create("pciio", 1375 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1376 M_DEVBUF, NULL, 0, EX_WAITOK); 1377 #endif 1378 mpc85xx_extirq_setup(); 1379 /* 1380 * PCI-Express virtual wire interrupts on combined with 1381 * External IRQ0/1/2/3. 1382 */ 1383 switch (svr) { 1384 #if defined(MPC8548) 1385 case SVR_MPC8548v1 >> 16: 1386 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1387 IST_LEVEL, 0, 1, 2, 3); 1388 break; 1389 #endif 1390 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1391 case SVR_MPC8536v1 >> 16: 1392 case SVR_MPC8544v1 >> 16: 1393 case SVR_MPC8572v1 >> 16: 1394 case SVR_P2010v2 >> 16: 1395 case SVR_P2020v2 >> 16: 1396 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1397 0, 1, 2, 3); 1398 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1399 4, 5, 6, 7); 1400 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1401 8, 9, 10, 11); 1402 break; 1403 #endif 1404 } 1405 switch (svr) { 1406 #if defined(MPC8536) 1407 case SVR_MPC8536v1 >> 16: 1408 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1409 1, 2, 3, 4); 1410 break; 1411 #endif 1412 #if defined(MPC8544) 1413 case SVR_MPC8544v1 >> 16: 1414 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1415 0, 1, 2, 3); 1416 break; 1417 #endif 1418 #if defined(MPC8548) 1419 case SVR_MPC8548v1 >> 16: 1420 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1421 0, 1, 2, 3); 1422 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1423 11, 1, 2, 3); 1424 break; 1425 #endif 1426 } 1427 } 1428
Indexes created Tue Oct 21 15:09:54 GMT 2025