machdep.c revision 1.26
1 /* $NetBSD: machdep.c,v 1.26 2012/07/17 01:36:12 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_altivec.h" 42 #include "opt_ddb.h" 43 #include "opt_mpc85xx.h" 44 #include "opt_pci.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <dev/cons.h> 70 71 #include <dev/ic/comreg.h> 72 #include <dev/ic/comvar.h> 73 74 #include <net/if.h> 75 #include <net/if_media.h> 76 #include <dev/mii/miivar.h> 77 78 #include <powerpc/cpuset.h> 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 struct uboot_bdinfo { 96 uint32_t bd_memstart; 97 uint32_t bd_memsize; 98 uint32_t bd_flashstart; 99 uint32_t bd_flashsize; 100 /*10*/ uint32_t bd_flashoffset; 101 uint32_t bd_sramstart; 102 uint32_t bd_sramsize; 103 uint32_t bd_immrbase; 104 /*20*/ uint32_t bd_bootflags; 105 uint32_t bd_ipaddr; 106 uint8_t bd_etheraddr[6]; 107 uint16_t bd_ethspeed; 108 /*30*/ uint32_t bd_intfreq; 109 uint32_t bd_cpufreq; 110 uint32_t bd_baudrate; 111 /*3c*/ uint8_t bd_etheraddr1[6]; 112 /*42*/ uint8_t bd_etheraddr2[6]; 113 /*48*/ uint8_t bd_etheraddr3[6]; 114 /*4e*/ uint16_t bd_pad; 115 }; 116 117 /* 118 * booke kernels need to set module_machine to this for modules to work. 119 */ 120 char module_machine_booke[] = "powerpc-booke"; 121 122 void initppc(vaddr_t, vaddr_t, void *, void *, void *, void *); 123 124 #define MEMREGIONS 4 125 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 126 phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 127 static u_int nmemr; 128 129 #ifndef CONSFREQ 130 # define CONSFREQ -1 /* inherit from firmware */ 131 #endif 132 #ifndef CONSPEED 133 # define CONSPEED 115200 134 #endif 135 #ifndef CONMODE 136 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 137 #endif 138 #ifndef CONSADDR 139 # define CONSADDR DUART2_BASE 140 #endif 141 142 int comcnfreq = CONSFREQ; 143 int comcnspeed = CONSPEED; 144 tcflag_t comcnmode = CONMODE; 145 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 146 147 #if NPCI > 0 148 struct extent *pcimem_ex; 149 struct extent *pciio_ex; 150 #endif 151 152 struct powerpc_bus_space gur_bst = { 153 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 154 .pbs_offset = GUR_BASE, 155 .pbs_limit = GUR_SIZE, 156 }; 157 158 struct powerpc_bus_space gur_le_bst = { 159 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 160 .pbs_offset = GUR_BASE, 161 .pbs_limit = GUR_SIZE, 162 }; 163 164 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 165 166 #if defined(SYS_CLK) 167 static uint64_t e500_sys_clk = SYS_CLK; 168 #endif 169 #ifdef CADMUS 170 static uint8_t cadmus_pci; 171 static uint8_t cadmus_csr; 172 #ifndef SYS_CLK 173 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 174 #endif 175 #elif defined(PIXIS) 176 static const uint32_t pixis_spd_map[8] = { 177 [PX_SPD_33MHZ] = 33333333, 178 [PX_SPD_40MHZ] = 40000000, 179 [PX_SPD_50MHZ] = 50000000, 180 [PX_SPD_66MHZ] = 66666666, 181 [PX_SPD_83MHZ] = 83333333, 182 [PX_SPD_100MHZ] = 100000000, 183 [PX_SPD_133MHZ] = 133333333, 184 [PX_SPD_166MHZ] = 166666667, 185 }; 186 static uint8_t pixis_spd; 187 #ifndef SYS_CLK 188 static uint64_t e500_sys_clk; 189 #endif 190 #elif !defined(SYS_CLK) 191 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 192 #endif 193 194 static int e500_cngetc(dev_t); 195 static void e500_cnputc(dev_t, int); 196 197 static struct consdev e500_earlycons = { 198 .cn_getc = e500_cngetc, 199 .cn_putc = e500_cnputc, 200 .cn_pollc = nullcnpollc, 201 }; 202 203 /* 204 * List of port-specific devices to attach to the processor local bus. 205 */ 206 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 207 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 208 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 209 SVR_P1025v1 >> 16 } }, 210 #if defined(MPC8572) || defined(P2020) || defined(P1025) 211 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 212 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 213 SVR_P1025v1 >> 16 } }, 214 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 215 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 216 SVR_P1025v1 >> 16 } }, 217 #endif 218 { "wdog" }, /* not a real device */ 219 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 220 1, { ISOURCE_DUART }, 221 1 + ilog2(DEVDISR_DUART) }, 222 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 223 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 224 1 + ilog2(DEVDISR_TSEC1), 225 { 0xffff, SVR_P1025v1 >> 16 } }, 226 #if defined(P1025) 227 { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1, 228 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 229 1 + ilog2(DEVDISR_TSEC1), 230 { SVR_P1025v1 >> 16 } }, 231 #if 0 232 { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1, 233 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX, 234 ISOURCE_ETSEC1_G1_ERR }, 235 1 + ilog2(DEVDISR_TSEC1), 236 { SVR_P1025v1 >> 16 } }, 237 #endif 238 #endif 239 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \ 240 || defined(P2020) 241 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 242 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 243 1 + ilog2(DEVDISR_TSEC2), 244 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 245 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 246 SVR_P1025v1 >> 16 } }, 247 #endif 248 #if defined(P1025) 249 { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2, 250 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 251 1 + ilog2(DEVDISR_TSEC2), 252 { SVR_P1025v1 >> 16 } }, 253 #if 0 254 { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5, 255 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX, 256 ISOURCE_ETSEC2_G1_ERR }, 257 1 + ilog2(DEVDISR_TSEC2), 258 { SVR_P1025v1 >> 16 } }, 259 #endif 260 #endif 261 #if defined(MPC8544) || defined(MPC8536) 262 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 263 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 264 1 + ilog2(DEVDISR_TSEC3), 265 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 266 #endif 267 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 268 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 269 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 270 1 + ilog2(DEVDISR_TSEC3), 271 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 272 SVR_P2020v2 >> 16 } }, 273 #endif 274 #if defined(P1025) 275 { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3, 276 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 277 1 + ilog2(DEVDISR_TSEC3), 278 { SVR_P1025v1 >> 16 } }, 279 #if 0 280 { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3, 281 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX, 282 ISOURCE_ETSEC3_G1_ERR }, 283 1 + ilog2(DEVDISR_TSEC3), 284 { SVR_P1025v1 >> 16 } }, 285 #endif 286 #endif 287 #if defined(MPC8548) || defined(MPC8572) 288 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 289 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 290 1 + ilog2(DEVDISR_TSEC4), 291 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 292 #endif 293 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 294 1, { ISOURCE_I2C }, 295 1 + ilog2(DEVDISR_I2C) }, 296 /* MPC8572 doesn't have any GPIO */ 297 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 298 1, { ISOURCE_GPIO }, 299 0, 300 { 0xffff, SVR_MPC8572v1 >> 16 } }, 301 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 302 1, { ISOURCE_DDR }, 303 1 + ilog2(DEVDISR_DDR_15), 304 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 305 #if defined(MPC8536) 306 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 307 1, { ISOURCE_DDR }, 308 1 + ilog2(DEVDISR_DDR_16), 309 { SVR_MPC8536v1 >> 16 } }, 310 #endif 311 #if defined(MPC8572) 312 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 313 1, { ISOURCE_DDR }, 314 1 + ilog2(DEVDISR_DDR_15), 315 { SVR_MPC8572v1 >> 16 } }, 316 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 317 1, { ISOURCE_DDR }, 318 1 + ilog2(DEVDISR_DDR2_14), 319 { SVR_MPC8572v1 >> 16 } }, 320 #endif 321 { "lbc", LBC_BASE, LBC_SIZE, 0, 322 1, { ISOURCE_LBC }, 323 1 + ilog2(DEVDISR_LBC) }, 324 #if defined(MPC8544) || defined(MPC8536) 325 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 326 1, { ISOURCE_PCIEX }, 327 1 + ilog2(DEVDISR_PCIE), 328 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 329 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 330 1, { ISOURCE_PCIEX2 }, 331 1 + ilog2(DEVDISR_PCIE2), 332 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 333 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 334 1, { ISOURCE_PCIEX3 }, 335 1 + ilog2(DEVDISR_PCIE3), 336 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 337 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 338 1, { ISOURCE_PCI1 }, 339 1 + ilog2(DEVDISR_PCI1), 340 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 341 #endif 342 #ifdef MPC8548 343 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 344 1, { ISOURCE_PCIEX }, 345 1 + ilog2(DEVDISR_PCIE), 346 { SVR_MPC8548v1 >> 16 }, }, 347 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 348 1, { ISOURCE_PCI1 }, 349 1 + ilog2(DEVDISR_PCI1), 350 { SVR_MPC8548v1 >> 16 }, }, 351 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 352 1, { ISOURCE_PCI2 }, 353 1 + ilog2(DEVDISR_PCI2), 354 { SVR_MPC8548v1 >> 16 }, }, 355 #endif 356 #if defined(MPC8572) || defined(P1025) || defined(P2020) 357 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 358 1, { ISOURCE_PCIEX }, 359 1 + ilog2(DEVDISR_PCIE), 360 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 361 SVR_P1025v1 >> 16 } }, 362 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 363 1, { ISOURCE_PCIEX2 }, 364 1 + ilog2(DEVDISR_PCIE2), 365 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 366 SVR_P1025v1 >> 16 } }, 367 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 368 1, { ISOURCE_PCIEX3_MPC8572 }, 369 1 + ilog2(DEVDISR_PCIE3), 370 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 371 SVR_P1025v1 >> 16 } }, 372 #endif 373 #if defined(MPC8536) || defined(P1025) || defined(P2020) 374 { "ehci", USB1_BASE, USB_SIZE, 1, 375 1, { ISOURCE_USB1 }, 376 1 + ilog2(DEVDISR_USB1), 377 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16, 378 SVR_P1025v1 >> 16 } }, 379 #endif 380 #ifdef MPC8536 381 { "ehci", USB2_BASE, USB_SIZE, 2, 382 1, { ISOURCE_USB2 }, 383 1 + ilog2(DEVDISR_USB2), 384 { SVR_MPC8536v1 >> 16 }, }, 385 { "ehci", USB3_BASE, USB_SIZE, 3, 386 1, { ISOURCE_USB3 }, 387 1 + ilog2(DEVDISR_USB3), 388 { SVR_MPC8536v1 >> 16 }, }, 389 { "sata", SATA1_BASE, SATA_SIZE, 1, 390 1, { ISOURCE_SATA1 }, 391 1 + ilog2(DEVDISR_SATA1), 392 { SVR_MPC8536v1 >> 16 }, }, 393 { "sata", SATA2_BASE, SATA_SIZE, 2, 394 1, { ISOURCE_SATA2 }, 395 1 + ilog2(DEVDISR_SATA2), 396 { SVR_MPC8536v1 >> 16 }, }, 397 { "spi", SPI_BASE, SPI_SIZE, 0, 398 1, { ISOURCE_SPI }, 399 1 + ilog2(DEVDISR_SPI_15), 400 { SVR_MPC8536v1 >> 16 }, }, 401 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 402 1, { ISOURCE_ESDHC }, 403 1 + ilog2(DEVDISR_ESDHC_12), 404 { SVR_MPC8536v1 >> 16 }, }, 405 #endif 406 #if defined(P1025) || defined(P2020) 407 { "spi", SPI_BASE, SPI_SIZE, 0, 408 1, { ISOURCE_SPI }, 409 1 + ilog2(DEVDISR_SPI_28), 410 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 411 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 412 1, { ISOURCE_ESDHC }, 413 1 + ilog2(DEVDISR_ESDHC_10), 414 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 415 #endif 416 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 417 { NULL } 418 }; 419 420 static int 421 e500_cngetc(dev_t dv) 422 { 423 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 424 425 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 426 return -1; 427 428 return com0addr[com_data] & 0xff; 429 } 430 431 static void 432 e500_cnputc(dev_t dv, int c) 433 { 434 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 435 int timo = 150000; 436 437 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 438 ; 439 440 com0addr[com_data] = c; 441 __asm("mbar"); 442 443 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 444 ; 445 } 446 447 static void * 448 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 449 { 450 if (prefetchable) 451 return NULL; 452 if (pa < gur_bst.pbs_offset) 453 return NULL; 454 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 455 return NULL; 456 return (void *)pa; 457 } 458 459 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 460 461 static void 462 e500_cpu_reset(void) 463 { 464 __asm volatile("sync"); 465 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 466 __asm volatile("msync;isync"); 467 } 468 469 static psize_t 470 memprobe(vaddr_t endkernel) 471 { 472 phys_ram_seg_t *mr; 473 paddr_t boot_page = cpu_read_4(GUR_BPTR); 474 printf(" bptr=%"PRIxPADDR, boot_page); 475 if (boot_page & BPTR_EN) { 476 /* 477 * shift it to an address 478 */ 479 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 480 } else { 481 boot_page = ~(paddr_t)0; 482 } 483 484 /* 485 * First we need to find out how much physical memory we have. 486 * We could let our bootloader tell us, but it's almost as easy 487 * to ask the DDR memory controller. 488 */ 489 mr = physmemr; 490 for (u_int i = 0; i < 4; i++) { 491 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 492 if (v & CS_CONFIG_EN) { 493 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 494 if (v == 0) 495 continue; 496 mr->start = BNDS_SA_GET(v); 497 mr->size = BNDS_SIZE_GET(v); 498 #ifdef MEMSIZE 499 if (mr->start >= MEMSIZE) 500 continue; 501 if (mr->start + mr->size > MEMSIZE) 502 mr->size = MEMSIZE - mr->start; 503 #endif 504 #if 0 505 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 506 mr - physmemr, mr->size, mr->start); 507 #endif 508 mr++; 509 } 510 } 511 512 if (mr == physmemr) 513 panic("no memory configured!"); 514 515 /* 516 * Sort memory regions from low to high and coalesce adjacent regions 517 */ 518 u_int cnt = mr - physmemr; 519 if (cnt > 1) { 520 for (u_int i = 0; i < cnt - 1; i++) { 521 for (u_int j = i + 1; j < cnt; j++) { 522 if (physmemr[j].start < physmemr[i].start) { 523 phys_ram_seg_t tmp = physmemr[i]; 524 physmemr[i] = physmemr[j]; 525 physmemr[j] = tmp; 526 } 527 } 528 } 529 mr = physmemr; 530 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 531 if (mr->start + mr->size == mr[1].start) { 532 mr->size += mr[1].size; 533 for (u_int j = 1; i + j + 1 < cnt; j++) 534 mr[j] = mr[j+1]; 535 cnt--; 536 } 537 } 538 } else if (cnt == 0) { 539 panic("%s: no memory found", __func__); 540 } 541 542 /* 543 * Copy physical memory to available memory. 544 */ 545 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 546 547 /* 548 * Adjust available memory to skip kernel at start of memory. 549 */ 550 availmemr[0].size -= endkernel - availmemr[0].start; 551 availmemr[0].start = endkernel; 552 553 mr = availmemr; 554 for (u_int i = 0; i < cnt; i++, mr++) { 555 /* 556 * U-boot reserves a boot-page on multi-core chips. 557 * We need to make sure that we never disturb it. 558 */ 559 const paddr_t mr_end = mr->start + mr->size; 560 if (mr_end > boot_page && boot_page >= mr->start) { 561 /* 562 * Normally u-boot will put in at the end 563 * of memory. But in case it doesn't, deal 564 * with all possibilities. 565 */ 566 if (boot_page + PAGE_SIZE == mr_end) { 567 mr->size -= PAGE_SIZE; 568 } else if (boot_page == mr->start) { 569 mr->start += PAGE_SIZE; 570 mr->size -= PAGE_SIZE; 571 } else { 572 mr->size = boot_page - mr->start; 573 mr++; 574 for (u_int j = cnt; j > i + 1; j--) { 575 availmemr[j] = availmemr[j-1]; 576 } 577 cnt++; 578 mr->start = boot_page + PAGE_SIZE; 579 mr->size = mr_end - mr->start; 580 } 581 break; 582 } 583 } 584 585 /* 586 * Steal pages at the end of memory for the kernel message buffer. 587 */ 588 mr = availmemr + cnt - 1; 589 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 590 mr->size -= round_page(MSGBUFSIZE); 591 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 592 593 /* 594 * Calculate physmem. 595 */ 596 for (u_int i = 0; i < cnt; i++) 597 physmem += atop(physmemr[i].size); 598 599 nmemr = cnt; 600 return physmemr[cnt-1].start + physmemr[cnt-1].size; 601 } 602 603 void 604 consinit(void) 605 { 606 static bool attached = false; 607 608 if (attached) 609 return; 610 attached = true; 611 612 if (comcnfreq == -1) { 613 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 614 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 615 comcnfreq = e500_sys_clk * plat_ratio; 616 printf(" comcnfreq=%u", comcnfreq); 617 } 618 619 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 620 COM_TYPE_NORMAL, comcnmode); 621 } 622 623 void 624 cpu_probe_cache(void) 625 { 626 struct cpu_info * const ci = curcpu(); 627 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 628 629 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 630 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 631 632 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 633 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 634 635 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 636 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 637 } else { 638 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 639 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 640 } 641 642 #ifdef DEBUG 643 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 644 if ((L1CSR_CE & l1csr0) == 0) 645 printf(" DC=off"); 646 647 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 648 if ((L1CSR_CE & l1csr1) == 0) 649 printf(" IC=off"); 650 #endif 651 } 652 653 static uint16_t 654 getsvr(void) 655 { 656 uint16_t svr = mfspr(SPR_SVR) >> 16; 657 658 svr &= ~0x8; /* clear security bit */ 659 switch (svr) { 660 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 661 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 662 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 663 case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16; 664 default: return svr; 665 } 666 } 667 668 static const char * 669 socname(uint32_t svr) 670 { 671 svr &= ~0x80000; /* clear security bit */ 672 switch (svr >> 8) { 673 case SVR_MPC8533 >> 8: return "MPC8533"; 674 case SVR_MPC8536v1 >> 8: return "MPC8536"; 675 case SVR_MPC8541v1 >> 8: return "MPC8541"; 676 case SVR_MPC8543v2 >> 8: return "MPC8543"; 677 case SVR_MPC8544v1 >> 8: return "MPC8544"; 678 case SVR_MPC8545v2 >> 8: return "MPC8545"; 679 case SVR_MPC8547v2 >> 8: return "MPC8547"; 680 case SVR_MPC8548v2 >> 8: return "MPC8548"; 681 case SVR_MPC8555v1 >> 8: return "MPC8555"; 682 case SVR_MPC8568v1 >> 8: return "MPC8568"; 683 case SVR_MPC8567v1 >> 8: return "MPC8567"; 684 case SVR_MPC8572v1 >> 8: return "MPC8572"; 685 case SVR_P2020v2 >> 8: return "P2020"; 686 case SVR_P2010v2 >> 8: return "P2010"; 687 case SVR_P1016v1 >> 8: return "P1016"; 688 case SVR_P1025v1 >> 8: return "P1025"; 689 default: 690 panic("%s: unknown SVR %#x", __func__, svr); 691 } 692 } 693 694 static void 695 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 696 { 697 static const char units[16] = "KKKKKMMMMMGGGGGT"; 698 699 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 700 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 701 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 702 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 703 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 704 705 aprint_normal_dev(self, "%s:", name); 706 707 aprint_normal(" %u", nentries); 708 if (TLBCFG_AVAIL_P(tlbcfg)) { 709 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 710 minsize, maxsize, units[maxsize_log4k]); 711 } else { 712 aprint_normal(" fixed-size (%uKB)", minsize); 713 } 714 if (assoc == 0 || assoc == nentries) 715 aprint_normal(" fully"); 716 else 717 aprint_normal(" %u-way set", assoc); 718 aprint_normal(" associative entries\n"); 719 } 720 721 static void 722 cpu_print_info(struct cpu_info *ci) 723 { 724 uint64_t freq = board_info_get_number("processor-frequency"); 725 device_t self = ci->ci_dev; 726 727 char freqbuf[10]; 728 if (freq >= 999500000) { 729 const uint32_t freq32 = (freq + 500000) / 10000000; 730 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 731 freq32 / 100, freq32 % 100); 732 } else { 733 const uint32_t freq32 = (freq + 500000) / 1000000; 734 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 735 } 736 737 const uint32_t pvr = mfpvr(); 738 const uint32_t svr = mfspr(SPR_SVR); 739 const uint32_t pir = mfspr(SPR_PIR); 740 741 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 742 "ID %u%s\n", 743 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 744 (svr >> 4) & 15, svr & 15, 745 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 746 (pvr >> 4) & 15, pvr & 15, 747 pir, (pir == 0 ? " (Primary)" : "")); 748 749 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 750 aprint_normal_dev(self, 751 "%uKB/%uB %u-way L1 %s cache\n", 752 L1CFG_CSIZE_GET(l1cfg0) >> 10, 753 32 << L1CFG_CBSIZE_GET(l1cfg0), 754 L1CFG_CNWAY_GET(l1cfg0), 755 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 756 ? "data" : "unified"); 757 758 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 759 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 760 aprint_normal_dev(self, 761 "%uKB/%uB %u-way L1 %s cache\n", 762 L1CFG_CSIZE_GET(l1cfg1) >> 10, 763 32 << L1CFG_CBSIZE_GET(l1cfg1), 764 L1CFG_CNWAY_GET(l1cfg1), 765 "instruction"); 766 } 767 768 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 769 aprint_normal_dev(self, 770 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 771 MMUCFG_NTLBS_GET(mmucfg) + 1, 772 MMUCFG_NPIDS_GET(mmucfg), 773 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 774 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 775 776 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 777 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 778 } 779 780 #ifdef MULTIPROCESSOR 781 static void 782 e500_cpu_spinup(device_t self, struct cpu_info *ci) 783 { 784 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 785 struct pglist splist; 786 787 if (spinup_table_addr == 0) { 788 aprint_error_dev(self, "hatch failed (no spin-up table)"); 789 return; 790 } 791 792 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 793 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 794 const size_t id = cpu_index(ci); 795 volatile __cpuset_t * const hatchlings = &cpuset_info.cpus_hatched; 796 797 if (h->hatch_sp == 0) { 798 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 799 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 800 if (error) { 801 aprint_error_dev(self, 802 "unable to allocate hatch stack\n"); 803 return; 804 } 805 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 806 + PAGE_SIZE - CALLFRAMELEN; 807 } 808 809 810 for (size_t i = 1; e[i].entry_pir != 0; i++) { 811 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 812 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 813 if (e[i].entry_pir == ci->ci_cpuid) { 814 815 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 816 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 817 ci->ci_curpm = pmap_kernel(); 818 ci->ci_lasttb = cpu_info[0].ci_lasttb; 819 ci->ci_data.cpu_cc_freq = 820 cpu_info[0].ci_data.cpu_cc_freq; 821 822 h->hatch_self = self; 823 h->hatch_ci = ci; 824 h->hatch_running = -1; 825 h->hatch_pir = e[i].entry_pir; 826 h->hatch_hid0 = mfspr(SPR_HID0); 827 KASSERT(h->hatch_sp != 0); 828 /* 829 * Get new timebase. We don't want to deal with 830 * timebase crossing a 32-bit boundary so make sure 831 * that we have enough headroom to do the timebase 832 * synchronization. 833 */ 834 #define TBSYNC_SLOP 2000 835 uint32_t tbl; 836 uint32_t tbu; 837 do { 838 tbu = mfspr(SPR_RTBU); 839 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 840 } while (tbl < TBSYNC_SLOP); 841 842 h->hatch_tbu = tbu; 843 h->hatch_tbl = tbl; 844 __asm("sync;isync"); 845 dcache_wbinv((vaddr_t)h, sizeof(*h)); 846 847 #if 1 848 /* 849 * And here we go... 850 */ 851 e[i].entry_addr_lower = 852 (uint32_t)e500_spinup_trampoline; 853 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 854 __asm __volatile("sync;isync"); 855 __insn_barrier(); 856 857 for (u_int timo = 0; timo++ < 10000; ) { 858 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 859 if (e[i].entry_addr_lower == 3) { 860 printf( 861 "%s: cpu%u started in %u spins\n", 862 __func__, cpu_index(ci), timo); 863 break; 864 } 865 } 866 for (u_int timo = 0; timo++ < 10000; ) { 867 dcache_inv((vaddr_t)h, sizeof(*h)); 868 if (h->hatch_running == 0) { 869 printf( 870 "%s: cpu%u cracked in %u spins: (running=%d)\n", 871 __func__, cpu_index(ci), 872 timo, h->hatch_running); 873 break; 874 } 875 } 876 if (h->hatch_running == -1) { 877 aprint_error_dev(self, 878 "hatch failed (timeout): running=%d" 879 ", entry=%#x\n", 880 h->hatch_running, e[i].entry_addr_lower); 881 goto out; 882 } 883 #endif 884 885 /* 886 * First then we do is to synchronize timebases. 887 * TBSYNC_SLOP*16 should be more than enough 888 * instructions. 889 */ 890 while (tbl != mftbl()) 891 continue; 892 h->hatch_running = 1; 893 dcache_wbinv((vaddr_t)h, sizeof(*h)); 894 __asm("sync;isync"); 895 __insn_barrier(); 896 897 for (u_int timo = 10000; timo-- > 0; ) { 898 dcache_inv((vaddr_t)h, sizeof(*h)); 899 if (h->hatch_running > 1) 900 break; 901 } 902 if (h->hatch_running == 1) { 903 printf( 904 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 905 __func__, 906 ((int64_t)tbu << 32) + tbl, 907 (int64_t) 908 (((uint64_t)h->hatch_tbu << 32) 909 + (uint64_t)h->hatch_tbl), 910 h->hatch_running); 911 goto out; 912 } 913 printf( 914 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 915 __func__, 916 (int64_t) 917 (((uint64_t)h->hatch_tbu << 32) 918 + (uint64_t)h->hatch_tbl), 919 h->hatch_running); 920 /* 921 * Now we wait for the hatching to complete. 10ms 922 * should be long enough. 923 */ 924 for (u_int timo = 10000; timo-- > 0; ) { 925 if (CPUSET_HAS_P(*hatchlings, id)) { 926 aprint_normal_dev(self, 927 "hatch successful (%u spins, " 928 "timebase adjusted by %"PRId64")\n", 929 10000 - timo, 930 (int64_t) 931 (((uint64_t)h->hatch_tbu << 32) 932 + (uint64_t)h->hatch_tbl)); 933 goto out; 934 } 935 DELAY(1); 936 } 937 938 aprint_error_dev(self, 939 "hatch failed (timeout): running=%u\n", 940 h->hatch_running); 941 goto out; 942 } 943 } 944 945 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 946 ci->ci_cpuid); 947 out: 948 if (h->hatch_sp == 0) 949 uvm_pglistfree(&splist); 950 } 951 #endif 952 953 void 954 e500_cpu_hatch(struct cpu_info *ci) 955 { 956 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 957 958 /* 959 * Make sure interrupts are blocked. 960 */ 961 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 962 963 intr_cpu_hatch(ci); 964 965 cpu_print_info(ci); 966 967 /* 968 */ 969 } 970 971 static void 972 e500_cpu_attach(device_t self, u_int instance) 973 { 974 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 975 976 if (instance > 1) { 977 #if defined(MULTIPROCESSOR) 978 ci->ci_idepth = -1; 979 self->dv_private = ci; 980 981 ci->ci_cpuid = instance - (instance > 0); 982 ci->ci_dev = self; 983 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 984 985 mi_cpu_attach(ci); 986 987 intr_cpu_attach(ci); 988 cpu_evcnt_attach(ci); 989 990 e500_cpu_spinup(self, ci); 991 return; 992 #else 993 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 994 return; 995 #endif 996 } 997 998 self->dv_private = ci; 999 1000 ci->ci_cpuid = instance - (instance > 0); 1001 ci->ci_dev = self; 1002 1003 intr_cpu_attach(ci); 1004 cpu_evcnt_attach(ci); 1005 1006 KASSERT(ci == curcpu()); 1007 intr_cpu_hatch(ci); 1008 1009 cpu_print_info(ci); 1010 } 1011 1012 void 1013 e500_ipi_halt(void) 1014 { 1015 register_t msr, hid0; 1016 1017 msr = wrtee(0); 1018 1019 hid0 = mfspr(SPR_HID0); 1020 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 1021 mtspr(SPR_HID0, hid0); 1022 1023 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 1024 mtmsr(msr); 1025 for (;;); /* loop forever */ 1026 } 1027 1028 1029 static void 1030 calltozero(void) 1031 { 1032 panic("call to 0 from %p", __builtin_return_address(0)); 1033 } 1034 1035 void 1036 initppc(vaddr_t startkernel, vaddr_t endkernel, 1037 void *a0, void *a1, void *a2, void *a3) 1038 { 1039 struct cpu_info * const ci = curcpu(); 1040 struct cpu_softc * const cpu = ci->ci_softc; 1041 1042 cn_tab = &e500_earlycons; 1043 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 1044 startkernel, endkernel, a0, a1, a2, a3); 1045 1046 /* 1047 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 1048 * DOZE is ok. 1049 */ 1050 const register_t hid0 = mfspr(SPR_HID0); 1051 mtspr(SPR_HID0, 1052 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1053 #ifdef CADMUS 1054 /* 1055 * Need to cache this from cadmus since we need to unmap cadmus since 1056 * it falls in the middle of kernel address space. 1057 */ 1058 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1059 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1060 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1061 printf(" cadmus_pci=%#x", cadmus_pci); 1062 printf(" cadmus_csr=%#x", cadmus_csr); 1063 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1064 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1065 e500_sys_clk *= 2; 1066 } 1067 #endif 1068 #ifdef PIXIS 1069 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1070 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1071 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1072 #ifndef SYS_CLK 1073 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1074 #else 1075 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1076 #endif 1077 #endif 1078 printf(" porpllsr=0x%08x", 1079 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1080 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1081 1082 /* 1083 * Make sure arguments are page aligned. 1084 */ 1085 startkernel = trunc_page(startkernel); 1086 endkernel = round_page(endkernel); 1087 1088 /* 1089 * Initialize the bus space tag used to access the 85xx general 1090 * utility registers. It doesn't need to be extent protected. 1091 * We know the GUR is mapped via a TLB1 entry so we add a limited 1092 * mapiodev which allows mappings in GUR space. 1093 */ 1094 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1095 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1096 bus_space_init(&gur_bst, NULL, NULL, 0); 1097 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1098 cpu->cpu_bst = &gur_bst; 1099 cpu->cpu_le_bst = &gur_le_bst; 1100 cpu->cpu_bsh = gur_bsh; 1101 1102 /* 1103 * Attach the console early, really early. 1104 */ 1105 consinit(); 1106 1107 /* 1108 * Reset the PIC to a known state. 1109 */ 1110 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1111 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1112 ; 1113 #if 0 1114 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1115 #endif 1116 printf(" openpic-reset(ctpr=%u)", 1117 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1118 1119 /* 1120 * fill in with an absolute branch to a routine that will panic. 1121 */ 1122 *(int *)0 = 0x48000002 | (int) calltozero; 1123 1124 /* 1125 * Get the cache sizes. 1126 */ 1127 cpu_probe_cache(); 1128 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1129 ci->ci_ci.dcache_size >> 10, 1130 ci->ci_ci.dcache_line_size, 1131 ci->ci_ci.icache_size >> 10, 1132 ci->ci_ci.icache_line_size); 1133 1134 /* 1135 * Now find out how much memory is attached 1136 */ 1137 pmemsize = memprobe(endkernel); 1138 cpu->cpu_highmem = pmemsize; 1139 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1140 1141 /* 1142 * Now we need cleanout the TLB of stuff that we don't need. 1143 */ 1144 e500_tlb_init(endkernel, pmemsize); 1145 printf(" e500_tlbinit(%#lx,%zuMB)", 1146 endkernel, (size_t) (pmemsize >> 20)); 1147 1148 /* 1149 * 1150 */ 1151 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1152 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1153 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1154 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1155 1156 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1157 1158 /* 1159 * Initialize the message buffer. 1160 */ 1161 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1162 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1163 1164 /* 1165 * Initialize exception vectors and interrupts 1166 */ 1167 exception_init(&e500_intrsw); 1168 1169 printf(" exception_init=%p", &e500_intrsw); 1170 1171 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1172 1173 /* 1174 * Set the page size. 1175 */ 1176 uvm_setpagesize(); 1177 1178 /* 1179 * Initialize the pmap. 1180 */ 1181 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1182 1183 /* 1184 * Let's take all the indirect calls via our stubs and patch 1185 * them to be direct calls. 1186 */ 1187 cpu_fixup_stubs(); 1188 1189 /* 1190 * As a debug measure we can change the TLB entry that maps all of 1191 * memory to one that encompasses the 64KB with the kernel vectors. 1192 * All other pages will be soft faulted into the TLB as needed. 1193 */ 1194 e500_tlb_minimize(endkernel); 1195 1196 /* 1197 * Set some more MD helpers 1198 */ 1199 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1200 cpu_md_ops.md_device_register = e500_device_register; 1201 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1202 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1203 #if NGPIO > 0 1204 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1205 #endif 1206 1207 printf(" initppc done!\n"); 1208 1209 /* 1210 * Look for the Book-E modules in the right place. 1211 */ 1212 module_machine = module_machine_booke; 1213 } 1214 1215 #ifdef MPC8548 1216 static const char * const mpc8548cds_extirq_names[] = { 1217 [0] = "pci inta", 1218 [1] = "pci intb", 1219 [2] = "pci intc", 1220 [3] = "pci intd", 1221 [4] = "irq4", 1222 [5] = "gige phy", 1223 [6] = "atm phy", 1224 [7] = "cpld", 1225 [8] = "irq8", 1226 [9] = "nvram", 1227 [10] = "debug", 1228 [11] = "pci2 inta", 1229 }; 1230 #endif 1231 1232 static const char * const mpc85xx_extirq_names[] = { 1233 [0] = "extirq 0", 1234 [1] = "extirq 1", 1235 [2] = "extirq 2", 1236 [3] = "extirq 3", 1237 [4] = "extirq 4", 1238 [5] = "extirq 5", 1239 [6] = "extirq 6", 1240 [7] = "extirq 7", 1241 [8] = "extirq 8", 1242 [9] = "extirq 9", 1243 [10] = "extirq 10", 1244 [11] = "extirq 11", 1245 }; 1246 1247 static void 1248 mpc85xx_extirq_setup(void) 1249 { 1250 #ifdef MPC8548 1251 const char * const * names = mpc8548cds_extirq_names; 1252 const size_t n = __arraycount(mpc8548cds_extirq_names); 1253 #else 1254 const char * const * names = mpc85xx_extirq_names; 1255 const size_t n = __arraycount(mpc85xx_extirq_names); 1256 #endif 1257 prop_array_t extirqs = prop_array_create_with_capacity(n); 1258 for (u_int i = 0; i < n; i++) { 1259 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1260 prop_array_set(extirqs, i, ps); 1261 prop_object_release(ps); 1262 } 1263 board_info_add_object("external-irqs", extirqs); 1264 prop_object_release(extirqs); 1265 } 1266 1267 static void 1268 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1269 { 1270 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1271 KASSERT(pci_intmap != NULL); 1272 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1273 KASSERT(mask != NULL); 1274 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1275 prop_object_release(mask); 1276 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1277 KASSERT(pn_ist != NULL); 1278 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1279 KASSERT(pn_intr != NULL); 1280 prop_dictionary_t entry = prop_dictionary_create(); 1281 KASSERT(entry != NULL); 1282 prop_dictionary_set(entry, "interrupt", pn_intr); 1283 prop_dictionary_set(entry, "type", pn_ist); 1284 prop_dictionary_set(pci_intmap, "000000", entry); 1285 prop_object_release(pn_intr); 1286 prop_object_release(entry); 1287 va_list ap; 1288 va_start(ap, inta); 1289 u_int intrinc = __LOWEST_SET_BIT(intmask); 1290 for (u_int i = 0; i < intmask; i += intrinc) { 1291 char prop_name[12]; 1292 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1293 entry = prop_dictionary_create(); 1294 KASSERT(entry != NULL); 1295 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1296 KASSERT(pn_intr != NULL); 1297 prop_dictionary_set(entry, "interrupt", pn_intr); 1298 prop_dictionary_set(entry, "type", pn_ist); 1299 prop_dictionary_set(pci_intmap, prop_name, entry); 1300 prop_object_release(pn_intr); 1301 prop_object_release(entry); 1302 } 1303 va_end(ap); 1304 prop_object_release(pn_ist); 1305 board_info_add_object(name, pci_intmap); 1306 prop_object_release(pci_intmap); 1307 } 1308 1309 void 1310 cpu_startup(void) 1311 { 1312 struct cpu_info * const ci = curcpu(); 1313 const uint16_t svr = getsvr(); 1314 1315 powersave = 0; /* we can do it but turn it on by default */ 1316 1317 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1318 1319 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1320 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1321 uint32_t e500_ratio = E500_RATIO_GET(v); 1322 1323 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1324 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1325 1326 ci->ci_khz = (cpu_freq + 500) / 1000; 1327 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1328 1329 board_info_add_number("my-id", svr); 1330 board_info_add_bool("pq3"); 1331 board_info_add_number("mem-size", pmemsize); 1332 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1333 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1334 uint32_t l2banks = l2siz >> 16; 1335 #ifdef MPC85555 1336 if (svr == (MPC8555v1 >> 16)) { 1337 l2siz >>= 1; 1338 l2banks >>= 1; 1339 } 1340 #endif 1341 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1342 if (boot_page & BPTR_EN) { 1343 bool found = false; 1344 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1345 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1346 * const bp = (void *)boot_page; 1347 bp <= dp; dp--) { 1348 if (*dp == boot_page) { 1349 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1350 spinup_table_addr = 1351 roundup2(spinup_table_addr, 32); 1352 board_info_add_number("mp-boot-page", 1353 boot_page); 1354 board_info_add_number("mp-spin-up-table", 1355 spinup_table_addr); 1356 printf("Found MP boot page @ %#"PRIxPADDR". " 1357 "Spin-up table @ %#"PRIxPTR"\n", 1358 boot_page, spinup_table_addr); 1359 found = true; 1360 break; 1361 } 1362 } 1363 if (!found) { 1364 printf("Found MP boot page @ %#"PRIxPADDR 1365 " with missing U-boot signature!\n", boot_page); 1366 board_info_add_number("mp-spin-up-table", 0); 1367 } 1368 } 1369 board_info_add_number("l2-cache-size", l2siz); 1370 board_info_add_number("l2-cache-line-size", 32); 1371 board_info_add_number("l2-cache-banks", l2banks); 1372 board_info_add_number("l2-cache-ways", 8); 1373 1374 board_info_add_number("processor-frequency", cpu_freq); 1375 board_info_add_number("bus-frequency", ccb_freq); 1376 board_info_add_number("pci-frequency", e500_sys_clk); 1377 board_info_add_number("timebase-frequency", ccb_freq / 8); 1378 1379 #ifdef CADMUS 1380 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1381 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1382 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1383 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1384 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1385 #else 1386 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1387 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1388 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1389 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1390 #endif 1391 1392 uint64_t macstnaddr = 1393 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1394 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1395 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1396 1397 #if NPCI > 0 && defined(PCI_MEMBASE) 1398 pcimem_ex = extent_create("pcimem", 1399 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1400 NULL, 0, EX_WAITOK); 1401 #endif 1402 #if NPCI > 0 && defined(PCI_IOBASE) 1403 pciio_ex = extent_create("pciio", 1404 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1405 NULL, 0, EX_WAITOK); 1406 #endif 1407 mpc85xx_extirq_setup(); 1408 /* 1409 * PCI-Express virtual wire interrupts on combined with 1410 * External IRQ0/1/2/3. 1411 */ 1412 switch (svr) { 1413 #if defined(MPC8548) 1414 case SVR_MPC8548v1 >> 16: 1415 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1416 IST_LEVEL, 0, 1, 2, 3); 1417 break; 1418 #endif 1419 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \ 1420 || defined(P1025) || defined(P2020) 1421 case SVR_MPC8536v1 >> 16: 1422 case SVR_MPC8544v1 >> 16: 1423 case SVR_MPC8572v1 >> 16: 1424 case SVR_P1016v1 >> 16: 1425 case SVR_P1025v1 >> 16: 1426 case SVR_P2010v2 >> 16: 1427 case SVR_P2020v2 >> 16: 1428 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1429 0, 1, 2, 3); 1430 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1431 4, 5, 6, 7); 1432 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1433 8, 9, 10, 11); 1434 break; 1435 #endif 1436 } 1437 switch (svr) { 1438 #if defined(MPC8536) 1439 case SVR_MPC8536v1 >> 16: 1440 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1441 1, 2, 3, 4); 1442 break; 1443 #endif 1444 #if defined(MPC8544) 1445 case SVR_MPC8544v1 >> 16: 1446 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1447 0, 1, 2, 3); 1448 break; 1449 #endif 1450 #if defined(MPC8548) 1451 case SVR_MPC8548v1 >> 16: 1452 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1453 0, 1, 2, 3); 1454 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1455 11, 1, 2, 3); 1456 break; 1457 #endif 1458 } 1459 } 1460
Indexes created Sun Sep 28 12:09:53 GMT 2025