machdep.c revision 1.27
1 /* $NetBSD: machdep.c,v 1.27 2012/07/18 19:38:26 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_altivec.h" 42 #include "opt_ddb.h" 43 #include "opt_mpc85xx.h" 44 #include "opt_pci.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <dev/cons.h> 70 71 #include <dev/ic/comreg.h> 72 #include <dev/ic/comvar.h> 73 74 #include <net/if.h> 75 #include <net/if_media.h> 76 #include <dev/mii/miivar.h> 77 78 #include <powerpc/cpuset.h> 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 struct uboot_bdinfo { 96 uint32_t bd_memstart; 97 uint32_t bd_memsize; 98 uint32_t bd_flashstart; 99 uint32_t bd_flashsize; 100 /*10*/ uint32_t bd_flashoffset; 101 uint32_t bd_sramstart; 102 uint32_t bd_sramsize; 103 uint32_t bd_immrbase; 104 /*20*/ uint32_t bd_bootflags; 105 uint32_t bd_ipaddr; 106 uint8_t bd_etheraddr[6]; 107 uint16_t bd_ethspeed; 108 /*30*/ uint32_t bd_intfreq; 109 uint32_t bd_cpufreq; 110 uint32_t bd_baudrate; 111 /*3c*/ uint8_t bd_etheraddr1[6]; 112 /*42*/ uint8_t bd_etheraddr2[6]; 113 /*48*/ uint8_t bd_etheraddr3[6]; 114 /*4e*/ uint16_t bd_pad; 115 }; 116 117 /* 118 * booke kernels need to set module_machine to this for modules to work. 119 */ 120 char module_machine_booke[] = "powerpc-booke"; 121 122 void initppc(vaddr_t, vaddr_t, void *, void *, void *, void *); 123 124 #define MEMREGIONS 4 125 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 126 phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 127 static u_int nmemr; 128 129 #ifndef CONSFREQ 130 # define CONSFREQ -1 /* inherit from firmware */ 131 #endif 132 #ifndef CONSPEED 133 # define CONSPEED 115200 134 #endif 135 #ifndef CONMODE 136 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 137 #endif 138 #ifndef CONSADDR 139 # define CONSADDR DUART2_BASE 140 #endif 141 142 int comcnfreq = CONSFREQ; 143 int comcnspeed = CONSPEED; 144 tcflag_t comcnmode = CONMODE; 145 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 146 147 #if NPCI > 0 148 struct extent *pcimem_ex; 149 struct extent *pciio_ex; 150 #endif 151 152 struct powerpc_bus_space gur_bst = { 153 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 154 .pbs_offset = GUR_BASE, 155 .pbs_limit = GUR_SIZE, 156 }; 157 158 struct powerpc_bus_space gur_le_bst = { 159 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 160 .pbs_offset = GUR_BASE, 161 .pbs_limit = GUR_SIZE, 162 }; 163 164 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 165 166 #if defined(SYS_CLK) 167 static uint64_t e500_sys_clk = SYS_CLK; 168 #endif 169 #ifdef CADMUS 170 static uint8_t cadmus_pci; 171 static uint8_t cadmus_csr; 172 #ifndef SYS_CLK 173 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 174 #endif 175 #elif defined(PIXIS) 176 static const uint32_t pixis_spd_map[8] = { 177 [PX_SPD_33MHZ] = 33333333, 178 [PX_SPD_40MHZ] = 40000000, 179 [PX_SPD_50MHZ] = 50000000, 180 [PX_SPD_66MHZ] = 66666666, 181 [PX_SPD_83MHZ] = 83333333, 182 [PX_SPD_100MHZ] = 100000000, 183 [PX_SPD_133MHZ] = 133333333, 184 [PX_SPD_166MHZ] = 166666667, 185 }; 186 static uint8_t pixis_spd; 187 #ifndef SYS_CLK 188 static uint64_t e500_sys_clk; 189 #endif 190 #elif !defined(SYS_CLK) 191 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 192 #endif 193 194 static int e500_cngetc(dev_t); 195 static void e500_cnputc(dev_t, int); 196 197 static struct consdev e500_earlycons = { 198 .cn_getc = e500_cngetc, 199 .cn_putc = e500_cnputc, 200 .cn_pollc = nullcnpollc, 201 }; 202 203 /* 204 * List of port-specific devices to attach to the processor local bus. 205 */ 206 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 207 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 208 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 209 SVR_P1025v1 >> 16 } }, 210 #if defined(MPC8572) || defined(P2020) || defined(P1025) 211 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 212 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 213 SVR_P1025v1 >> 16 } }, 214 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 215 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 216 SVR_P1025v1 >> 16 } }, 217 #endif 218 { "wdog" }, /* not a real device */ 219 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 220 1, { ISOURCE_DUART }, 221 1 + ilog2(DEVDISR_DUART) }, 222 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 223 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 224 1 + ilog2(DEVDISR_TSEC1), 225 { 0xffff, SVR_P1025v1 >> 16 } }, 226 #if defined(P1025) 227 { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1, 228 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 229 1 + ilog2(DEVDISR_TSEC1), 230 { SVR_P1025v1 >> 16 } }, 231 #if 0 232 { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1, 233 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX, 234 ISOURCE_ETSEC1_G1_ERR }, 235 1 + ilog2(DEVDISR_TSEC1), 236 { SVR_P1025v1 >> 16 } }, 237 #endif 238 #endif 239 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \ 240 || defined(P2020) 241 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 242 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 243 1 + ilog2(DEVDISR_TSEC2), 244 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 245 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 246 SVR_P1025v1 >> 16 } }, 247 #endif 248 #if defined(P1025) 249 { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2, 250 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 251 1 + ilog2(DEVDISR_TSEC2), 252 { SVR_P1025v1 >> 16 } }, 253 #if 0 254 { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5, 255 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX, 256 ISOURCE_ETSEC2_G1_ERR }, 257 1 + ilog2(DEVDISR_TSEC2), 258 { SVR_P1025v1 >> 16 } }, 259 #endif 260 #endif 261 #if defined(MPC8544) || defined(MPC8536) 262 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 263 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 264 1 + ilog2(DEVDISR_TSEC3), 265 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 266 #endif 267 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 268 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 269 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 270 1 + ilog2(DEVDISR_TSEC3), 271 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 272 SVR_P2020v2 >> 16 } }, 273 #endif 274 #if defined(P1025) 275 { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3, 276 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 277 1 + ilog2(DEVDISR_TSEC3), 278 { SVR_P1025v1 >> 16 } }, 279 #if 0 280 { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3, 281 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX, 282 ISOURCE_ETSEC3_G1_ERR }, 283 1 + ilog2(DEVDISR_TSEC3), 284 { SVR_P1025v1 >> 16 } }, 285 #endif 286 #endif 287 #if defined(MPC8548) || defined(MPC8572) 288 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 289 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 290 1 + ilog2(DEVDISR_TSEC4), 291 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 292 #endif 293 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 294 1, { ISOURCE_I2C }, 295 1 + ilog2(DEVDISR_I2C) }, 296 /* MPC8572 doesn't have any GPIO */ 297 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 298 1, { ISOURCE_GPIO }, 299 0, 300 { 0xffff, SVR_MPC8572v1 >> 16 } }, 301 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 302 1, { ISOURCE_DDR }, 303 1 + ilog2(DEVDISR_DDR_15), 304 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 305 #if defined(MPC8536) 306 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 307 1, { ISOURCE_DDR }, 308 1 + ilog2(DEVDISR_DDR_16), 309 { SVR_MPC8536v1 >> 16 } }, 310 #endif 311 #if defined(MPC8572) 312 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 313 1, { ISOURCE_DDR }, 314 1 + ilog2(DEVDISR_DDR_15), 315 { SVR_MPC8572v1 >> 16 } }, 316 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 317 1, { ISOURCE_DDR }, 318 1 + ilog2(DEVDISR_DDR2_14), 319 { SVR_MPC8572v1 >> 16 } }, 320 #endif 321 { "lbc", LBC_BASE, LBC_SIZE, 0, 322 1, { ISOURCE_LBC }, 323 1 + ilog2(DEVDISR_LBC) }, 324 #if defined(MPC8544) || defined(MPC8536) 325 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 326 1, { ISOURCE_PCIEX }, 327 1 + ilog2(DEVDISR_PCIE), 328 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 329 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 330 1, { ISOURCE_PCIEX2 }, 331 1 + ilog2(DEVDISR_PCIE2), 332 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 333 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 334 1, { ISOURCE_PCIEX3 }, 335 1 + ilog2(DEVDISR_PCIE3), 336 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 337 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 338 1, { ISOURCE_PCI1 }, 339 1 + ilog2(DEVDISR_PCI1), 340 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 341 #endif 342 #ifdef MPC8548 343 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 344 1, { ISOURCE_PCIEX }, 345 1 + ilog2(DEVDISR_PCIE), 346 { SVR_MPC8548v1 >> 16 }, }, 347 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 348 1, { ISOURCE_PCI1 }, 349 1 + ilog2(DEVDISR_PCI1), 350 { SVR_MPC8548v1 >> 16 }, }, 351 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 352 1, { ISOURCE_PCI2 }, 353 1 + ilog2(DEVDISR_PCI2), 354 { SVR_MPC8548v1 >> 16 }, }, 355 #endif 356 #if defined(MPC8572) || defined(P1025) || defined(P2020) 357 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 358 1, { ISOURCE_PCIEX }, 359 1 + ilog2(DEVDISR_PCIE), 360 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 361 SVR_P1025v1 >> 16 } }, 362 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 363 1, { ISOURCE_PCIEX2 }, 364 1 + ilog2(DEVDISR_PCIE2), 365 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 366 SVR_P1025v1 >> 16 } }, 367 #endif 368 #if defined(MPC8572) || defined(P2020) 369 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 370 1, { ISOURCE_PCIEX3_MPC8572 }, 371 1 + ilog2(DEVDISR_PCIE3), 372 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, } }, 373 #endif 374 #if defined(MPC8536) || defined(P1025) || defined(P2020) 375 { "ehci", USB1_BASE, USB_SIZE, 1, 376 1, { ISOURCE_USB1 }, 377 1 + ilog2(DEVDISR_USB1), 378 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16, 379 SVR_P1025v1 >> 16 } }, 380 #endif 381 #ifdef MPC8536 382 { "ehci", USB2_BASE, USB_SIZE, 2, 383 1, { ISOURCE_USB2 }, 384 1 + ilog2(DEVDISR_USB2), 385 { SVR_MPC8536v1 >> 16 }, }, 386 { "ehci", USB3_BASE, USB_SIZE, 3, 387 1, { ISOURCE_USB3 }, 388 1 + ilog2(DEVDISR_USB3), 389 { SVR_MPC8536v1 >> 16 }, }, 390 { "sata", SATA1_BASE, SATA_SIZE, 1, 391 1, { ISOURCE_SATA1 }, 392 1 + ilog2(DEVDISR_SATA1), 393 { SVR_MPC8536v1 >> 16 }, }, 394 { "sata", SATA2_BASE, SATA_SIZE, 2, 395 1, { ISOURCE_SATA2 }, 396 1 + ilog2(DEVDISR_SATA2), 397 { SVR_MPC8536v1 >> 16 }, }, 398 { "spi", SPI_BASE, SPI_SIZE, 0, 399 1, { ISOURCE_SPI }, 400 1 + ilog2(DEVDISR_SPI_15), 401 { SVR_MPC8536v1 >> 16 }, }, 402 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 403 1, { ISOURCE_ESDHC }, 404 1 + ilog2(DEVDISR_ESDHC_12), 405 { SVR_MPC8536v1 >> 16 }, }, 406 #endif 407 #if defined(P1025) || defined(P2020) 408 { "spi", SPI_BASE, SPI_SIZE, 0, 409 1, { ISOURCE_SPI }, 410 1 + ilog2(DEVDISR_SPI_28), 411 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 412 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 413 1, { ISOURCE_ESDHC }, 414 1 + ilog2(DEVDISR_ESDHC_10), 415 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 416 #endif 417 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 418 { NULL } 419 }; 420 421 static int 422 e500_cngetc(dev_t dv) 423 { 424 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 425 426 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 427 return -1; 428 429 return com0addr[com_data] & 0xff; 430 } 431 432 static void 433 e500_cnputc(dev_t dv, int c) 434 { 435 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 436 int timo = 150000; 437 438 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 439 ; 440 441 com0addr[com_data] = c; 442 __asm("mbar"); 443 444 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 445 ; 446 } 447 448 static void * 449 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 450 { 451 if (prefetchable) 452 return NULL; 453 if (pa < gur_bst.pbs_offset) 454 return NULL; 455 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 456 return NULL; 457 return (void *)pa; 458 } 459 460 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 461 462 static void 463 e500_cpu_reset(void) 464 { 465 __asm volatile("sync"); 466 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 467 __asm volatile("msync;isync"); 468 } 469 470 static psize_t 471 memprobe(vaddr_t endkernel) 472 { 473 phys_ram_seg_t *mr; 474 paddr_t boot_page = cpu_read_4(GUR_BPTR); 475 printf(" bptr=%"PRIxPADDR, boot_page); 476 if (boot_page & BPTR_EN) { 477 /* 478 * shift it to an address 479 */ 480 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 481 } else { 482 boot_page = ~(paddr_t)0; 483 } 484 485 /* 486 * First we need to find out how much physical memory we have. 487 * We could let our bootloader tell us, but it's almost as easy 488 * to ask the DDR memory controller. 489 */ 490 mr = physmemr; 491 for (u_int i = 0; i < 4; i++) { 492 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 493 if (v & CS_CONFIG_EN) { 494 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 495 if (v == 0) 496 continue; 497 mr->start = BNDS_SA_GET(v); 498 mr->size = BNDS_SIZE_GET(v); 499 #ifdef MEMSIZE 500 if (mr->start >= MEMSIZE) 501 continue; 502 if (mr->start + mr->size > MEMSIZE) 503 mr->size = MEMSIZE - mr->start; 504 #endif 505 #if 0 506 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 507 mr - physmemr, mr->size, mr->start); 508 #endif 509 mr++; 510 } 511 } 512 513 if (mr == physmemr) 514 panic("no memory configured!"); 515 516 /* 517 * Sort memory regions from low to high and coalesce adjacent regions 518 */ 519 u_int cnt = mr - physmemr; 520 if (cnt > 1) { 521 for (u_int i = 0; i < cnt - 1; i++) { 522 for (u_int j = i + 1; j < cnt; j++) { 523 if (physmemr[j].start < physmemr[i].start) { 524 phys_ram_seg_t tmp = physmemr[i]; 525 physmemr[i] = physmemr[j]; 526 physmemr[j] = tmp; 527 } 528 } 529 } 530 mr = physmemr; 531 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 532 if (mr->start + mr->size == mr[1].start) { 533 mr->size += mr[1].size; 534 for (u_int j = 1; i + j + 1 < cnt; j++) 535 mr[j] = mr[j+1]; 536 cnt--; 537 } 538 } 539 } else if (cnt == 0) { 540 panic("%s: no memory found", __func__); 541 } 542 543 /* 544 * Copy physical memory to available memory. 545 */ 546 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 547 548 /* 549 * Adjust available memory to skip kernel at start of memory. 550 */ 551 availmemr[0].size -= endkernel - availmemr[0].start; 552 availmemr[0].start = endkernel; 553 554 mr = availmemr; 555 for (u_int i = 0; i < cnt; i++, mr++) { 556 /* 557 * U-boot reserves a boot-page on multi-core chips. 558 * We need to make sure that we never disturb it. 559 */ 560 const paddr_t mr_end = mr->start + mr->size; 561 if (mr_end > boot_page && boot_page >= mr->start) { 562 /* 563 * Normally u-boot will put in at the end 564 * of memory. But in case it doesn't, deal 565 * with all possibilities. 566 */ 567 if (boot_page + PAGE_SIZE == mr_end) { 568 mr->size -= PAGE_SIZE; 569 } else if (boot_page == mr->start) { 570 mr->start += PAGE_SIZE; 571 mr->size -= PAGE_SIZE; 572 } else { 573 mr->size = boot_page - mr->start; 574 mr++; 575 for (u_int j = cnt; j > i + 1; j--) { 576 availmemr[j] = availmemr[j-1]; 577 } 578 cnt++; 579 mr->start = boot_page + PAGE_SIZE; 580 mr->size = mr_end - mr->start; 581 } 582 break; 583 } 584 } 585 586 /* 587 * Steal pages at the end of memory for the kernel message buffer. 588 */ 589 mr = availmemr + cnt - 1; 590 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 591 mr->size -= round_page(MSGBUFSIZE); 592 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 593 594 /* 595 * Calculate physmem. 596 */ 597 for (u_int i = 0; i < cnt; i++) 598 physmem += atop(physmemr[i].size); 599 600 nmemr = cnt; 601 return physmemr[cnt-1].start + physmemr[cnt-1].size; 602 } 603 604 void 605 consinit(void) 606 { 607 static bool attached = false; 608 609 if (attached) 610 return; 611 attached = true; 612 613 if (comcnfreq == -1) { 614 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 615 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 616 comcnfreq = e500_sys_clk * plat_ratio; 617 printf(" comcnfreq=%u", comcnfreq); 618 } 619 620 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 621 COM_TYPE_NORMAL, comcnmode); 622 } 623 624 void 625 cpu_probe_cache(void) 626 { 627 struct cpu_info * const ci = curcpu(); 628 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 629 630 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 631 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 632 633 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 634 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 635 636 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 637 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 638 } else { 639 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 640 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 641 } 642 643 #ifdef DEBUG 644 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 645 if ((L1CSR_CE & l1csr0) == 0) 646 printf(" DC=off"); 647 648 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 649 if ((L1CSR_CE & l1csr1) == 0) 650 printf(" IC=off"); 651 #endif 652 } 653 654 static uint16_t 655 getsvr(void) 656 { 657 uint16_t svr = mfspr(SPR_SVR) >> 16; 658 659 svr &= ~0x8; /* clear security bit */ 660 switch (svr) { 661 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 662 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 663 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 664 case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16; 665 default: return svr; 666 } 667 } 668 669 static const char * 670 socname(uint32_t svr) 671 { 672 svr &= ~0x80000; /* clear security bit */ 673 switch (svr >> 8) { 674 case SVR_MPC8533 >> 8: return "MPC8533"; 675 case SVR_MPC8536v1 >> 8: return "MPC8536"; 676 case SVR_MPC8541v1 >> 8: return "MPC8541"; 677 case SVR_MPC8543v2 >> 8: return "MPC8543"; 678 case SVR_MPC8544v1 >> 8: return "MPC8544"; 679 case SVR_MPC8545v2 >> 8: return "MPC8545"; 680 case SVR_MPC8547v2 >> 8: return "MPC8547"; 681 case SVR_MPC8548v2 >> 8: return "MPC8548"; 682 case SVR_MPC8555v1 >> 8: return "MPC8555"; 683 case SVR_MPC8568v1 >> 8: return "MPC8568"; 684 case SVR_MPC8567v1 >> 8: return "MPC8567"; 685 case SVR_MPC8572v1 >> 8: return "MPC8572"; 686 case SVR_P2020v2 >> 8: return "P2020"; 687 case SVR_P2010v2 >> 8: return "P2010"; 688 case SVR_P1016v1 >> 8: return "P1016"; 689 case SVR_P1025v1 >> 8: return "P1025"; 690 default: 691 panic("%s: unknown SVR %#x", __func__, svr); 692 } 693 } 694 695 static void 696 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 697 { 698 static const char units[16] = "KKKKKMMMMMGGGGGT"; 699 700 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 701 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 702 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 703 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 704 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 705 706 aprint_normal_dev(self, "%s:", name); 707 708 aprint_normal(" %u", nentries); 709 if (TLBCFG_AVAIL_P(tlbcfg)) { 710 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 711 minsize, maxsize, units[maxsize_log4k]); 712 } else { 713 aprint_normal(" fixed-size (%uKB)", minsize); 714 } 715 if (assoc == 0 || assoc == nentries) 716 aprint_normal(" fully"); 717 else 718 aprint_normal(" %u-way set", assoc); 719 aprint_normal(" associative entries\n"); 720 } 721 722 static void 723 cpu_print_info(struct cpu_info *ci) 724 { 725 uint64_t freq = board_info_get_number("processor-frequency"); 726 device_t self = ci->ci_dev; 727 728 char freqbuf[10]; 729 if (freq >= 999500000) { 730 const uint32_t freq32 = (freq + 500000) / 10000000; 731 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 732 freq32 / 100, freq32 % 100); 733 } else { 734 const uint32_t freq32 = (freq + 500000) / 1000000; 735 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 736 } 737 738 const uint32_t pvr = mfpvr(); 739 const uint32_t svr = mfspr(SPR_SVR); 740 const uint32_t pir = mfspr(SPR_PIR); 741 742 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 743 "ID %u%s\n", 744 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 745 (svr >> 4) & 15, svr & 15, 746 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 747 (pvr >> 4) & 15, pvr & 15, 748 pir, (pir == 0 ? " (Primary)" : "")); 749 750 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 751 aprint_normal_dev(self, 752 "%uKB/%uB %u-way L1 %s cache\n", 753 L1CFG_CSIZE_GET(l1cfg0) >> 10, 754 32 << L1CFG_CBSIZE_GET(l1cfg0), 755 L1CFG_CNWAY_GET(l1cfg0), 756 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 757 ? "data" : "unified"); 758 759 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 760 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 761 aprint_normal_dev(self, 762 "%uKB/%uB %u-way L1 %s cache\n", 763 L1CFG_CSIZE_GET(l1cfg1) >> 10, 764 32 << L1CFG_CBSIZE_GET(l1cfg1), 765 L1CFG_CNWAY_GET(l1cfg1), 766 "instruction"); 767 } 768 769 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 770 aprint_normal_dev(self, 771 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 772 MMUCFG_NTLBS_GET(mmucfg) + 1, 773 MMUCFG_NPIDS_GET(mmucfg), 774 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 775 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 776 777 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 778 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 779 } 780 781 #ifdef MULTIPROCESSOR 782 static void 783 e500_cpu_spinup(device_t self, struct cpu_info *ci) 784 { 785 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 786 struct pglist splist; 787 788 if (spinup_table_addr == 0) { 789 aprint_error_dev(self, "hatch failed (no spin-up table)"); 790 return; 791 } 792 793 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 794 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 795 const size_t id = cpu_index(ci); 796 volatile __cpuset_t * const hatchlings = &cpuset_info.cpus_hatched; 797 798 if (h->hatch_sp == 0) { 799 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 800 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 801 if (error) { 802 aprint_error_dev(self, 803 "unable to allocate hatch stack\n"); 804 return; 805 } 806 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 807 + PAGE_SIZE - CALLFRAMELEN; 808 } 809 810 811 for (size_t i = 1; e[i].entry_pir != 0; i++) { 812 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 813 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 814 if (e[i].entry_pir == ci->ci_cpuid) { 815 816 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 817 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 818 ci->ci_curpm = pmap_kernel(); 819 ci->ci_lasttb = cpu_info[0].ci_lasttb; 820 ci->ci_data.cpu_cc_freq = 821 cpu_info[0].ci_data.cpu_cc_freq; 822 823 h->hatch_self = self; 824 h->hatch_ci = ci; 825 h->hatch_running = -1; 826 h->hatch_pir = e[i].entry_pir; 827 h->hatch_hid0 = mfspr(SPR_HID0); 828 KASSERT(h->hatch_sp != 0); 829 /* 830 * Get new timebase. We don't want to deal with 831 * timebase crossing a 32-bit boundary so make sure 832 * that we have enough headroom to do the timebase 833 * synchronization. 834 */ 835 #define TBSYNC_SLOP 2000 836 uint32_t tbl; 837 uint32_t tbu; 838 do { 839 tbu = mfspr(SPR_RTBU); 840 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 841 } while (tbl < TBSYNC_SLOP); 842 843 h->hatch_tbu = tbu; 844 h->hatch_tbl = tbl; 845 __asm("sync;isync"); 846 dcache_wbinv((vaddr_t)h, sizeof(*h)); 847 848 #if 1 849 /* 850 * And here we go... 851 */ 852 e[i].entry_addr_lower = 853 (uint32_t)e500_spinup_trampoline; 854 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 855 __asm __volatile("sync;isync"); 856 __insn_barrier(); 857 858 for (u_int timo = 0; timo++ < 10000; ) { 859 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 860 if (e[i].entry_addr_lower == 3) { 861 printf( 862 "%s: cpu%u started in %u spins\n", 863 __func__, cpu_index(ci), timo); 864 break; 865 } 866 } 867 for (u_int timo = 0; timo++ < 10000; ) { 868 dcache_inv((vaddr_t)h, sizeof(*h)); 869 if (h->hatch_running == 0) { 870 printf( 871 "%s: cpu%u cracked in %u spins: (running=%d)\n", 872 __func__, cpu_index(ci), 873 timo, h->hatch_running); 874 break; 875 } 876 } 877 if (h->hatch_running == -1) { 878 aprint_error_dev(self, 879 "hatch failed (timeout): running=%d" 880 ", entry=%#x\n", 881 h->hatch_running, e[i].entry_addr_lower); 882 goto out; 883 } 884 #endif 885 886 /* 887 * First then we do is to synchronize timebases. 888 * TBSYNC_SLOP*16 should be more than enough 889 * instructions. 890 */ 891 while (tbl != mftbl()) 892 continue; 893 h->hatch_running = 1; 894 dcache_wbinv((vaddr_t)h, sizeof(*h)); 895 __asm("sync;isync"); 896 __insn_barrier(); 897 898 for (u_int timo = 10000; timo-- > 0; ) { 899 dcache_inv((vaddr_t)h, sizeof(*h)); 900 if (h->hatch_running > 1) 901 break; 902 } 903 if (h->hatch_running == 1) { 904 printf( 905 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 906 __func__, 907 ((int64_t)tbu << 32) + tbl, 908 (int64_t) 909 (((uint64_t)h->hatch_tbu << 32) 910 + (uint64_t)h->hatch_tbl), 911 h->hatch_running); 912 goto out; 913 } 914 printf( 915 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 916 __func__, 917 (int64_t) 918 (((uint64_t)h->hatch_tbu << 32) 919 + (uint64_t)h->hatch_tbl), 920 h->hatch_running); 921 /* 922 * Now we wait for the hatching to complete. 10ms 923 * should be long enough. 924 */ 925 for (u_int timo = 10000; timo-- > 0; ) { 926 if (CPUSET_HAS_P(*hatchlings, id)) { 927 aprint_normal_dev(self, 928 "hatch successful (%u spins, " 929 "timebase adjusted by %"PRId64")\n", 930 10000 - timo, 931 (int64_t) 932 (((uint64_t)h->hatch_tbu << 32) 933 + (uint64_t)h->hatch_tbl)); 934 goto out; 935 } 936 DELAY(1); 937 } 938 939 aprint_error_dev(self, 940 "hatch failed (timeout): running=%u\n", 941 h->hatch_running); 942 goto out; 943 } 944 } 945 946 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 947 ci->ci_cpuid); 948 out: 949 if (h->hatch_sp == 0) 950 uvm_pglistfree(&splist); 951 } 952 #endif 953 954 void 955 e500_cpu_hatch(struct cpu_info *ci) 956 { 957 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 958 959 /* 960 * Make sure interrupts are blocked. 961 */ 962 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 963 964 intr_cpu_hatch(ci); 965 966 cpu_print_info(ci); 967 968 /* 969 */ 970 } 971 972 static void 973 e500_cpu_attach(device_t self, u_int instance) 974 { 975 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 976 977 if (instance > 1) { 978 #if defined(MULTIPROCESSOR) 979 ci->ci_idepth = -1; 980 self->dv_private = ci; 981 982 ci->ci_cpuid = instance - (instance > 0); 983 ci->ci_dev = self; 984 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 985 986 mi_cpu_attach(ci); 987 988 intr_cpu_attach(ci); 989 cpu_evcnt_attach(ci); 990 991 e500_cpu_spinup(self, ci); 992 return; 993 #else 994 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 995 return; 996 #endif 997 } 998 999 self->dv_private = ci; 1000 1001 ci->ci_cpuid = instance - (instance > 0); 1002 ci->ci_dev = self; 1003 1004 intr_cpu_attach(ci); 1005 cpu_evcnt_attach(ci); 1006 1007 KASSERT(ci == curcpu()); 1008 intr_cpu_hatch(ci); 1009 1010 cpu_print_info(ci); 1011 } 1012 1013 void 1014 e500_ipi_halt(void) 1015 { 1016 register_t msr, hid0; 1017 1018 msr = wrtee(0); 1019 1020 hid0 = mfspr(SPR_HID0); 1021 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 1022 mtspr(SPR_HID0, hid0); 1023 1024 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 1025 mtmsr(msr); 1026 for (;;); /* loop forever */ 1027 } 1028 1029 1030 static void 1031 calltozero(void) 1032 { 1033 panic("call to 0 from %p", __builtin_return_address(0)); 1034 } 1035 1036 void 1037 initppc(vaddr_t startkernel, vaddr_t endkernel, 1038 void *a0, void *a1, void *a2, void *a3) 1039 { 1040 struct cpu_info * const ci = curcpu(); 1041 struct cpu_softc * const cpu = ci->ci_softc; 1042 1043 cn_tab = &e500_earlycons; 1044 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 1045 startkernel, endkernel, a0, a1, a2, a3); 1046 1047 /* 1048 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 1049 * DOZE is ok. 1050 */ 1051 const register_t hid0 = mfspr(SPR_HID0); 1052 mtspr(SPR_HID0, 1053 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1054 #ifdef CADMUS 1055 /* 1056 * Need to cache this from cadmus since we need to unmap cadmus since 1057 * it falls in the middle of kernel address space. 1058 */ 1059 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1060 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1061 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1062 printf(" cadmus_pci=%#x", cadmus_pci); 1063 printf(" cadmus_csr=%#x", cadmus_csr); 1064 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1065 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1066 e500_sys_clk *= 2; 1067 } 1068 #endif 1069 #ifdef PIXIS 1070 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1071 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1072 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1073 #ifndef SYS_CLK 1074 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1075 #else 1076 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1077 #endif 1078 #endif 1079 printf(" porpllsr=0x%08x", 1080 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1081 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1082 1083 /* 1084 * Make sure arguments are page aligned. 1085 */ 1086 startkernel = trunc_page(startkernel); 1087 endkernel = round_page(endkernel); 1088 1089 /* 1090 * Initialize the bus space tag used to access the 85xx general 1091 * utility registers. It doesn't need to be extent protected. 1092 * We know the GUR is mapped via a TLB1 entry so we add a limited 1093 * mapiodev which allows mappings in GUR space. 1094 */ 1095 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1096 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1097 bus_space_init(&gur_bst, NULL, NULL, 0); 1098 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1099 cpu->cpu_bst = &gur_bst; 1100 cpu->cpu_le_bst = &gur_le_bst; 1101 cpu->cpu_bsh = gur_bsh; 1102 1103 /* 1104 * Attach the console early, really early. 1105 */ 1106 consinit(); 1107 1108 /* 1109 * Reset the PIC to a known state. 1110 */ 1111 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1112 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1113 ; 1114 #if 0 1115 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1116 #endif 1117 printf(" openpic-reset(ctpr=%u)", 1118 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1119 1120 /* 1121 * fill in with an absolute branch to a routine that will panic. 1122 */ 1123 *(int *)0 = 0x48000002 | (int) calltozero; 1124 1125 /* 1126 * Get the cache sizes. 1127 */ 1128 cpu_probe_cache(); 1129 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1130 ci->ci_ci.dcache_size >> 10, 1131 ci->ci_ci.dcache_line_size, 1132 ci->ci_ci.icache_size >> 10, 1133 ci->ci_ci.icache_line_size); 1134 1135 /* 1136 * Now find out how much memory is attached 1137 */ 1138 pmemsize = memprobe(endkernel); 1139 cpu->cpu_highmem = pmemsize; 1140 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1141 1142 /* 1143 * Now we need cleanout the TLB of stuff that we don't need. 1144 */ 1145 e500_tlb_init(endkernel, pmemsize); 1146 printf(" e500_tlbinit(%#lx,%zuMB)", 1147 endkernel, (size_t) (pmemsize >> 20)); 1148 1149 /* 1150 * 1151 */ 1152 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1153 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1154 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1155 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1156 1157 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1158 1159 /* 1160 * Initialize the message buffer. 1161 */ 1162 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1163 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1164 1165 /* 1166 * Initialize exception vectors and interrupts 1167 */ 1168 exception_init(&e500_intrsw); 1169 1170 printf(" exception_init=%p", &e500_intrsw); 1171 1172 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1173 1174 /* 1175 * Set the page size. 1176 */ 1177 uvm_setpagesize(); 1178 1179 /* 1180 * Initialize the pmap. 1181 */ 1182 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1183 1184 /* 1185 * Let's take all the indirect calls via our stubs and patch 1186 * them to be direct calls. 1187 */ 1188 cpu_fixup_stubs(); 1189 1190 /* 1191 * As a debug measure we can change the TLB entry that maps all of 1192 * memory to one that encompasses the 64KB with the kernel vectors. 1193 * All other pages will be soft faulted into the TLB as needed. 1194 */ 1195 e500_tlb_minimize(endkernel); 1196 1197 /* 1198 * Set some more MD helpers 1199 */ 1200 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1201 cpu_md_ops.md_device_register = e500_device_register; 1202 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1203 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1204 #if NGPIO > 0 1205 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1206 #endif 1207 1208 printf(" initppc done!\n"); 1209 1210 /* 1211 * Look for the Book-E modules in the right place. 1212 */ 1213 module_machine = module_machine_booke; 1214 } 1215 1216 #ifdef MPC8548 1217 static const char * const mpc8548cds_extirq_names[] = { 1218 [0] = "pci inta", 1219 [1] = "pci intb", 1220 [2] = "pci intc", 1221 [3] = "pci intd", 1222 [4] = "irq4", 1223 [5] = "gige phy", 1224 [6] = "atm phy", 1225 [7] = "cpld", 1226 [8] = "irq8", 1227 [9] = "nvram", 1228 [10] = "debug", 1229 [11] = "pci2 inta", 1230 }; 1231 #endif 1232 1233 static const char * const mpc85xx_extirq_names[] = { 1234 [0] = "extirq 0", 1235 [1] = "extirq 1", 1236 [2] = "extirq 2", 1237 [3] = "extirq 3", 1238 [4] = "extirq 4", 1239 [5] = "extirq 5", 1240 [6] = "extirq 6", 1241 [7] = "extirq 7", 1242 [8] = "extirq 8", 1243 [9] = "extirq 9", 1244 [10] = "extirq 10", 1245 [11] = "extirq 11", 1246 }; 1247 1248 static void 1249 mpc85xx_extirq_setup(void) 1250 { 1251 #ifdef MPC8548 1252 const char * const * names = mpc8548cds_extirq_names; 1253 const size_t n = __arraycount(mpc8548cds_extirq_names); 1254 #else 1255 const char * const * names = mpc85xx_extirq_names; 1256 const size_t n = __arraycount(mpc85xx_extirq_names); 1257 #endif 1258 prop_array_t extirqs = prop_array_create_with_capacity(n); 1259 for (u_int i = 0; i < n; i++) { 1260 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1261 prop_array_set(extirqs, i, ps); 1262 prop_object_release(ps); 1263 } 1264 board_info_add_object("external-irqs", extirqs); 1265 prop_object_release(extirqs); 1266 } 1267 1268 static void 1269 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1270 { 1271 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1272 KASSERT(pci_intmap != NULL); 1273 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1274 KASSERT(mask != NULL); 1275 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1276 prop_object_release(mask); 1277 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1278 KASSERT(pn_ist != NULL); 1279 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1280 KASSERT(pn_intr != NULL); 1281 prop_dictionary_t entry = prop_dictionary_create(); 1282 KASSERT(entry != NULL); 1283 prop_dictionary_set(entry, "interrupt", pn_intr); 1284 prop_dictionary_set(entry, "type", pn_ist); 1285 prop_dictionary_set(pci_intmap, "000000", entry); 1286 prop_object_release(pn_intr); 1287 prop_object_release(entry); 1288 va_list ap; 1289 va_start(ap, inta); 1290 u_int intrinc = __LOWEST_SET_BIT(intmask); 1291 for (u_int i = 0; i < intmask; i += intrinc) { 1292 char prop_name[12]; 1293 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1294 entry = prop_dictionary_create(); 1295 KASSERT(entry != NULL); 1296 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1297 KASSERT(pn_intr != NULL); 1298 prop_dictionary_set(entry, "interrupt", pn_intr); 1299 prop_dictionary_set(entry, "type", pn_ist); 1300 prop_dictionary_set(pci_intmap, prop_name, entry); 1301 prop_object_release(pn_intr); 1302 prop_object_release(entry); 1303 } 1304 va_end(ap); 1305 prop_object_release(pn_ist); 1306 board_info_add_object(name, pci_intmap); 1307 prop_object_release(pci_intmap); 1308 } 1309 1310 void 1311 cpu_startup(void) 1312 { 1313 struct cpu_info * const ci = curcpu(); 1314 const uint16_t svr = getsvr(); 1315 1316 powersave = 0; /* we can do it but turn it on by default */ 1317 1318 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1319 1320 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1321 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1322 uint32_t e500_ratio = E500_RATIO_GET(v); 1323 1324 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1325 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1326 1327 ci->ci_khz = (cpu_freq + 500) / 1000; 1328 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1329 1330 board_info_add_number("my-id", svr); 1331 board_info_add_bool("pq3"); 1332 board_info_add_number("mem-size", pmemsize); 1333 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1334 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1335 uint32_t l2banks = l2siz >> 16; 1336 #ifdef MPC85555 1337 if (svr == (MPC8555v1 >> 16)) { 1338 l2siz >>= 1; 1339 l2banks >>= 1; 1340 } 1341 #endif 1342 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1343 if (boot_page & BPTR_EN) { 1344 bool found = false; 1345 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1346 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1347 * const bp = (void *)boot_page; 1348 bp <= dp; dp--) { 1349 if (*dp == boot_page) { 1350 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1351 spinup_table_addr = 1352 roundup2(spinup_table_addr, 32); 1353 board_info_add_number("mp-boot-page", 1354 boot_page); 1355 board_info_add_number("mp-spin-up-table", 1356 spinup_table_addr); 1357 printf("Found MP boot page @ %#"PRIxPADDR". " 1358 "Spin-up table @ %#"PRIxPTR"\n", 1359 boot_page, spinup_table_addr); 1360 found = true; 1361 break; 1362 } 1363 } 1364 if (!found) { 1365 printf("Found MP boot page @ %#"PRIxPADDR 1366 " with missing U-boot signature!\n", boot_page); 1367 board_info_add_number("mp-spin-up-table", 0); 1368 } 1369 } 1370 board_info_add_number("l2-cache-size", l2siz); 1371 board_info_add_number("l2-cache-line-size", 32); 1372 board_info_add_number("l2-cache-banks", l2banks); 1373 board_info_add_number("l2-cache-ways", 8); 1374 1375 board_info_add_number("processor-frequency", cpu_freq); 1376 board_info_add_number("bus-frequency", ccb_freq); 1377 board_info_add_number("pci-frequency", e500_sys_clk); 1378 board_info_add_number("timebase-frequency", ccb_freq / 8); 1379 1380 #ifdef CADMUS 1381 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1382 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1383 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1384 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1385 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1386 #else 1387 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1388 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1389 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1390 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1391 #endif 1392 1393 uint64_t macstnaddr = 1394 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1395 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1396 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1397 1398 #if NPCI > 0 && defined(PCI_MEMBASE) 1399 pcimem_ex = extent_create("pcimem", 1400 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1401 NULL, 0, EX_WAITOK); 1402 #endif 1403 #if NPCI > 0 && defined(PCI_IOBASE) 1404 pciio_ex = extent_create("pciio", 1405 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1406 NULL, 0, EX_WAITOK); 1407 #endif 1408 mpc85xx_extirq_setup(); 1409 /* 1410 * PCI-Express virtual wire interrupts on combined with 1411 * External IRQ0/1/2/3. 1412 */ 1413 switch (svr) { 1414 #if defined(MPC8548) 1415 case SVR_MPC8548v1 >> 16: 1416 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1417 IST_LEVEL, 0, 1, 2, 3); 1418 break; 1419 #endif 1420 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \ 1421 || defined(P1025) || defined(P2020) 1422 case SVR_MPC8536v1 >> 16: 1423 case SVR_MPC8544v1 >> 16: 1424 case SVR_MPC8572v1 >> 16: 1425 case SVR_P1016v1 >> 16: 1426 case SVR_P2010v2 >> 16: 1427 case SVR_P2020v2 >> 16: 1428 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1429 8, 9, 10, 11); 1430 /* FALLTHROUGH */ 1431 case SVR_P1025v1 >> 16: 1432 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1433 4, 5, 6, 7); 1434 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1435 0, 1, 2, 3); 1436 break; 1437 #endif 1438 } 1439 switch (svr) { 1440 #if defined(MPC8536) 1441 case SVR_MPC8536v1 >> 16: 1442 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1443 1, 2, 3, 4); 1444 break; 1445 #endif 1446 #if defined(MPC8544) 1447 case SVR_MPC8544v1 >> 16: 1448 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1449 0, 1, 2, 3); 1450 break; 1451 #endif 1452 #if defined(MPC8548) 1453 case SVR_MPC8548v1 >> 16: 1454 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1455 0, 1, 2, 3); 1456 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1457 11, 1, 2, 3); 1458 break; 1459 #endif 1460 } 1461 } 1462
Indexes created Tue Sep 30 07:10:03 GMT 2025