machdep.c revision 1.28
1 /* $NetBSD: machdep.c,v 1.28 2012/07/22 23:46:10 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_altivec.h" 42 #include "opt_ddb.h" 43 #include "opt_mpc85xx.h" 44 #include "opt_pci.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <dev/cons.h> 70 71 #include <dev/ic/comreg.h> 72 #include <dev/ic/comvar.h> 73 74 #include <net/if.h> 75 #include <net/if_media.h> 76 #include <dev/mii/miivar.h> 77 78 #include <powerpc/cpuset.h> 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 struct uboot_bdinfo { 96 uint32_t bd_memstart; 97 uint32_t bd_memsize; 98 uint32_t bd_flashstart; 99 uint32_t bd_flashsize; 100 /*10*/ uint32_t bd_flashoffset; 101 uint32_t bd_sramstart; 102 uint32_t bd_sramsize; 103 uint32_t bd_immrbase; 104 /*20*/ uint32_t bd_bootflags; 105 uint32_t bd_ipaddr; 106 uint8_t bd_etheraddr[6]; 107 uint16_t bd_ethspeed; 108 /*30*/ uint32_t bd_intfreq; 109 uint32_t bd_cpufreq; 110 uint32_t bd_baudrate; 111 /*3c*/ uint8_t bd_etheraddr1[6]; 112 /*42*/ uint8_t bd_etheraddr2[6]; 113 /*48*/ uint8_t bd_etheraddr3[6]; 114 /*4e*/ uint16_t bd_pad; 115 }; 116 117 /* 118 * booke kernels need to set module_machine to this for modules to work. 119 */ 120 char module_machine_booke[] = "powerpc-booke"; 121 122 void initppc(vaddr_t, vaddr_t, void *, void *, void *, void *); 123 124 #define MEMREGIONS 4 125 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 126 phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 127 static u_int nmemr; 128 129 #ifndef CONSFREQ 130 # define CONSFREQ -1 /* inherit from firmware */ 131 #endif 132 #ifndef CONSPEED 133 # define CONSPEED 115200 134 #endif 135 #ifndef CONMODE 136 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 137 #endif 138 #ifndef CONSADDR 139 # define CONSADDR DUART2_BASE 140 #endif 141 142 int comcnfreq = CONSFREQ; 143 int comcnspeed = CONSPEED; 144 tcflag_t comcnmode = CONMODE; 145 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 146 147 #if NPCI > 0 148 struct extent *pcimem_ex; 149 struct extent *pciio_ex; 150 #endif 151 152 struct powerpc_bus_space gur_bst = { 153 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 154 .pbs_offset = GUR_BASE, 155 .pbs_limit = GUR_SIZE, 156 }; 157 158 struct powerpc_bus_space gur_le_bst = { 159 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 160 .pbs_offset = GUR_BASE, 161 .pbs_limit = GUR_SIZE, 162 }; 163 164 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 165 166 #if defined(SYS_CLK) 167 static uint64_t e500_sys_clk = SYS_CLK; 168 #endif 169 #ifdef CADMUS 170 static uint8_t cadmus_pci; 171 static uint8_t cadmus_csr; 172 #ifndef SYS_CLK 173 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 174 #endif 175 #elif defined(PIXIS) 176 static const uint32_t pixis_spd_map[8] = { 177 [PX_SPD_33MHZ] = 33333333, 178 [PX_SPD_40MHZ] = 40000000, 179 [PX_SPD_50MHZ] = 50000000, 180 [PX_SPD_66MHZ] = 66666666, 181 [PX_SPD_83MHZ] = 83333333, 182 [PX_SPD_100MHZ] = 100000000, 183 [PX_SPD_133MHZ] = 133333333, 184 [PX_SPD_166MHZ] = 166666667, 185 }; 186 static uint8_t pixis_spd; 187 #ifndef SYS_CLK 188 static uint64_t e500_sys_clk; 189 #endif 190 #elif !defined(SYS_CLK) 191 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 192 #endif 193 194 static int e500_cngetc(dev_t); 195 static void e500_cnputc(dev_t, int); 196 197 static struct consdev e500_earlycons = { 198 .cn_getc = e500_cngetc, 199 .cn_putc = e500_cnputc, 200 .cn_pollc = nullcnpollc, 201 }; 202 203 /* 204 * List of port-specific devices to attach to the processor local bus. 205 */ 206 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 207 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 208 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 209 SVR_P1025v1 >> 16 } }, 210 #if defined(MPC8572) || defined(P2020) || defined(P1025) 211 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 212 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 213 SVR_P1025v1 >> 16 } }, 214 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 215 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 216 SVR_P1025v1 >> 16 } }, 217 #endif 218 { "wdog" }, /* not a real device */ 219 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 220 1, { ISOURCE_DUART }, 221 1 + ilog2(DEVDISR_DUART) }, 222 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 223 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 224 1 + ilog2(DEVDISR_TSEC1), 225 { 0xffff, SVR_P1025v1 >> 16 } }, 226 #if defined(P1025) 227 { "mdio", ETSEC1_BASE, ETSEC_SIZE, 1, 228 0, { }, 229 1 + ilog2(DEVDISR_TSEC1), 230 { SVR_P1025v1 >> 16 } }, 231 { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1, 232 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 233 1 + ilog2(DEVDISR_TSEC1), 234 { SVR_P1025v1 >> 16 } }, 235 #if 0 236 { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1, 237 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX, 238 ISOURCE_ETSEC1_G1_ERR }, 239 1 + ilog2(DEVDISR_TSEC1), 240 { SVR_P1025v1 >> 16 } }, 241 #endif 242 #endif 243 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \ 244 || defined(P2020) 245 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 246 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 247 1 + ilog2(DEVDISR_TSEC2), 248 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 249 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 250 SVR_P1025v1 >> 16 } }, 251 #endif 252 #if defined(P1025) 253 { "mdio", ETSEC2_BASE, ETSEC_SIZE, 2, 254 0, { }, 255 1 + ilog2(DEVDISR_TSEC2), 256 { SVR_P1025v1 >> 16 } }, 257 { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2, 258 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 259 1 + ilog2(DEVDISR_TSEC2), 260 { SVR_P1025v1 >> 16 } }, 261 #if 0 262 { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5, 263 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX, 264 ISOURCE_ETSEC2_G1_ERR }, 265 1 + ilog2(DEVDISR_TSEC2), 266 { SVR_P1025v1 >> 16 } }, 267 #endif 268 #endif 269 #if defined(MPC8544) || defined(MPC8536) 270 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 271 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 272 1 + ilog2(DEVDISR_TSEC3), 273 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 274 #endif 275 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 276 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 277 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 278 1 + ilog2(DEVDISR_TSEC3), 279 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 280 SVR_P2020v2 >> 16 } }, 281 #endif 282 #if defined(P1025) 283 { "mdio", ETSEC3_BASE, ETSEC_SIZE, 3, 284 0, { }, 285 1 + ilog2(DEVDISR_TSEC3), 286 { SVR_P1025v1 >> 16 } }, 287 { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3, 288 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 289 1 + ilog2(DEVDISR_TSEC3), 290 { SVR_P1025v1 >> 16 } }, 291 #if 0 292 { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3, 293 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX, 294 ISOURCE_ETSEC3_G1_ERR }, 295 1 + ilog2(DEVDISR_TSEC3), 296 { SVR_P1025v1 >> 16 } }, 297 #endif 298 #endif 299 #if defined(MPC8548) || defined(MPC8572) 300 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 301 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 302 1 + ilog2(DEVDISR_TSEC4), 303 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 304 #endif 305 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 306 1, { ISOURCE_I2C }, 307 1 + ilog2(DEVDISR_I2C) }, 308 /* MPC8572 doesn't have any GPIO */ 309 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 310 1, { ISOURCE_GPIO }, 311 0, 312 { 0xffff, SVR_MPC8572v1 >> 16 } }, 313 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 314 1, { ISOURCE_DDR }, 315 1 + ilog2(DEVDISR_DDR_15), 316 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 317 #if defined(MPC8536) 318 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 319 1, { ISOURCE_DDR }, 320 1 + ilog2(DEVDISR_DDR_16), 321 { SVR_MPC8536v1 >> 16 } }, 322 #endif 323 #if defined(MPC8572) 324 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 325 1, { ISOURCE_DDR }, 326 1 + ilog2(DEVDISR_DDR_15), 327 { SVR_MPC8572v1 >> 16 } }, 328 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 329 1, { ISOURCE_DDR }, 330 1 + ilog2(DEVDISR_DDR2_14), 331 { SVR_MPC8572v1 >> 16 } }, 332 #endif 333 { "lbc", LBC_BASE, LBC_SIZE, 0, 334 1, { ISOURCE_LBC }, 335 1 + ilog2(DEVDISR_LBC) }, 336 #if defined(MPC8544) || defined(MPC8536) 337 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 338 1, { ISOURCE_PCIEX }, 339 1 + ilog2(DEVDISR_PCIE), 340 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 341 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 342 1, { ISOURCE_PCIEX2 }, 343 1 + ilog2(DEVDISR_PCIE2), 344 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 345 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 346 1, { ISOURCE_PCIEX3 }, 347 1 + ilog2(DEVDISR_PCIE3), 348 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 349 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 350 1, { ISOURCE_PCI1 }, 351 1 + ilog2(DEVDISR_PCI1), 352 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 353 #endif 354 #ifdef MPC8548 355 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 356 1, { ISOURCE_PCIEX }, 357 1 + ilog2(DEVDISR_PCIE), 358 { SVR_MPC8548v1 >> 16 }, }, 359 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 360 1, { ISOURCE_PCI1 }, 361 1 + ilog2(DEVDISR_PCI1), 362 { SVR_MPC8548v1 >> 16 }, }, 363 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 364 1, { ISOURCE_PCI2 }, 365 1 + ilog2(DEVDISR_PCI2), 366 { SVR_MPC8548v1 >> 16 }, }, 367 #endif 368 #if defined(MPC8572) || defined(P1025) || defined(P2020) 369 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 370 1, { ISOURCE_PCIEX }, 371 1 + ilog2(DEVDISR_PCIE), 372 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 373 SVR_P1025v1 >> 16 } }, 374 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 375 1, { ISOURCE_PCIEX2 }, 376 1 + ilog2(DEVDISR_PCIE2), 377 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 378 SVR_P1025v1 >> 16 } }, 379 #endif 380 #if defined(MPC8572) || defined(P2020) 381 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 382 1, { ISOURCE_PCIEX3_MPC8572 }, 383 1 + ilog2(DEVDISR_PCIE3), 384 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, } }, 385 #endif 386 #if defined(MPC8536) || defined(P1025) || defined(P2020) 387 { "ehci", USB1_BASE, USB_SIZE, 1, 388 1, { ISOURCE_USB1 }, 389 1 + ilog2(DEVDISR_USB1), 390 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16, 391 SVR_P1025v1 >> 16 } }, 392 #endif 393 #ifdef MPC8536 394 { "ehci", USB2_BASE, USB_SIZE, 2, 395 1, { ISOURCE_USB2 }, 396 1 + ilog2(DEVDISR_USB2), 397 { SVR_MPC8536v1 >> 16 }, }, 398 { "ehci", USB3_BASE, USB_SIZE, 3, 399 1, { ISOURCE_USB3 }, 400 1 + ilog2(DEVDISR_USB3), 401 { SVR_MPC8536v1 >> 16 }, }, 402 { "sata", SATA1_BASE, SATA_SIZE, 1, 403 1, { ISOURCE_SATA1 }, 404 1 + ilog2(DEVDISR_SATA1), 405 { SVR_MPC8536v1 >> 16 }, }, 406 { "sata", SATA2_BASE, SATA_SIZE, 2, 407 1, { ISOURCE_SATA2 }, 408 1 + ilog2(DEVDISR_SATA2), 409 { SVR_MPC8536v1 >> 16 }, }, 410 { "spi", SPI_BASE, SPI_SIZE, 0, 411 1, { ISOURCE_SPI }, 412 1 + ilog2(DEVDISR_SPI_15), 413 { SVR_MPC8536v1 >> 16 }, }, 414 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 415 1, { ISOURCE_ESDHC }, 416 1 + ilog2(DEVDISR_ESDHC_12), 417 { SVR_MPC8536v1 >> 16 }, }, 418 #endif 419 #if defined(P1025) || defined(P2020) 420 { "spi", SPI_BASE, SPI_SIZE, 0, 421 1, { ISOURCE_SPI }, 422 1 + ilog2(DEVDISR_SPI_28), 423 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 424 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 425 1, { ISOURCE_ESDHC }, 426 1 + ilog2(DEVDISR_ESDHC_10), 427 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 428 #endif 429 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 430 { NULL } 431 }; 432 433 static int 434 e500_cngetc(dev_t dv) 435 { 436 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 437 438 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 439 return -1; 440 441 return com0addr[com_data] & 0xff; 442 } 443 444 static void 445 e500_cnputc(dev_t dv, int c) 446 { 447 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 448 int timo = 150000; 449 450 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 451 ; 452 453 com0addr[com_data] = c; 454 __asm("mbar"); 455 456 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 457 ; 458 } 459 460 static void * 461 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 462 { 463 if (prefetchable) 464 return NULL; 465 if (pa < gur_bst.pbs_offset) 466 return NULL; 467 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 468 return NULL; 469 return (void *)pa; 470 } 471 472 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 473 474 static void 475 e500_cpu_reset(void) 476 { 477 __asm volatile("sync"); 478 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 479 __asm volatile("msync;isync"); 480 } 481 482 static psize_t 483 memprobe(vaddr_t endkernel) 484 { 485 phys_ram_seg_t *mr; 486 paddr_t boot_page = cpu_read_4(GUR_BPTR); 487 printf(" bptr=%"PRIxPADDR, boot_page); 488 if (boot_page & BPTR_EN) { 489 /* 490 * shift it to an address 491 */ 492 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 493 } else { 494 boot_page = ~(paddr_t)0; 495 } 496 497 /* 498 * First we need to find out how much physical memory we have. 499 * We could let our bootloader tell us, but it's almost as easy 500 * to ask the DDR memory controller. 501 */ 502 mr = physmemr; 503 for (u_int i = 0; i < 4; i++) { 504 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 505 if (v & CS_CONFIG_EN) { 506 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 507 if (v == 0) 508 continue; 509 mr->start = BNDS_SA_GET(v); 510 mr->size = BNDS_SIZE_GET(v); 511 #ifdef MEMSIZE 512 if (mr->start >= MEMSIZE) 513 continue; 514 if (mr->start + mr->size > MEMSIZE) 515 mr->size = MEMSIZE - mr->start; 516 #endif 517 #if 0 518 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 519 mr - physmemr, mr->size, mr->start); 520 #endif 521 mr++; 522 } 523 } 524 525 if (mr == physmemr) 526 panic("no memory configured!"); 527 528 /* 529 * Sort memory regions from low to high and coalesce adjacent regions 530 */ 531 u_int cnt = mr - physmemr; 532 if (cnt > 1) { 533 for (u_int i = 0; i < cnt - 1; i++) { 534 for (u_int j = i + 1; j < cnt; j++) { 535 if (physmemr[j].start < physmemr[i].start) { 536 phys_ram_seg_t tmp = physmemr[i]; 537 physmemr[i] = physmemr[j]; 538 physmemr[j] = tmp; 539 } 540 } 541 } 542 mr = physmemr; 543 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 544 if (mr->start + mr->size == mr[1].start) { 545 mr->size += mr[1].size; 546 for (u_int j = 1; i + j + 1 < cnt; j++) 547 mr[j] = mr[j+1]; 548 cnt--; 549 } 550 } 551 } else if (cnt == 0) { 552 panic("%s: no memory found", __func__); 553 } 554 555 /* 556 * Copy physical memory to available memory. 557 */ 558 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 559 560 /* 561 * Adjust available memory to skip kernel at start of memory. 562 */ 563 availmemr[0].size -= endkernel - availmemr[0].start; 564 availmemr[0].start = endkernel; 565 566 mr = availmemr; 567 for (u_int i = 0; i < cnt; i++, mr++) { 568 /* 569 * U-boot reserves a boot-page on multi-core chips. 570 * We need to make sure that we never disturb it. 571 */ 572 const paddr_t mr_end = mr->start + mr->size; 573 if (mr_end > boot_page && boot_page >= mr->start) { 574 /* 575 * Normally u-boot will put in at the end 576 * of memory. But in case it doesn't, deal 577 * with all possibilities. 578 */ 579 if (boot_page + PAGE_SIZE == mr_end) { 580 mr->size -= PAGE_SIZE; 581 } else if (boot_page == mr->start) { 582 mr->start += PAGE_SIZE; 583 mr->size -= PAGE_SIZE; 584 } else { 585 mr->size = boot_page - mr->start; 586 mr++; 587 for (u_int j = cnt; j > i + 1; j--) { 588 availmemr[j] = availmemr[j-1]; 589 } 590 cnt++; 591 mr->start = boot_page + PAGE_SIZE; 592 mr->size = mr_end - mr->start; 593 } 594 break; 595 } 596 } 597 598 /* 599 * Steal pages at the end of memory for the kernel message buffer. 600 */ 601 mr = availmemr + cnt - 1; 602 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 603 mr->size -= round_page(MSGBUFSIZE); 604 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 605 606 /* 607 * Calculate physmem. 608 */ 609 for (u_int i = 0; i < cnt; i++) 610 physmem += atop(physmemr[i].size); 611 612 nmemr = cnt; 613 return physmemr[cnt-1].start + physmemr[cnt-1].size; 614 } 615 616 void 617 consinit(void) 618 { 619 static bool attached = false; 620 621 if (attached) 622 return; 623 attached = true; 624 625 if (comcnfreq == -1) { 626 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 627 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 628 comcnfreq = e500_sys_clk * plat_ratio; 629 printf(" comcnfreq=%u", comcnfreq); 630 } 631 632 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 633 COM_TYPE_NORMAL, comcnmode); 634 } 635 636 void 637 cpu_probe_cache(void) 638 { 639 struct cpu_info * const ci = curcpu(); 640 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 641 642 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 643 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 644 645 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 646 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 647 648 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 649 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 650 } else { 651 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 652 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 653 } 654 655 #ifdef DEBUG 656 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 657 if ((L1CSR_CE & l1csr0) == 0) 658 printf(" DC=off"); 659 660 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 661 if ((L1CSR_CE & l1csr1) == 0) 662 printf(" IC=off"); 663 #endif 664 } 665 666 static uint16_t 667 getsvr(void) 668 { 669 uint16_t svr = mfspr(SPR_SVR) >> 16; 670 671 svr &= ~0x8; /* clear security bit */ 672 switch (svr) { 673 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 674 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 675 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 676 case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16; 677 default: return svr; 678 } 679 } 680 681 static const char * 682 socname(uint32_t svr) 683 { 684 svr &= ~0x80000; /* clear security bit */ 685 switch (svr >> 8) { 686 case SVR_MPC8533 >> 8: return "MPC8533"; 687 case SVR_MPC8536v1 >> 8: return "MPC8536"; 688 case SVR_MPC8541v1 >> 8: return "MPC8541"; 689 case SVR_MPC8543v2 >> 8: return "MPC8543"; 690 case SVR_MPC8544v1 >> 8: return "MPC8544"; 691 case SVR_MPC8545v2 >> 8: return "MPC8545"; 692 case SVR_MPC8547v2 >> 8: return "MPC8547"; 693 case SVR_MPC8548v2 >> 8: return "MPC8548"; 694 case SVR_MPC8555v1 >> 8: return "MPC8555"; 695 case SVR_MPC8568v1 >> 8: return "MPC8568"; 696 case SVR_MPC8567v1 >> 8: return "MPC8567"; 697 case SVR_MPC8572v1 >> 8: return "MPC8572"; 698 case SVR_P2020v2 >> 8: return "P2020"; 699 case SVR_P2010v2 >> 8: return "P2010"; 700 case SVR_P1016v1 >> 8: return "P1016"; 701 case SVR_P1025v1 >> 8: return "P1025"; 702 default: 703 panic("%s: unknown SVR %#x", __func__, svr); 704 } 705 } 706 707 static void 708 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 709 { 710 static const char units[16] = "KKKKKMMMMMGGGGGT"; 711 712 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 713 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 714 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 715 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 716 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 717 718 aprint_normal_dev(self, "%s:", name); 719 720 aprint_normal(" %u", nentries); 721 if (TLBCFG_AVAIL_P(tlbcfg)) { 722 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 723 minsize, maxsize, units[maxsize_log4k]); 724 } else { 725 aprint_normal(" fixed-size (%uKB)", minsize); 726 } 727 if (assoc == 0 || assoc == nentries) 728 aprint_normal(" fully"); 729 else 730 aprint_normal(" %u-way set", assoc); 731 aprint_normal(" associative entries\n"); 732 } 733 734 static void 735 cpu_print_info(struct cpu_info *ci) 736 { 737 uint64_t freq = board_info_get_number("processor-frequency"); 738 device_t self = ci->ci_dev; 739 740 char freqbuf[10]; 741 if (freq >= 999500000) { 742 const uint32_t freq32 = (freq + 500000) / 10000000; 743 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 744 freq32 / 100, freq32 % 100); 745 } else { 746 const uint32_t freq32 = (freq + 500000) / 1000000; 747 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 748 } 749 750 const uint32_t pvr = mfpvr(); 751 const uint32_t svr = mfspr(SPR_SVR); 752 const uint32_t pir = mfspr(SPR_PIR); 753 754 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 755 "ID %u%s\n", 756 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 757 (svr >> 4) & 15, svr & 15, 758 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 759 (pvr >> 4) & 15, pvr & 15, 760 pir, (pir == 0 ? " (Primary)" : "")); 761 762 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 763 aprint_normal_dev(self, 764 "%uKB/%uB %u-way L1 %s cache\n", 765 L1CFG_CSIZE_GET(l1cfg0) >> 10, 766 32 << L1CFG_CBSIZE_GET(l1cfg0), 767 L1CFG_CNWAY_GET(l1cfg0), 768 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 769 ? "data" : "unified"); 770 771 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 772 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 773 aprint_normal_dev(self, 774 "%uKB/%uB %u-way L1 %s cache\n", 775 L1CFG_CSIZE_GET(l1cfg1) >> 10, 776 32 << L1CFG_CBSIZE_GET(l1cfg1), 777 L1CFG_CNWAY_GET(l1cfg1), 778 "instruction"); 779 } 780 781 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 782 aprint_normal_dev(self, 783 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 784 MMUCFG_NTLBS_GET(mmucfg) + 1, 785 MMUCFG_NPIDS_GET(mmucfg), 786 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 787 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 788 789 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 790 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 791 } 792 793 #ifdef MULTIPROCESSOR 794 static void 795 e500_cpu_spinup(device_t self, struct cpu_info *ci) 796 { 797 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 798 struct pglist splist; 799 800 if (spinup_table_addr == 0) { 801 aprint_error_dev(self, "hatch failed (no spin-up table)"); 802 return; 803 } 804 805 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 806 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 807 const size_t id = cpu_index(ci); 808 volatile __cpuset_t * const hatchlings = &cpuset_info.cpus_hatched; 809 810 if (h->hatch_sp == 0) { 811 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 812 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 813 if (error) { 814 aprint_error_dev(self, 815 "unable to allocate hatch stack\n"); 816 return; 817 } 818 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 819 + PAGE_SIZE - CALLFRAMELEN; 820 } 821 822 823 for (size_t i = 1; e[i].entry_pir != 0; i++) { 824 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 825 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 826 if (e[i].entry_pir == ci->ci_cpuid) { 827 828 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 829 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 830 ci->ci_curpm = pmap_kernel(); 831 ci->ci_lasttb = cpu_info[0].ci_lasttb; 832 ci->ci_data.cpu_cc_freq = 833 cpu_info[0].ci_data.cpu_cc_freq; 834 835 h->hatch_self = self; 836 h->hatch_ci = ci; 837 h->hatch_running = -1; 838 h->hatch_pir = e[i].entry_pir; 839 h->hatch_hid0 = mfspr(SPR_HID0); 840 KASSERT(h->hatch_sp != 0); 841 /* 842 * Get new timebase. We don't want to deal with 843 * timebase crossing a 32-bit boundary so make sure 844 * that we have enough headroom to do the timebase 845 * synchronization. 846 */ 847 #define TBSYNC_SLOP 2000 848 uint32_t tbl; 849 uint32_t tbu; 850 do { 851 tbu = mfspr(SPR_RTBU); 852 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 853 } while (tbl < TBSYNC_SLOP); 854 855 h->hatch_tbu = tbu; 856 h->hatch_tbl = tbl; 857 __asm("sync;isync"); 858 dcache_wbinv((vaddr_t)h, sizeof(*h)); 859 860 #if 1 861 /* 862 * And here we go... 863 */ 864 e[i].entry_addr_lower = 865 (uint32_t)e500_spinup_trampoline; 866 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 867 __asm __volatile("sync;isync"); 868 __insn_barrier(); 869 870 for (u_int timo = 0; timo++ < 10000; ) { 871 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 872 if (e[i].entry_addr_lower == 3) { 873 printf( 874 "%s: cpu%u started in %u spins\n", 875 __func__, cpu_index(ci), timo); 876 break; 877 } 878 } 879 for (u_int timo = 0; timo++ < 10000; ) { 880 dcache_inv((vaddr_t)h, sizeof(*h)); 881 if (h->hatch_running == 0) { 882 printf( 883 "%s: cpu%u cracked in %u spins: (running=%d)\n", 884 __func__, cpu_index(ci), 885 timo, h->hatch_running); 886 break; 887 } 888 } 889 if (h->hatch_running == -1) { 890 aprint_error_dev(self, 891 "hatch failed (timeout): running=%d" 892 ", entry=%#x\n", 893 h->hatch_running, e[i].entry_addr_lower); 894 goto out; 895 } 896 #endif 897 898 /* 899 * First then we do is to synchronize timebases. 900 * TBSYNC_SLOP*16 should be more than enough 901 * instructions. 902 */ 903 while (tbl != mftbl()) 904 continue; 905 h->hatch_running = 1; 906 dcache_wbinv((vaddr_t)h, sizeof(*h)); 907 __asm("sync;isync"); 908 __insn_barrier(); 909 910 for (u_int timo = 10000; timo-- > 0; ) { 911 dcache_inv((vaddr_t)h, sizeof(*h)); 912 if (h->hatch_running > 1) 913 break; 914 } 915 if (h->hatch_running == 1) { 916 printf( 917 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 918 __func__, 919 ((int64_t)tbu << 32) + tbl, 920 (int64_t) 921 (((uint64_t)h->hatch_tbu << 32) 922 + (uint64_t)h->hatch_tbl), 923 h->hatch_running); 924 goto out; 925 } 926 printf( 927 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 928 __func__, 929 (int64_t) 930 (((uint64_t)h->hatch_tbu << 32) 931 + (uint64_t)h->hatch_tbl), 932 h->hatch_running); 933 /* 934 * Now we wait for the hatching to complete. 10ms 935 * should be long enough. 936 */ 937 for (u_int timo = 10000; timo-- > 0; ) { 938 if (CPUSET_HAS_P(*hatchlings, id)) { 939 aprint_normal_dev(self, 940 "hatch successful (%u spins, " 941 "timebase adjusted by %"PRId64")\n", 942 10000 - timo, 943 (int64_t) 944 (((uint64_t)h->hatch_tbu << 32) 945 + (uint64_t)h->hatch_tbl)); 946 goto out; 947 } 948 DELAY(1); 949 } 950 951 aprint_error_dev(self, 952 "hatch failed (timeout): running=%u\n", 953 h->hatch_running); 954 goto out; 955 } 956 } 957 958 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 959 ci->ci_cpuid); 960 out: 961 if (h->hatch_sp == 0) 962 uvm_pglistfree(&splist); 963 } 964 #endif 965 966 void 967 e500_cpu_hatch(struct cpu_info *ci) 968 { 969 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 970 971 /* 972 * Make sure interrupts are blocked. 973 */ 974 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 975 976 intr_cpu_hatch(ci); 977 978 cpu_print_info(ci); 979 980 /* 981 */ 982 } 983 984 static void 985 e500_cpu_attach(device_t self, u_int instance) 986 { 987 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 988 989 if (instance > 1) { 990 #if defined(MULTIPROCESSOR) 991 ci->ci_idepth = -1; 992 self->dv_private = ci; 993 994 ci->ci_cpuid = instance - (instance > 0); 995 ci->ci_dev = self; 996 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 997 998 mi_cpu_attach(ci); 999 1000 intr_cpu_attach(ci); 1001 cpu_evcnt_attach(ci); 1002 1003 e500_cpu_spinup(self, ci); 1004 return; 1005 #else 1006 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 1007 return; 1008 #endif 1009 } 1010 1011 self->dv_private = ci; 1012 1013 ci->ci_cpuid = instance - (instance > 0); 1014 ci->ci_dev = self; 1015 1016 intr_cpu_attach(ci); 1017 cpu_evcnt_attach(ci); 1018 1019 KASSERT(ci == curcpu()); 1020 intr_cpu_hatch(ci); 1021 1022 cpu_print_info(ci); 1023 } 1024 1025 void 1026 e500_ipi_halt(void) 1027 { 1028 register_t msr, hid0; 1029 1030 msr = wrtee(0); 1031 1032 hid0 = mfspr(SPR_HID0); 1033 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 1034 mtspr(SPR_HID0, hid0); 1035 1036 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 1037 mtmsr(msr); 1038 for (;;); /* loop forever */ 1039 } 1040 1041 1042 static void 1043 calltozero(void) 1044 { 1045 panic("call to 0 from %p", __builtin_return_address(0)); 1046 } 1047 1048 void 1049 initppc(vaddr_t startkernel, vaddr_t endkernel, 1050 void *a0, void *a1, void *a2, void *a3) 1051 { 1052 struct cpu_info * const ci = curcpu(); 1053 struct cpu_softc * const cpu = ci->ci_softc; 1054 1055 cn_tab = &e500_earlycons; 1056 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 1057 startkernel, endkernel, a0, a1, a2, a3); 1058 1059 /* 1060 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 1061 * DOZE is ok. 1062 */ 1063 const register_t hid0 = mfspr(SPR_HID0); 1064 mtspr(SPR_HID0, 1065 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1066 #ifdef CADMUS 1067 /* 1068 * Need to cache this from cadmus since we need to unmap cadmus since 1069 * it falls in the middle of kernel address space. 1070 */ 1071 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1072 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1073 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1074 printf(" cadmus_pci=%#x", cadmus_pci); 1075 printf(" cadmus_csr=%#x", cadmus_csr); 1076 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1077 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1078 e500_sys_clk *= 2; 1079 } 1080 #endif 1081 #ifdef PIXIS 1082 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1083 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1084 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1085 #ifndef SYS_CLK 1086 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1087 #else 1088 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1089 #endif 1090 #endif 1091 printf(" porpllsr=0x%08x", 1092 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1093 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1094 1095 /* 1096 * Make sure arguments are page aligned. 1097 */ 1098 startkernel = trunc_page(startkernel); 1099 endkernel = round_page(endkernel); 1100 1101 /* 1102 * Initialize the bus space tag used to access the 85xx general 1103 * utility registers. It doesn't need to be extent protected. 1104 * We know the GUR is mapped via a TLB1 entry so we add a limited 1105 * mapiodev which allows mappings in GUR space. 1106 */ 1107 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1108 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1109 bus_space_init(&gur_bst, NULL, NULL, 0); 1110 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1111 cpu->cpu_bst = &gur_bst; 1112 cpu->cpu_le_bst = &gur_le_bst; 1113 cpu->cpu_bsh = gur_bsh; 1114 1115 /* 1116 * Attach the console early, really early. 1117 */ 1118 consinit(); 1119 1120 /* 1121 * Reset the PIC to a known state. 1122 */ 1123 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1124 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1125 ; 1126 #if 0 1127 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1128 #endif 1129 printf(" openpic-reset(ctpr=%u)", 1130 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1131 1132 /* 1133 * fill in with an absolute branch to a routine that will panic. 1134 */ 1135 *(int *)0 = 0x48000002 | (int) calltozero; 1136 1137 /* 1138 * Get the cache sizes. 1139 */ 1140 cpu_probe_cache(); 1141 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1142 ci->ci_ci.dcache_size >> 10, 1143 ci->ci_ci.dcache_line_size, 1144 ci->ci_ci.icache_size >> 10, 1145 ci->ci_ci.icache_line_size); 1146 1147 /* 1148 * Now find out how much memory is attached 1149 */ 1150 pmemsize = memprobe(endkernel); 1151 cpu->cpu_highmem = pmemsize; 1152 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1153 1154 /* 1155 * Now we need cleanout the TLB of stuff that we don't need. 1156 */ 1157 e500_tlb_init(endkernel, pmemsize); 1158 printf(" e500_tlbinit(%#lx,%zuMB)", 1159 endkernel, (size_t) (pmemsize >> 20)); 1160 1161 /* 1162 * 1163 */ 1164 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1165 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1166 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1167 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1168 1169 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1170 1171 /* 1172 * Initialize the message buffer. 1173 */ 1174 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1175 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1176 1177 /* 1178 * Initialize exception vectors and interrupts 1179 */ 1180 exception_init(&e500_intrsw); 1181 1182 printf(" exception_init=%p", &e500_intrsw); 1183 1184 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1185 1186 /* 1187 * Set the page size. 1188 */ 1189 uvm_setpagesize(); 1190 1191 /* 1192 * Initialize the pmap. 1193 */ 1194 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1195 1196 /* 1197 * Let's take all the indirect calls via our stubs and patch 1198 * them to be direct calls. 1199 */ 1200 cpu_fixup_stubs(); 1201 1202 /* 1203 * As a debug measure we can change the TLB entry that maps all of 1204 * memory to one that encompasses the 64KB with the kernel vectors. 1205 * All other pages will be soft faulted into the TLB as needed. 1206 */ 1207 e500_tlb_minimize(endkernel); 1208 1209 /* 1210 * Set some more MD helpers 1211 */ 1212 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1213 cpu_md_ops.md_device_register = e500_device_register; 1214 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1215 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1216 #if NGPIO > 0 1217 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1218 #endif 1219 1220 printf(" initppc done!\n"); 1221 1222 /* 1223 * Look for the Book-E modules in the right place. 1224 */ 1225 module_machine = module_machine_booke; 1226 } 1227 1228 #ifdef MPC8548 1229 static const char * const mpc8548cds_extirq_names[] = { 1230 [0] = "pci inta", 1231 [1] = "pci intb", 1232 [2] = "pci intc", 1233 [3] = "pci intd", 1234 [4] = "irq4", 1235 [5] = "gige phy", 1236 [6] = "atm phy", 1237 [7] = "cpld", 1238 [8] = "irq8", 1239 [9] = "nvram", 1240 [10] = "debug", 1241 [11] = "pci2 inta", 1242 }; 1243 #endif 1244 1245 static const char * const mpc85xx_extirq_names[] = { 1246 [0] = "extirq 0", 1247 [1] = "extirq 1", 1248 [2] = "extirq 2", 1249 [3] = "extirq 3", 1250 [4] = "extirq 4", 1251 [5] = "extirq 5", 1252 [6] = "extirq 6", 1253 [7] = "extirq 7", 1254 [8] = "extirq 8", 1255 [9] = "extirq 9", 1256 [10] = "extirq 10", 1257 [11] = "extirq 11", 1258 }; 1259 1260 static void 1261 mpc85xx_extirq_setup(void) 1262 { 1263 #ifdef MPC8548 1264 const char * const * names = mpc8548cds_extirq_names; 1265 const size_t n = __arraycount(mpc8548cds_extirq_names); 1266 #else 1267 const char * const * names = mpc85xx_extirq_names; 1268 const size_t n = __arraycount(mpc85xx_extirq_names); 1269 #endif 1270 prop_array_t extirqs = prop_array_create_with_capacity(n); 1271 for (u_int i = 0; i < n; i++) { 1272 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1273 prop_array_set(extirqs, i, ps); 1274 prop_object_release(ps); 1275 } 1276 board_info_add_object("external-irqs", extirqs); 1277 prop_object_release(extirqs); 1278 } 1279 1280 static void 1281 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1282 { 1283 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1284 KASSERT(pci_intmap != NULL); 1285 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1286 KASSERT(mask != NULL); 1287 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1288 prop_object_release(mask); 1289 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1290 KASSERT(pn_ist != NULL); 1291 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1292 KASSERT(pn_intr != NULL); 1293 prop_dictionary_t entry = prop_dictionary_create(); 1294 KASSERT(entry != NULL); 1295 prop_dictionary_set(entry, "interrupt", pn_intr); 1296 prop_dictionary_set(entry, "type", pn_ist); 1297 prop_dictionary_set(pci_intmap, "000000", entry); 1298 prop_object_release(pn_intr); 1299 prop_object_release(entry); 1300 va_list ap; 1301 va_start(ap, inta); 1302 u_int intrinc = __LOWEST_SET_BIT(intmask); 1303 for (u_int i = 0; i < intmask; i += intrinc) { 1304 char prop_name[12]; 1305 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1306 entry = prop_dictionary_create(); 1307 KASSERT(entry != NULL); 1308 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1309 KASSERT(pn_intr != NULL); 1310 prop_dictionary_set(entry, "interrupt", pn_intr); 1311 prop_dictionary_set(entry, "type", pn_ist); 1312 prop_dictionary_set(pci_intmap, prop_name, entry); 1313 prop_object_release(pn_intr); 1314 prop_object_release(entry); 1315 } 1316 va_end(ap); 1317 prop_object_release(pn_ist); 1318 board_info_add_object(name, pci_intmap); 1319 prop_object_release(pci_intmap); 1320 } 1321 1322 void 1323 cpu_startup(void) 1324 { 1325 struct cpu_info * const ci = curcpu(); 1326 const uint16_t svr = getsvr(); 1327 1328 powersave = 0; /* we can do it but turn it on by default */ 1329 1330 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1331 1332 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1333 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1334 uint32_t e500_ratio = E500_RATIO_GET(v); 1335 1336 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1337 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1338 1339 ci->ci_khz = (cpu_freq + 500) / 1000; 1340 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1341 1342 board_info_add_number("my-id", svr); 1343 board_info_add_bool("pq3"); 1344 board_info_add_number("mem-size", pmemsize); 1345 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1346 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1347 uint32_t l2banks = l2siz >> 16; 1348 #ifdef MPC85555 1349 if (svr == (MPC8555v1 >> 16)) { 1350 l2siz >>= 1; 1351 l2banks >>= 1; 1352 } 1353 #endif 1354 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1355 if (boot_page & BPTR_EN) { 1356 bool found = false; 1357 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1358 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1359 * const bp = (void *)boot_page; 1360 bp <= dp; dp--) { 1361 if (*dp == boot_page) { 1362 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1363 spinup_table_addr = 1364 roundup2(spinup_table_addr, 32); 1365 board_info_add_number("mp-boot-page", 1366 boot_page); 1367 board_info_add_number("mp-spin-up-table", 1368 spinup_table_addr); 1369 printf("Found MP boot page @ %#"PRIxPADDR". " 1370 "Spin-up table @ %#"PRIxPTR"\n", 1371 boot_page, spinup_table_addr); 1372 found = true; 1373 break; 1374 } 1375 } 1376 if (!found) { 1377 printf("Found MP boot page @ %#"PRIxPADDR 1378 " with missing U-boot signature!\n", boot_page); 1379 board_info_add_number("mp-spin-up-table", 0); 1380 } 1381 } 1382 board_info_add_number("l2-cache-size", l2siz); 1383 board_info_add_number("l2-cache-line-size", 32); 1384 board_info_add_number("l2-cache-banks", l2banks); 1385 board_info_add_number("l2-cache-ways", 8); 1386 1387 board_info_add_number("processor-frequency", cpu_freq); 1388 board_info_add_number("bus-frequency", ccb_freq); 1389 board_info_add_number("pci-frequency", e500_sys_clk); 1390 board_info_add_number("timebase-frequency", ccb_freq / 8); 1391 1392 #ifdef CADMUS 1393 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1394 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1395 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1396 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1397 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1398 #else 1399 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1400 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1401 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1402 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1403 #endif 1404 1405 uint64_t macstnaddr = 1406 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1407 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1408 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1409 1410 #if NPCI > 0 && defined(PCI_MEMBASE) 1411 pcimem_ex = extent_create("pcimem", 1412 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1413 NULL, 0, EX_WAITOK); 1414 #endif 1415 #if NPCI > 0 && defined(PCI_IOBASE) 1416 pciio_ex = extent_create("pciio", 1417 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1418 NULL, 0, EX_WAITOK); 1419 #endif 1420 mpc85xx_extirq_setup(); 1421 /* 1422 * PCI-Express virtual wire interrupts on combined with 1423 * External IRQ0/1/2/3. 1424 */ 1425 switch (svr) { 1426 #if defined(MPC8548) 1427 case SVR_MPC8548v1 >> 16: 1428 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1429 IST_LEVEL, 0, 1, 2, 3); 1430 break; 1431 #endif 1432 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \ 1433 || defined(P1025) || defined(P2020) 1434 case SVR_MPC8536v1 >> 16: 1435 case SVR_MPC8544v1 >> 16: 1436 case SVR_MPC8572v1 >> 16: 1437 case SVR_P1016v1 >> 16: 1438 case SVR_P2010v2 >> 16: 1439 case SVR_P2020v2 >> 16: 1440 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1441 8, 9, 10, 11); 1442 /* FALLTHROUGH */ 1443 case SVR_P1025v1 >> 16: 1444 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1445 4, 5, 6, 7); 1446 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1447 0, 1, 2, 3); 1448 break; 1449 #endif 1450 } 1451 switch (svr) { 1452 #if defined(MPC8536) 1453 case SVR_MPC8536v1 >> 16: 1454 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1455 1, 2, 3, 4); 1456 break; 1457 #endif 1458 #if defined(MPC8544) 1459 case SVR_MPC8544v1 >> 16: 1460 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1461 0, 1, 2, 3); 1462 break; 1463 #endif 1464 #if defined(MPC8548) 1465 case SVR_MPC8548v1 >> 16: 1466 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1467 0, 1, 2, 3); 1468 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1469 11, 1, 2, 3); 1470 break; 1471 #endif 1472 } 1473 } 1474
Indexes created Tue Sep 30 07:10:03 GMT 2025