machdep.c revision 1.3
1 /* $NetBSD: machdep.c,v 1.3 2011/02/08 06:22:29 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 64 #include <uvm/uvm_extern.h> 65 66 #include <prop/proplib.h> 67 68 #include <machine/stdarg.h> 69 70 #include <dev/cons.h> 71 72 #include <dev/ic/comreg.h> 73 #include <dev/ic/comvar.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 #include <dev/mii/miivar.h> 78 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 void initppc(vaddr_t, vaddr_t); 96 97 #define MEMREGIONS 4 98 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 99 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 100 static u_int nmemr; 101 102 #ifndef CONSFREQ 103 # define CONSFREQ -1 /* inherit from firmware */ 104 #endif 105 #ifndef CONSPEED 106 # define CONSPEED 115200 107 #endif 108 #ifndef CONMODE 109 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 110 #endif 111 #ifndef CONSADDR 112 # define CONSADDR DUART2_BASE 113 #endif 114 115 int comcnfreq = CONSFREQ; 116 int comcnspeed = CONSPEED; 117 tcflag_t comcnmode = CONMODE; 118 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 119 120 #if NPCI > 0 121 struct extent *pcimem_ex; 122 struct extent *pciio_ex; 123 #endif 124 125 struct powerpc_bus_space gur_bst = { 126 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 127 .pbs_offset = GUR_BASE, 128 .pbs_limit = GUR_SIZE, 129 }; 130 131 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 132 133 #ifdef CADMUS 134 static uint8_t cadmus_pci; 135 static uint8_t cadmus_csr; 136 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 137 #elif defined(PIXIS) 138 static const uint32_t pixis_spd_map[8] = { 139 [PX_SPD_33MHZ] = 33333333, 140 [PX_SPD_40MHZ] = 40000000, 141 [PX_SPD_50MHZ] = 50000000, 142 [PX_SPD_66MHZ] = 66666666, 143 [PX_SPD_83MHZ] = 83333333, 144 [PX_SPD_133MHZ] = 100000000, 145 [PX_SPD_133MHZ] = 133333333, 146 [PX_SPD_166MHZ] = 166666667, 147 }; 148 static uint8_t pixis_spd; 149 static uint64_t e500_sys_clk; 150 #elif defined(SYS_CLK) 151 static uint64_t e500_sys_clk = SYS_CLK; 152 #else 153 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 154 #endif 155 156 static int e500_cngetc(dev_t); 157 static void e500_cnputc(dev_t, int); 158 159 static struct consdev e500_earlycons = { 160 .cn_getc = e500_cngetc, 161 .cn_putc = e500_cnputc, 162 .cn_pollc = nullcnpollc, 163 }; 164 165 /* 166 * List of port-specific devices to attach to the processor local bus. 167 */ 168 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 169 { "cpu" }, /* not a real device */ 170 { "wdog" }, /* not a real device */ 171 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 172 1, { ISOURCE_DUART }, 173 1 + ilog2(DEVDISR_DUART) }, 174 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 175 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 176 1 + ilog2(DEVDISR_TSEC1) }, 177 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 178 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 179 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 180 1 + ilog2(DEVDISR_TSEC2), 181 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 182 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 183 #endif 184 #if defined(MPC8544) || defined(MPC8536) 185 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 186 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 187 1 + ilog2(DEVDISR_TSEC3), 188 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 189 #endif 190 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 191 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 192 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 193 1 + ilog2(DEVDISR_TSEC3), 194 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 195 SVR_P2020v2 >> 16 } }, 196 #endif 197 #if defined(MPC8548) || defined(MPC8572) 198 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 199 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 200 1 + ilog2(DEVDISR_TSEC4), 201 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 202 #endif 203 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 204 1, { ISOURCE_I2C }, 205 1 + ilog2(DEVDISR_I2C) }, 206 /* MPC8572 doesn't have any GPIO */ 207 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 208 1, { ISOURCE_GPIO }, 209 0, 210 { 0xffff, SVR_MPC8572v1 >> 16 } }, 211 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 212 1, { ISOURCE_DDR }, 213 1 + ilog2(DEVDISR_DDR_15), 214 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 215 #if defined(MPC8536) 216 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 217 1, { ISOURCE_DDR }, 218 1 + ilog2(DEVDISR_DDR_16), 219 { SVR_MPC8536v1 >> 16 } }, 220 #endif 221 #if defined(MPC8572) 222 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 223 1, { ISOURCE_DDR }, 224 1 + ilog2(DEVDISR_DDR_15), 225 { SVR_MPC8572v1 >> 16 } }, 226 { "ddrc", DDRC1_BASE, DDRC_SIZE, 2, 227 1, { ISOURCE_DDR }, 228 1 + ilog2(DEVDISR_DDR2_14), 229 { SVR_MPC8572v1 >> 16 } }, 230 #endif 231 #if defined(MPC8544) || defined(MPC8536) 232 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 233 1, { ISOURCE_PCIEX }, 234 1 + ilog2(DEVDISR_PCIE), 235 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 236 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 237 1, { ISOURCE_PCIEX2 }, 238 1 + ilog2(DEVDISR_PCIE2), 239 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 240 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 241 1, { ISOURCE_PCIEX3 }, 242 1 + ilog2(DEVDISR_PCIE3), 243 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 244 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 245 1, { ISOURCE_PCI1 }, 246 1 + ilog2(DEVDISR_PCI1), 247 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 248 #endif 249 #ifdef MPC8548 250 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 251 1, { ISOURCE_PCIEX }, 252 1 + ilog2(DEVDISR_PCIE), 253 { SVR_MPC8538v1 >> 16 }, }, 254 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 255 1, { ISOURCE_PCI1 }, 256 1 + ilog2(DEVDISR_PCI1), 257 { SVR_MPC8538v1 >> 16 }, }, 258 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 259 1, { ISOURCE_PCI2 }, 260 1 + ilog2(DEVDISR_PCI2), 261 { SVR_MPC8538v1 >> 16 }, }, 262 #endif 263 #if defined(MPC8572) || defined(P2020) 264 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 265 1, { ISOURCE_PCIEX }, 266 1 + ilog2(DEVDISR_PCIE), 267 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 268 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 269 1, { ISOURCE_PCIEX2 }, 270 1 + ilog2(DEVDISR_PCIE2), 271 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 272 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 273 1, { ISOURCE_PCIEX3_MPC8572 }, 274 1 + ilog2(DEVDISR_PCIE3), 275 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 276 #endif 277 #if defined(MPC8536) || defined(P2020) 278 { "ehci", USB1_BASE, USB_SIZE, 1, 279 1, { ISOURCE_USB1 }, 280 1 + ilog2(DEVDISR_USB1), 281 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 282 #endif 283 #ifdef MPC8536 284 { "ehci", USB2_BASE, USB_SIZE, 2, 285 1, { ISOURCE_USB2 }, 286 1 + ilog2(DEVDISR_USB2), 287 { SVR_MPC8536v1 >> 16 }, }, 288 { "ehci", USB3_BASE, USB_SIZE, 3, 289 1, { ISOURCE_USB3 }, 290 1 + ilog2(DEVDISR_USB3), 291 { SVR_MPC8536v1 >> 16 }, }, 292 { "sata", SATA1_BASE, SATA_SIZE, 1, 293 1, { ISOURCE_SATA1 }, 294 1 + ilog2(DEVDISR_SATA1), 295 { SVR_MPC8536v1 >> 16 }, }, 296 { "sata", SATA2_BASE, SATA_SIZE, 2, 297 1, { ISOURCE_SATA2 }, 298 1 + ilog2(DEVDISR_SATA2), 299 { SVR_MPC8536v1 >> 16 }, }, 300 { "spi", SPI_BASE, SPI_SIZE, 0, 301 1, { ISOURCE_SPI }, 302 1 + ilog2(DEVDISR_SPI_15), 303 { SVR_MPC8536v1 >> 16 }, }, 304 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 305 1, { ISOURCE_ESDHC }, 306 1 + ilog2(DEVDISR_ESDHC_12), 307 { SVR_MPC8536v1 >> 16 }, }, 308 #endif 309 #if defined(P2020) 310 { "spi", SPI_BASE, SPI_SIZE, 0, 311 1, { ISOURCE_SPI }, 312 1 + ilog2(DEVDISR_SPI_28), 313 { SVR_P2020v2 >> 16 }, }, 314 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 315 1, { ISOURCE_ESDHC }, 316 1 + ilog2(DEVDISR_ESDHC_10), 317 { SVR_P2020v2 >> 16 }, }, 318 #endif 319 { "lbc", LBC_BASE, LBC_SIZE, 0, 320 1, { ISOURCE_LBC }, 321 1 + ilog2(DEVDISR_LBC) }, 322 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 323 { NULL } 324 }; 325 326 static int 327 e500_cngetc(dev_t dv) 328 { 329 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 330 331 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 332 return -1; 333 334 return com0addr[com_data] & 0xff; 335 } 336 337 static void 338 e500_cnputc(dev_t dv, int c) 339 { 340 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 341 int timo = 150000; 342 343 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 344 ; 345 346 com0addr[com_data] = c; 347 __asm("mbar"); 348 349 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 350 ; 351 } 352 353 static void * 354 gur_tlb_mapiodev(paddr_t pa, psize_t len) 355 { 356 if (pa < gur_bst.pbs_offset) 357 return NULL; 358 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 359 return NULL; 360 return (void *)pa; 361 } 362 363 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 364 365 static void 366 e500_cpu_reset(void) 367 { 368 __asm volatile("sync"); 369 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 370 __asm volatile("msync;isync"); 371 } 372 373 static psize_t 374 memprobe(vaddr_t endkernel) 375 { 376 phys_ram_seg_t *mr; 377 378 /* 379 * First we need to find out how much physical memory we have. 380 * We could let our bootloader tell us, but it's almost as easy 381 * to ask the DDR memory controller. 382 */ 383 mr = physmemr; 384 #if 1 385 for (u_int i = 0; i < 4; i++) { 386 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 387 if (v & CS_CONFIG_EN) { 388 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 389 mr->start = BNDS_SA_GET(v); 390 mr->size = BNDS_SIZE_GET(v); 391 mr++; 392 } 393 } 394 395 if (mr == physmemr) 396 panic("no memory configured!"); 397 #else 398 mr->start = 0; 399 mr->size = 32 << 20; 400 mr++; 401 #endif 402 403 /* 404 * Sort memory regions from low to high and coalesce adjacent regions 405 */ 406 u_int cnt = mr - physmemr; 407 if (cnt > 1) { 408 for (u_int i = 0; i < cnt - 1; i++) { 409 for (u_int j = i + 1; j < cnt; j++) { 410 if (physmemr[j].start < physmemr[i].start) { 411 phys_ram_seg_t tmp = physmemr[i]; 412 physmemr[i] = physmemr[j]; 413 physmemr[j] = tmp; 414 } 415 } 416 } 417 mr = physmemr; 418 for (u_int i = 0; i < cnt; i++, mr++) { 419 if (mr->start + mr->size == mr[1].start) { 420 mr->size += mr[1].size; 421 for (u_int j = 1; j < cnt - i; j++) 422 mr[j] = mr[j+1]; 423 cnt--; 424 } 425 } 426 } 427 428 /* 429 * Copy physical memory to available memory. 430 */ 431 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 432 433 /* 434 * Adjust available memory to skip kernel at start of memory. 435 */ 436 availmemr[0].size -= endkernel - availmemr[0].start; 437 availmemr[0].start = endkernel; 438 439 /* 440 * Steal pages at the end of memory for the kernel message buffer. 441 */ 442 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 443 msgbuf_paddr = 444 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 445 446 /* 447 * Calculate physmem. 448 */ 449 for (u_int i = 0; i < cnt; i++) 450 physmem += atop(physmemr[i].size); 451 452 nmemr = cnt; 453 return physmemr[cnt-1].start + physmemr[cnt-1].size; 454 } 455 456 void 457 consinit(void) 458 { 459 static bool attached = false; 460 461 if (attached) 462 return; 463 attached = true; 464 465 if (comcnfreq == -1) { 466 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 467 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 468 comcnfreq = e500_sys_clk * plat_ratio; 469 printf(" comcnfreq=%u", comcnfreq); 470 } 471 472 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 473 COM_TYPE_NORMAL, comcnmode); 474 } 475 476 void 477 cpu_probe_cache(void) 478 { 479 struct cpu_info * const ci = curcpu(); 480 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 481 482 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 483 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 484 485 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 486 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 487 488 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 489 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 490 } else { 491 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 492 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 493 } 494 495 #ifdef DEBUG 496 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 497 if ((L1CSR_CE & l1csr0) == 0) 498 printf(" DC=off"); 499 500 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 501 if ((L1CSR_CE & l1csr1) == 0) 502 printf(" IC=off"); 503 #endif 504 } 505 506 static uint16_t 507 getsvr(void) 508 { 509 uint16_t svr = mfspr(SPR_SVR) >> 16; 510 511 svr &= ~0x8; /* clear security bit */ 512 switch (svr) { 513 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 514 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 515 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 516 default: return svr; 517 } 518 } 519 520 static const char * 521 socname(uint32_t svr) 522 { 523 svr &= ~0x80000; /* clear security bit */ 524 switch (svr >> 8) { 525 case SVR_MPC8536v1 >> 8: return "MPC8536"; 526 case SVR_MPC8541v1 >> 8: return "MPC8541"; 527 case SVR_MPC8543v2 >> 8: return "MPC8543"; 528 case SVR_MPC8544v1 >> 8: return "MPC8544"; 529 case SVR_MPC8545v2 >> 8: return "MPC8545"; 530 case SVR_MPC8547v2 >> 8: return "MPC8547"; 531 case SVR_MPC8548v2 >> 8: return "MPC8548"; 532 case SVR_MPC8555v1 >> 8: return "MPC8555"; 533 case SVR_MPC8568v1 >> 8: return "MPC8568"; 534 case SVR_MPC8567v1 >> 8: return "MPC8567"; 535 case SVR_MPC8572v1 >> 8: return "MPC8572"; 536 case SVR_P2020v2 >> 8: return "P2020"; 537 case SVR_P2010v2 >> 8: return "P2010"; 538 default: 539 panic("%s: unknown SVR %#x", __func__, svr); 540 } 541 } 542 543 static void 544 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 545 { 546 static const char units[16] = "KKKKKMMMMMGGGGGT"; 547 548 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 549 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 550 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 551 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 552 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 553 554 aprint_normal_dev(self, "%s:", name); 555 556 aprint_normal(" %u", nentries); 557 if (TLBCFG_AVAIL_P(tlbcfg)) { 558 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 559 minsize, maxsize, units[maxsize_log4k]); 560 } else { 561 aprint_normal(" fixed-size (%uKB)", minsize); 562 } 563 if (assoc == 0 || assoc == nentries) 564 aprint_normal(" fully"); 565 else 566 aprint_normal(" %u-way set", assoc); 567 aprint_normal(" associative entries\n"); 568 } 569 570 static void 571 e500_cpu_attach(device_t self, u_int instance) 572 { 573 struct cpu_info * const ci = &cpu_info[instance]; 574 575 KASSERT(instance == 0); 576 self->dv_private = ci; 577 578 ci->ci_cpuid = instance; 579 ci->ci_dev = self; 580 //ci->ci_idlespin = cpu_idlespin; 581 if (instance > 0) { 582 ci->ci_idepth = -1; 583 cpu_probe_cache(); 584 } 585 586 uint64_t freq = board_info_get_number("processor-frequency"); 587 char freqbuf[10]; 588 if (freq >= 999500000) { 589 const uint32_t freq32 = (freq + 500000) / 10000000; 590 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 591 freq32 / 100, freq32 % 100); 592 } else { 593 const uint32_t freq32 = (freq + 500000) / 1000000; 594 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 595 } 596 597 const uint32_t pvr = mfpvr(); 598 const uint32_t svr = mfspr(SPR_SVR); 599 const uint32_t pir = mfspr(SPR_PIR); 600 601 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 602 "ID %u%s\n", 603 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 604 (svr >> 4) & 15, svr & 15, 605 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 606 (pvr >> 4) & 15, pvr & 15, 607 pir, (pir == 0 ? " (Primary)" : "")); 608 609 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 610 aprint_normal_dev(self, 611 "%uKB/%uB %u-way L1 %s cache\n", 612 L1CFG_CSIZE_GET(l1cfg0) >> 10, 613 32 << L1CFG_CBSIZE_GET(l1cfg0), 614 L1CFG_CNWAY_GET(l1cfg0), 615 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 616 ? "data" : "unified"); 617 618 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 619 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 620 aprint_normal_dev(self, 621 "%uKB/%uB %u-way L1 %s cache\n", 622 L1CFG_CSIZE_GET(l1cfg1) >> 10, 623 32 << L1CFG_CBSIZE_GET(l1cfg1), 624 L1CFG_CNWAY_GET(l1cfg1), 625 "instruction"); 626 } 627 628 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 629 aprint_normal_dev(self, 630 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 631 MMUCFG_NTLBS_GET(mmucfg) + 1, 632 MMUCFG_NPIDS_GET(mmucfg), 633 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 634 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 635 636 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 637 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 638 639 intr_cpu_init(ci); 640 cpu_evcnt_attach(ci); 641 } 642 643 static void 644 calltozero(void) 645 { 646 panic("call to 0 from %p", __builtin_return_address(0)); 647 } 648 649 void 650 initppc(vaddr_t startkernel, vaddr_t endkernel) 651 { 652 struct cpu_info * const ci = curcpu(); 653 struct cpu_softc * const cpu = ci->ci_softc; 654 655 cn_tab = &e500_earlycons; 656 printf(" initppc<enter>"); 657 658 const register_t hid0 = mfspr(SPR_HID0); 659 mtspr(SPR_HID0, hid0 | HID0_TBEN | HID0_EMCP); 660 #ifdef CADMUS 661 /* 662 * Need to cache this from cadmus since we need to unmap cadmus since 663 * it falls in the middle of kernel address space. 664 */ 665 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 666 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 667 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 668 printf(" cadmus_pci=%#x", cadmus_pci); 669 printf(" cadmus_csr=%#x", cadmus_csr); 670 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 671 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 672 e500_sys_clk *= 2; 673 } 674 #endif 675 #ifdef PIXIS 676 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 677 printf(" pixis_spd=%#x ", pixis_spd); 678 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 679 #endif 680 printf(" porpllsr=0x%08x", 681 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 682 printf(" sys_clk=%"PRIu64, e500_sys_clk); 683 684 /* 685 * Make sure arguments are page aligned. 686 */ 687 startkernel = trunc_page(startkernel); 688 endkernel = round_page(endkernel); 689 690 /* 691 * Initialize the bus space tag used to access the 85xx general 692 * utility registers. It doesn't need to be extent protected. 693 * We know the GUR is mapped via a TLB1 entry so we add a limited 694 * mapiodev which allows mappings in GUR space. 695 */ 696 CTASSERT(offsetof(struct tlb_md_ops, md_tlb_mapiodev) == 0); 697 cpu_md_ops.md_tlb_ops = (const void *)&early_tlb_mapiodev; 698 bus_space_init(&gur_bst, NULL, NULL, 0); 699 cpu->cpu_bst = &gur_bst; 700 cpu->cpu_bsh = gur_bsh; 701 702 /* 703 * Attach the console early, really early. 704 */ 705 consinit(); 706 707 /* 708 * Reset the PIC to a known state. 709 */ 710 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 711 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 712 ; 713 #if 0 714 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 715 #endif 716 printf(" openpic-reset(ctpr=%u)", 717 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 718 719 /* 720 * fill in with an absolute branch to a routine that will panic. 721 */ 722 *(int *)0 = 0x48000002 | (int) calltozero; 723 724 /* 725 * Get the cache sizes. 726 */ 727 cpu_probe_cache(); 728 printf(" cache(DC=%u/%u,IC=%u/%u)", 729 ci->ci_ci.dcache_size >> 10, 730 ci->ci_ci.dcache_line_size, 731 ci->ci_ci.icache_size >> 10, 732 ci->ci_ci.icache_line_size); 733 734 /* 735 * Now find out how much memory is attached 736 */ 737 pmemsize = memprobe(endkernel); 738 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 739 740 /* 741 * Now we need cleanout the TLB of stuff that we don't need. 742 */ 743 e500_tlb_init(endkernel, pmemsize); 744 printf(" e500_tlbinit(%#lx,%zuMB)", 745 endkernel, (size_t) (pmemsize >> 20)); 746 747 /* 748 * 749 */ 750 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 751 printf(" hid1=%#lx", mfspr(SPR_HID1)); 752 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 753 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 754 755 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 756 757 /* 758 * Initialize the message buffer. 759 */ 760 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 761 printf(" msgbuf=%p", (void *)msgbuf_paddr); 762 763 /* 764 * Initialize exception vectors and interrupts 765 */ 766 exception_init(&e500_intrsw); 767 printf(" exception_init=%p", &e500_intrsw); 768 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 769 770 /* 771 * Set the page size. 772 */ 773 uvm_setpagesize(); 774 775 /* 776 * Initialize the pmap. 777 */ 778 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 779 780 /* 781 * Let's take all the indirect calls via our stubs and patch 782 * them to be direct calls. 783 */ 784 booke_fixup_stubs(); 785 #if 0 786 /* 787 * As a debug measure we can change the TLB entry that maps all of 788 * memory to one that encompasses the 64KB with the kernel vectors. 789 * All other pages will be soft faulted into the TLB as needed. 790 */ 791 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 792 mtspr(SPR_MAS6, 0); 793 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 794 uint32_t mas0 = mfspr(SPR_MAS0); 795 uint32_t mas1 = mfspr(SPR_MAS1); 796 uint32_t mas2 = mfspr(SPR_MAS2); 797 uint32_t mas3 = mfspr(SPR_MAS3); 798 KASSERT(mas3 & MAS3_SW); 799 KASSERT(mas3 & MAS3_SR); 800 KASSERT(mas3 & MAS3_SX); 801 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 802 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 803 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 804 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 805 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 806 #if 1 807 mtspr(SPR_MAS1, mas1); 808 mtspr(SPR_MAS2, mas2); 809 mtspr(SPR_MAS3, mas3); 810 extern void tlbwe(void); 811 tlbwe(); 812 mtspr(SPR_MAS0, saved_mas0); 813 printf("(ok)"); 814 #endif 815 #endif 816 817 /* 818 * Set some more MD helpers 819 */ 820 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 821 cpu_md_ops.md_device_register = e500_device_register; 822 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 823 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 824 #if NGPIO > 0 825 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 826 #endif 827 828 printf(" initppc done!\n"); 829 } 830 831 #ifdef MPC8548 832 static const char * const mpc8548cds_extirq_names[] = { 833 [0] = "pci inta", 834 [1] = "pci intb", 835 [2] = "pci intc", 836 [3] = "pci intd", 837 [4] = "irq4", 838 [5] = "gige phy", 839 [6] = "atm phy", 840 [7] = "cpld", 841 [8] = "irq8", 842 [9] = "nvram", 843 [10] = "debug", 844 [11] = "pci2 inta", 845 }; 846 #endif 847 848 static const char * const mpc85xx_extirq_names[] = { 849 [0] = "extirq 0", 850 [1] = "extirq 1", 851 [2] = "extirq 2", 852 [3] = "extirq 3", 853 [4] = "extirq 4", 854 [5] = "extirq 5", 855 [6] = "extirq 6", 856 [7] = "extirq 7", 857 [8] = "extirq 8", 858 [9] = "extirq 9", 859 [10] = "extirq 10", 860 [11] = "extirq 11", 861 }; 862 863 static void 864 mpc85xx_extirq_setup(void) 865 { 866 #ifdef MPC8548 867 const char * const * names = mpc8548cds_extirq_names; 868 const size_t n = __arraycount(mpc8548cds_extirq_names); 869 #else 870 const char * const * names = mpc85xx_extirq_names; 871 const size_t n = __arraycount(mpc85xx_extirq_names); 872 #endif 873 prop_array_t extirqs = prop_array_create_with_capacity(n); 874 for (u_int i = 0; i < n; i++) { 875 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 876 prop_array_set(extirqs, i, ps); 877 prop_object_release(ps); 878 } 879 board_info_add_object("external-irqs", extirqs); 880 prop_object_release(extirqs); 881 } 882 883 static void 884 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 885 { 886 prop_dictionary_t pci_intmap = prop_dictionary_create(); 887 KASSERT(pci_intmap != NULL); 888 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 889 KASSERT(mask != NULL); 890 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 891 prop_object_release(mask); 892 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 893 KASSERT(pn_ist != NULL); 894 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 895 KASSERT(pn_intr != NULL); 896 prop_dictionary_t entry = prop_dictionary_create(); 897 KASSERT(entry != NULL); 898 prop_dictionary_set(entry, "interrupt", pn_intr); 899 prop_dictionary_set(entry, "type", pn_ist); 900 prop_dictionary_set(pci_intmap, "000000", entry); 901 prop_object_release(pn_intr); 902 prop_object_release(entry); 903 va_list ap; 904 va_start(ap, inta); 905 u_int intrinc = __LOWEST_SET_BIT(intmask); 906 for (u_int i = 0; i < intmask; i += intrinc) { 907 char prop_name[12]; 908 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 909 entry = prop_dictionary_create(); 910 KASSERT(entry != NULL); 911 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 912 KASSERT(pn_intr != NULL); 913 prop_dictionary_set(entry, "interrupt", pn_intr); 914 prop_dictionary_set(entry, "type", pn_ist); 915 prop_dictionary_set(pci_intmap, prop_name, entry); 916 prop_object_release(pn_intr); 917 prop_object_release(entry); 918 } 919 va_end(ap); 920 prop_object_release(pn_ist); 921 board_info_add_object(name, pci_intmap); 922 prop_object_release(pci_intmap); 923 } 924 925 void 926 cpu_startup(void) 927 { 928 struct cpu_info * const ci = curcpu(); 929 const uint16_t svr = getsvr(); 930 931 booke_cpu_startup(socname(mfspr(SPR_SVR))); 932 933 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 934 uint32_t plat_ratio = PLAT_RATIO_GET(v); 935 uint32_t e500_ratio = E500_RATIO_GET(v); 936 937 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 938 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 939 940 ci->ci_khz = (cpu_freq + 500) / 1000; 941 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 942 943 board_info_add_number("my-id", svr); 944 board_info_add_bool("pq3"); 945 board_info_add_number("mem-size", pmemsize); 946 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 947 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 948 uint32_t l2banks = l2siz >> 16; 949 #ifdef MPC85555 950 if (svr == (MPC8555v1 >> 16)) { 951 l2siz >>= 1; 952 l2banks >>= 1; 953 } 954 #endif 955 board_info_add_number("l2-cache-size", l2siz); 956 board_info_add_number("l2-cache-line-size", 32); 957 board_info_add_number("l2-cache-banks", l2banks); 958 board_info_add_number("l2-cache-ways", 8); 959 960 board_info_add_number("processor-frequency", cpu_freq); 961 board_info_add_number("bus-frequency", ccb_freq); 962 board_info_add_number("pci-frequency", e500_sys_clk); 963 board_info_add_number("timebase-frequency", ccb_freq / 8); 964 965 #ifdef CADMUS 966 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 967 board_info_add_number("tsec1-phy-addr", phy_base + 0); 968 board_info_add_number("tsec2-phy-addr", phy_base + 1); 969 board_info_add_number("tsec3-phy-addr", phy_base + 2); 970 board_info_add_number("tsec4-phy-addr", phy_base + 3); 971 #else 972 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 973 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 974 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 975 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 976 #endif 977 978 uint64_t macstnaddr = 979 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 980 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 981 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 982 983 #if NPCI > 0 && defined(PCI_MEMBASE) 984 pcimem_ex = extent_create("pcimem", 985 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 986 M_DEVBUF, NULL, 0, EX_WAITOK); 987 #endif 988 #if NPCI > 0 && defined(PCI_IOBASE) 989 pciio_ex = extent_create("pciio", 990 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 991 M_DEVBUF, NULL, 0, EX_WAITOK); 992 #endif 993 mpc85xx_extirq_setup(); 994 /* 995 * PCI-Express virtual wire interrupts on combined with 996 * External IRQ0/1/2/3. 997 */ 998 switch (svr) { 999 #if defined(MPC8548) 1000 case SVR_MPC8548v1 >> 16: 1001 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1002 IST_LEVEL, 0, 1, 2, 3); 1003 break; 1004 #endif 1005 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1006 case SVR_MPC8536v1 >> 16: 1007 case SVR_MPC8544v1 >> 16: 1008 case SVR_MPC8572v1 >> 16: 1009 case SVR_P2010v2 >> 16: 1010 case SVR_P2020v2 >> 16: 1011 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1012 0, 1, 2, 3); 1013 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1014 4, 5, 6, 7); 1015 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1016 8, 9, 10, 11); 1017 break; 1018 #endif 1019 } 1020 switch (svr) { 1021 #if defined(MPC8536) 1022 case SVR_MPC8536v1 >> 16: 1023 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1024 1, 2, 3, 4); 1025 break; 1026 #endif 1027 #if defined(MPC8544) 1028 case SVR_MPC8544v1 >> 16: 1029 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1030 0, 1, 2, 3); 1031 break; 1032 #endif 1033 #if defined(MPC8548) 1034 case SVR_MPC8548v1 >> 16: 1035 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1036 0, 1, 2, 3); 1037 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1038 11, 1, 2, 3); 1039 break; 1040 #endif 1041 } 1042 } 1043
Indexes created Mon Sep 29 18:09:42 GMT 2025