machdep.c revision 1.36
1 /* $NetBSD: machdep.c,v 1.36 2014/12/19 04:31:41 nonaka Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_altivec.h" 42 #include "opt_ddb.h" 43 #include "opt_mpc85xx.h" 44 #include "opt_pci.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/reboot.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <dev/cons.h> 70 71 #include <dev/ic/comreg.h> 72 #include <dev/ic/comvar.h> 73 74 #include <net/if.h> 75 #include <net/if_media.h> 76 #include <dev/mii/miivar.h> 77 78 #include <powerpc/pcb.h> 79 #include <powerpc/spr.h> 80 #include <powerpc/booke/spr.h> 81 82 #include <powerpc/booke/cpuvar.h> 83 #include <powerpc/booke/e500reg.h> 84 #include <powerpc/booke/e500var.h> 85 #include <powerpc/booke/etsecreg.h> 86 #include <powerpc/booke/openpicreg.h> 87 #ifdef CADMUS 88 #include <evbppc/mpc85xx/cadmusreg.h> 89 #endif 90 #ifdef PIXIS 91 #include <evbppc/mpc85xx/pixisreg.h> 92 #endif 93 94 struct uboot_bdinfo { 95 uint32_t bd_memstart; 96 uint32_t bd_memsize; 97 uint32_t bd_flashstart; 98 uint32_t bd_flashsize; 99 /*10*/ uint32_t bd_flashoffset; 100 uint32_t bd_sramstart; 101 uint32_t bd_sramsize; 102 uint32_t bd_immrbase; 103 /*20*/ uint32_t bd_bootflags; 104 uint32_t bd_ipaddr; 105 uint8_t bd_etheraddr[6]; 106 uint16_t bd_ethspeed; 107 /*30*/ uint32_t bd_intfreq; 108 uint32_t bd_cpufreq; 109 uint32_t bd_baudrate; 110 /*3c*/ uint8_t bd_etheraddr1[6]; 111 /*42*/ uint8_t bd_etheraddr2[6]; 112 /*48*/ uint8_t bd_etheraddr3[6]; 113 /*4e*/ uint16_t bd_pad; 114 }; 115 116 char root_string[16]; 117 118 /* 119 * booke kernels need to set module_machine to this for modules to work. 120 */ 121 char module_machine_booke[] = "powerpc-booke"; 122 123 void initppc(vaddr_t, vaddr_t, void *, void *, char *, char *); 124 125 #define MEMREGIONS 4 126 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 127 phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 128 static u_int nmemr; 129 130 #ifndef CONSFREQ 131 # define CONSFREQ -1 /* inherit from firmware */ 132 #endif 133 #ifndef CONSPEED 134 # define CONSPEED 115200 135 #endif 136 #ifndef CONMODE 137 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 138 #endif 139 #ifndef CONSADDR 140 # define CONSADDR DUART2_BASE 141 #endif 142 143 int comcnfreq = CONSFREQ; 144 int comcnspeed = CONSPEED; 145 tcflag_t comcnmode = CONMODE; 146 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 147 148 #if NPCI > 0 149 struct extent *pcimem_ex; 150 struct extent *pciio_ex; 151 #endif 152 153 struct powerpc_bus_space gur_bst = { 154 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 155 .pbs_offset = GUR_BASE, 156 .pbs_limit = GUR_SIZE, 157 }; 158 159 struct powerpc_bus_space gur_le_bst = { 160 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 161 .pbs_offset = GUR_BASE, 162 .pbs_limit = GUR_SIZE, 163 }; 164 165 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 166 167 #if defined(SYS_CLK) 168 static uint64_t e500_sys_clk = SYS_CLK; 169 #endif 170 #ifdef CADMUS 171 static uint8_t cadmus_pci; 172 static uint8_t cadmus_csr; 173 #ifndef SYS_CLK 174 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 175 #endif 176 #elif defined(PIXIS) 177 static const uint32_t pixis_spd_map[8] = { 178 [PX_SPD_33MHZ] = 33333333, 179 [PX_SPD_40MHZ] = 40000000, 180 [PX_SPD_50MHZ] = 50000000, 181 [PX_SPD_66MHZ] = 66666666, 182 [PX_SPD_83MHZ] = 83333333, 183 [PX_SPD_100MHZ] = 100000000, 184 [PX_SPD_133MHZ] = 133333333, 185 [PX_SPD_166MHZ] = 166666667, 186 }; 187 static uint8_t pixis_spd; 188 #ifndef SYS_CLK 189 static uint64_t e500_sys_clk; 190 #endif 191 #elif !defined(SYS_CLK) 192 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 193 #endif 194 195 static int e500_cngetc(dev_t); 196 static void e500_cnputc(dev_t, int); 197 198 static struct consdev e500_earlycons = { 199 .cn_getc = e500_cngetc, 200 .cn_putc = e500_cnputc, 201 .cn_pollc = nullcnpollc, 202 }; 203 204 /* 205 * List of port-specific devices to attach to the processor local bus. 206 */ 207 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 208 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 209 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 210 SVR_P1025v1 >> 16 } }, 211 #if defined(MPC8572) || defined(P2020) || defined(P1025) 212 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 213 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 214 SVR_P1025v1 >> 16 } }, 215 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 216 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 217 SVR_P1025v1 >> 16 } }, 218 #endif 219 { "wdog" }, /* not a real device */ 220 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 221 1, { ISOURCE_DUART }, 222 1 + ilog2(DEVDISR_DUART) }, 223 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 224 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 225 1 + ilog2(DEVDISR_TSEC1), 226 { 0xffff, SVR_P1025v1 >> 16 } }, 227 #if defined(P1025) 228 { "mdio", ETSEC1_BASE, ETSEC_SIZE, 1, 229 0, { }, 230 1 + ilog2(DEVDISR_TSEC1), 231 { SVR_P1025v1 >> 16 } }, 232 { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1, 233 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 234 1 + ilog2(DEVDISR_TSEC1), 235 { SVR_P1025v1 >> 16 } }, 236 #if 0 237 { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1, 238 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX, 239 ISOURCE_ETSEC1_G1_ERR }, 240 1 + ilog2(DEVDISR_TSEC1), 241 { SVR_P1025v1 >> 16 } }, 242 #endif 243 #endif 244 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \ 245 || defined(P2020) 246 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 247 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 248 1 + ilog2(DEVDISR_TSEC2), 249 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 250 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 251 SVR_P1025v1 >> 16 } }, 252 #endif 253 #if defined(P1025) 254 { "mdio", ETSEC2_BASE, ETSEC_SIZE, 2, 255 0, { }, 256 1 + ilog2(DEVDISR_TSEC2), 257 { SVR_P1025v1 >> 16 } }, 258 { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2, 259 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 260 1 + ilog2(DEVDISR_TSEC2), 261 { SVR_P1025v1 >> 16 } }, 262 #if 0 263 { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5, 264 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX, 265 ISOURCE_ETSEC2_G1_ERR }, 266 1 + ilog2(DEVDISR_TSEC2), 267 { SVR_P1025v1 >> 16 } }, 268 #endif 269 #endif 270 #if defined(MPC8544) || defined(MPC8536) 271 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 272 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 273 1 + ilog2(DEVDISR_TSEC3), 274 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 275 #endif 276 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 277 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 278 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 279 1 + ilog2(DEVDISR_TSEC3), 280 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 281 SVR_P2020v2 >> 16 } }, 282 #endif 283 #if defined(P1025) 284 { "mdio", ETSEC3_BASE, ETSEC_SIZE, 3, 285 0, { }, 286 1 + ilog2(DEVDISR_TSEC3), 287 { SVR_P1025v1 >> 16 } }, 288 { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3, 289 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 290 1 + ilog2(DEVDISR_TSEC3), 291 { SVR_P1025v1 >> 16 } }, 292 #if 0 293 { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3, 294 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX, 295 ISOURCE_ETSEC3_G1_ERR }, 296 1 + ilog2(DEVDISR_TSEC3), 297 { SVR_P1025v1 >> 16 } }, 298 #endif 299 #endif 300 #if defined(MPC8548) || defined(MPC8572) 301 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 302 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 303 1 + ilog2(DEVDISR_TSEC4), 304 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 305 #endif 306 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 307 1, { ISOURCE_I2C }, 308 1 + ilog2(DEVDISR_I2C) }, 309 /* MPC8572 doesn't have any GPIO */ 310 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 311 1, { ISOURCE_GPIO }, 312 0, 313 { 0xffff, SVR_MPC8572v1 >> 16 } }, 314 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 315 1, { ISOURCE_DDR }, 316 1 + ilog2(DEVDISR_DDR_15), 317 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 318 #if defined(MPC8536) 319 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 320 1, { ISOURCE_DDR }, 321 1 + ilog2(DEVDISR_DDR_16), 322 { SVR_MPC8536v1 >> 16 } }, 323 #endif 324 #if defined(MPC8572) 325 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 326 1, { ISOURCE_DDR }, 327 1 + ilog2(DEVDISR_DDR_15), 328 { SVR_MPC8572v1 >> 16 } }, 329 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 330 1, { ISOURCE_DDR }, 331 1 + ilog2(DEVDISR_DDR2_14), 332 { SVR_MPC8572v1 >> 16 } }, 333 #endif 334 { "lbc", LBC_BASE, LBC_SIZE, 0, 335 1, { ISOURCE_LBC }, 336 1 + ilog2(DEVDISR_LBC) }, 337 #if defined(MPC8544) || defined(MPC8536) 338 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 339 1, { ISOURCE_PCIEX }, 340 1 + ilog2(DEVDISR_PCIE), 341 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 342 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 343 1, { ISOURCE_PCIEX2 }, 344 1 + ilog2(DEVDISR_PCIE2), 345 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 346 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 347 1, { ISOURCE_PCIEX3 }, 348 1 + ilog2(DEVDISR_PCIE3), 349 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 350 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 351 1, { ISOURCE_PCI1 }, 352 1 + ilog2(DEVDISR_PCI1), 353 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 354 #endif 355 #ifdef MPC8548 356 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 357 1, { ISOURCE_PCIEX }, 358 1 + ilog2(DEVDISR_PCIE), 359 { SVR_MPC8548v1 >> 16 }, }, 360 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 361 1, { ISOURCE_PCI1 }, 362 1 + ilog2(DEVDISR_PCI1), 363 { SVR_MPC8548v1 >> 16 }, }, 364 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 365 1, { ISOURCE_PCI2 }, 366 1 + ilog2(DEVDISR_PCI2), 367 { SVR_MPC8548v1 >> 16 }, }, 368 #endif 369 #if defined(MPC8572) || defined(P1025) || defined(P2020) 370 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 371 1, { ISOURCE_PCIEX }, 372 1 + ilog2(DEVDISR_PCIE), 373 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 374 SVR_P1025v1 >> 16 } }, 375 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 376 1, { ISOURCE_PCIEX2 }, 377 1 + ilog2(DEVDISR_PCIE2), 378 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 379 SVR_P1025v1 >> 16 } }, 380 #endif 381 #if defined(MPC8572) || defined(P2020) 382 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 383 1, { ISOURCE_PCIEX3_MPC8572 }, 384 1 + ilog2(DEVDISR_PCIE3), 385 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, } }, 386 #endif 387 #if defined(MPC8536) || defined(P1025) || defined(P2020) 388 { "ehci", USB1_BASE, USB_SIZE, 1, 389 1, { ISOURCE_USB1 }, 390 1 + ilog2(DEVDISR_USB1), 391 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16, 392 SVR_P1025v1 >> 16 } }, 393 #endif 394 #ifdef MPC8536 395 { "ehci", USB2_BASE, USB_SIZE, 2, 396 1, { ISOURCE_USB2 }, 397 1 + ilog2(DEVDISR_USB2), 398 { SVR_MPC8536v1 >> 16 }, }, 399 { "ehci", USB3_BASE, USB_SIZE, 3, 400 1, { ISOURCE_USB3 }, 401 1 + ilog2(DEVDISR_USB3), 402 { SVR_MPC8536v1 >> 16 }, }, 403 { "sata", SATA1_BASE, SATA_SIZE, 1, 404 1, { ISOURCE_SATA1 }, 405 1 + ilog2(DEVDISR_SATA1), 406 { SVR_MPC8536v1 >> 16 }, }, 407 { "sata", SATA2_BASE, SATA_SIZE, 2, 408 1, { ISOURCE_SATA2 }, 409 1 + ilog2(DEVDISR_SATA2), 410 { SVR_MPC8536v1 >> 16 }, }, 411 { "spi", SPI_BASE, SPI_SIZE, 0, 412 1, { ISOURCE_SPI }, 413 1 + ilog2(DEVDISR_SPI_15), 414 { SVR_MPC8536v1 >> 16 }, }, 415 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 416 1, { ISOURCE_ESDHC }, 417 1 + ilog2(DEVDISR_ESDHC_12), 418 { SVR_MPC8536v1 >> 16 }, }, 419 #endif 420 #if defined(P1025) || defined(P2020) 421 { "spi", SPI_BASE, SPI_SIZE, 0, 422 1, { ISOURCE_SPI }, 423 1 + ilog2(DEVDISR_SPI_28), 424 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 425 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 426 1, { ISOURCE_ESDHC }, 427 1 + ilog2(DEVDISR_ESDHC_10), 428 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 429 #endif 430 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 431 { NULL } 432 }; 433 434 static int 435 e500_cngetc(dev_t dv) 436 { 437 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 438 439 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 440 return -1; 441 442 return com0addr[com_data] & 0xff; 443 } 444 445 static void 446 e500_cnputc(dev_t dv, int c) 447 { 448 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 449 int timo = 150000; 450 451 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 452 ; 453 454 com0addr[com_data] = c; 455 __asm("mbar"); 456 457 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 458 ; 459 } 460 461 static void * 462 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 463 { 464 if (prefetchable) 465 return NULL; 466 if (pa < gur_bst.pbs_offset) 467 return NULL; 468 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 469 return NULL; 470 return (void *)pa; 471 } 472 473 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 474 475 static void 476 e500_cpu_reset(void) 477 { 478 __asm volatile("sync"); 479 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 480 __asm volatile("msync;isync"); 481 } 482 483 static psize_t 484 memprobe(vaddr_t endkernel) 485 { 486 phys_ram_seg_t *mr; 487 paddr_t boot_page = cpu_read_4(GUR_BPTR); 488 printf(" bptr=%"PRIxPADDR, boot_page); 489 if (boot_page & BPTR_EN) { 490 /* 491 * shift it to an address 492 */ 493 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 494 } else { 495 boot_page = ~(paddr_t)0; 496 } 497 498 /* 499 * First we need to find out how much physical memory we have. 500 * We could let our bootloader tell us, but it's almost as easy 501 * to ask the DDR memory controller. 502 */ 503 mr = physmemr; 504 for (u_int i = 0; i < 4; i++) { 505 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 506 if (v & CS_CONFIG_EN) { 507 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 508 if (v == 0) 509 continue; 510 mr->start = BNDS_SA_GET(v); 511 mr->size = BNDS_SIZE_GET(v); 512 #ifdef MEMSIZE 513 if (mr->start >= MEMSIZE) 514 continue; 515 if (mr->start + mr->size > MEMSIZE) 516 mr->size = MEMSIZE - mr->start; 517 #endif 518 #if 0 519 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 520 mr - physmemr, mr->size, mr->start); 521 #endif 522 mr++; 523 } 524 } 525 526 if (mr == physmemr) 527 panic("no memory configured!"); 528 529 /* 530 * Sort memory regions from low to high and coalesce adjacent regions 531 */ 532 u_int cnt = mr - physmemr; 533 if (cnt > 1) { 534 for (u_int i = 0; i < cnt - 1; i++) { 535 for (u_int j = i + 1; j < cnt; j++) { 536 if (physmemr[j].start < physmemr[i].start) { 537 phys_ram_seg_t tmp = physmemr[i]; 538 physmemr[i] = physmemr[j]; 539 physmemr[j] = tmp; 540 } 541 } 542 } 543 mr = physmemr; 544 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 545 if (mr->start + mr->size == mr[1].start) { 546 mr->size += mr[1].size; 547 for (u_int j = 1; i + j + 1 < cnt; j++) 548 mr[j] = mr[j+1]; 549 cnt--; 550 } 551 } 552 } else if (cnt == 0) { 553 panic("%s: no memory found", __func__); 554 } 555 556 /* 557 * Copy physical memory to available memory. 558 */ 559 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 560 561 /* 562 * Adjust available memory to skip kernel at start of memory. 563 */ 564 availmemr[0].size -= endkernel - availmemr[0].start; 565 availmemr[0].start = endkernel; 566 567 mr = availmemr; 568 for (u_int i = 0; i < cnt; i++, mr++) { 569 /* 570 * U-boot reserves a boot-page on multi-core chips. 571 * We need to make sure that we never disturb it. 572 */ 573 const paddr_t mr_end = mr->start + mr->size; 574 if (mr_end > boot_page && boot_page >= mr->start) { 575 /* 576 * Normally u-boot will put in at the end 577 * of memory. But in case it doesn't, deal 578 * with all possibilities. 579 */ 580 if (boot_page + PAGE_SIZE == mr_end) { 581 mr->size -= PAGE_SIZE; 582 } else if (boot_page == mr->start) { 583 mr->start += PAGE_SIZE; 584 mr->size -= PAGE_SIZE; 585 } else { 586 mr->size = boot_page - mr->start; 587 mr++; 588 for (u_int j = cnt; j > i + 1; j--) { 589 availmemr[j] = availmemr[j-1]; 590 } 591 cnt++; 592 mr->start = boot_page + PAGE_SIZE; 593 mr->size = mr_end - mr->start; 594 } 595 break; 596 } 597 } 598 599 /* 600 * Steal pages at the end of memory for the kernel message buffer. 601 */ 602 mr = availmemr + cnt - 1; 603 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 604 mr->size -= round_page(MSGBUFSIZE); 605 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 606 607 /* 608 * Calculate physmem. 609 */ 610 for (u_int i = 0; i < cnt; i++) 611 physmem += atop(physmemr[i].size); 612 613 nmemr = cnt; 614 return physmemr[cnt-1].start + physmemr[cnt-1].size; 615 } 616 617 void 618 consinit(void) 619 { 620 static bool attached = false; 621 622 if (attached) 623 return; 624 attached = true; 625 626 if (comcnfreq == -1) { 627 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 628 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 629 comcnfreq = e500_sys_clk * plat_ratio; 630 printf(" comcnfreq=%u", comcnfreq); 631 } 632 633 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 634 COM_TYPE_NORMAL, comcnmode); 635 } 636 637 void 638 cpu_probe_cache(void) 639 { 640 struct cpu_info * const ci = curcpu(); 641 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 642 const int dcache_assoc = L1CFG_CNWAY_GET(l1cfg0); 643 644 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 645 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 646 647 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 648 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 649 650 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 651 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 652 } else { 653 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 654 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 655 } 656 657 /* 658 * Possibly recolor. 659 */ 660 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / dcache_assoc)); 661 662 #ifdef DEBUG 663 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 664 if ((L1CSR_CE & l1csr0) == 0) 665 printf(" DC=off"); 666 667 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 668 if ((L1CSR_CE & l1csr1) == 0) 669 printf(" IC=off"); 670 #endif 671 } 672 673 static uint16_t 674 getsvr(void) 675 { 676 uint16_t svr = mfspr(SPR_SVR) >> 16; 677 678 svr &= ~0x8; /* clear security bit */ 679 switch (svr) { 680 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 681 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 682 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 683 case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16; 684 default: return svr; 685 } 686 } 687 688 static const char * 689 socname(uint32_t svr) 690 { 691 svr &= ~0x80000; /* clear security bit */ 692 switch (svr >> 8) { 693 case SVR_MPC8533 >> 8: return "MPC8533"; 694 case SVR_MPC8536v1 >> 8: return "MPC8536"; 695 case SVR_MPC8541v1 >> 8: return "MPC8541"; 696 case SVR_MPC8543v2 >> 8: return "MPC8543"; 697 case SVR_MPC8544v1 >> 8: return "MPC8544"; 698 case SVR_MPC8545v2 >> 8: return "MPC8545"; 699 case SVR_MPC8547v2 >> 8: return "MPC8547"; 700 case SVR_MPC8548v2 >> 8: return "MPC8548"; 701 case SVR_MPC8555v1 >> 8: return "MPC8555"; 702 case SVR_MPC8568v1 >> 8: return "MPC8568"; 703 case SVR_MPC8567v1 >> 8: return "MPC8567"; 704 case SVR_MPC8572v1 >> 8: return "MPC8572"; 705 case SVR_P2020v2 >> 8: return "P2020"; 706 case SVR_P2010v2 >> 8: return "P2010"; 707 case SVR_P1016v1 >> 8: return "P1016"; 708 case SVR_P1025v1 >> 8: return "P1025"; 709 default: 710 panic("%s: unknown SVR %#x", __func__, svr); 711 } 712 } 713 714 static void 715 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 716 { 717 static const char units[16] = "KKKKKMMMMMGGGGGT"; 718 719 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 720 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 721 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 722 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 723 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 724 725 aprint_normal_dev(self, "%s:", name); 726 727 aprint_normal(" %u", nentries); 728 if (TLBCFG_AVAIL_P(tlbcfg)) { 729 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 730 minsize, maxsize, units[maxsize_log4k]); 731 } else { 732 aprint_normal(" fixed-size (%uKB)", minsize); 733 } 734 if (assoc == 0 || assoc == nentries) 735 aprint_normal(" fully"); 736 else 737 aprint_normal(" %u-way set", assoc); 738 aprint_normal(" associative entries\n"); 739 } 740 741 static void 742 cpu_print_info(struct cpu_info *ci) 743 { 744 uint64_t freq = board_info_get_number("processor-frequency"); 745 device_t self = ci->ci_dev; 746 747 char freqbuf[10]; 748 if (freq >= 999500000) { 749 const uint32_t freq32 = (freq + 500000) / 10000000; 750 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 751 freq32 / 100, freq32 % 100); 752 } else { 753 const uint32_t freq32 = (freq + 500000) / 1000000; 754 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 755 } 756 757 const uint32_t pvr = mfpvr(); 758 const uint32_t svr = mfspr(SPR_SVR); 759 const uint32_t pir = mfspr(SPR_PIR); 760 761 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 762 "ID %u%s\n", 763 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 764 (svr >> 4) & 15, svr & 15, 765 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 766 (pvr >> 4) & 15, pvr & 15, 767 pir, (pir == 0 ? " (Primary)" : "")); 768 769 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 770 aprint_normal_dev(self, 771 "%uKB/%uB %u-way L1 %s cache\n", 772 L1CFG_CSIZE_GET(l1cfg0) >> 10, 773 32 << L1CFG_CBSIZE_GET(l1cfg0), 774 L1CFG_CNWAY_GET(l1cfg0), 775 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 776 ? "data" : "unified"); 777 778 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 779 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 780 aprint_normal_dev(self, 781 "%uKB/%uB %u-way L1 %s cache\n", 782 L1CFG_CSIZE_GET(l1cfg1) >> 10, 783 32 << L1CFG_CBSIZE_GET(l1cfg1), 784 L1CFG_CNWAY_GET(l1cfg1), 785 "instruction"); 786 } 787 788 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 789 aprint_normal_dev(self, 790 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 791 MMUCFG_NTLBS_GET(mmucfg) + 1, 792 MMUCFG_NPIDS_GET(mmucfg), 793 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 794 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 795 796 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 797 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 798 } 799 800 #ifdef MULTIPROCESSOR 801 static void 802 e500_cpu_spinup(device_t self, struct cpu_info *ci) 803 { 804 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 805 struct pglist splist; 806 807 if (spinup_table_addr == 0) { 808 aprint_error_dev(self, "hatch failed (no spin-up table)"); 809 return; 810 } 811 812 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 813 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 814 const size_t id = cpu_index(ci); 815 kcpuset_t * const hatchlings = cpuset_info.cpus_hatched; 816 817 if (h->hatch_sp == 0) { 818 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 819 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 820 if (error) { 821 aprint_error_dev(self, 822 "unable to allocate hatch stack\n"); 823 return; 824 } 825 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 826 + PAGE_SIZE - CALLFRAMELEN; 827 } 828 829 830 for (size_t i = 1; e[i].entry_pir != 0; i++) { 831 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 832 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 833 if (e[i].entry_pir == ci->ci_cpuid) { 834 835 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 836 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 837 ci->ci_curpm = pmap_kernel(); 838 ci->ci_lasttb = cpu_info[0].ci_lasttb; 839 ci->ci_data.cpu_cc_freq = 840 cpu_info[0].ci_data.cpu_cc_freq; 841 842 h->hatch_self = self; 843 h->hatch_ci = ci; 844 h->hatch_running = -1; 845 h->hatch_pir = e[i].entry_pir; 846 h->hatch_hid0 = mfspr(SPR_HID0); 847 u_int tlbidx; 848 e500_tlb_lookup_xtlb(0, &tlbidx); 849 h->hatch_tlbidx = tlbidx; 850 KASSERT(h->hatch_sp != 0); 851 /* 852 * Get new timebase. We don't want to deal with 853 * timebase crossing a 32-bit boundary so make sure 854 * that we have enough headroom to do the timebase 855 * synchronization. 856 */ 857 #define TBSYNC_SLOP 2000 858 uint32_t tbl; 859 uint32_t tbu; 860 do { 861 tbu = mfspr(SPR_RTBU); 862 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 863 } while (tbl < TBSYNC_SLOP); 864 865 h->hatch_tbu = tbu; 866 h->hatch_tbl = tbl; 867 __asm("sync;isync"); 868 dcache_wbinv((vaddr_t)h, sizeof(*h)); 869 870 /* 871 * And here we go... 872 */ 873 e[i].entry_addr_lower = 874 (uint32_t)e500_spinup_trampoline; 875 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 876 __asm __volatile("sync;isync"); 877 __insn_barrier(); 878 879 for (u_int timo = 0; timo++ < 10000; ) { 880 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 881 if (e[i].entry_addr_lower == 3) { 882 #if 0 883 printf( 884 "%s: cpu%u started in %u spins\n", 885 __func__, cpu_index(ci), timo); 886 #endif 887 break; 888 } 889 } 890 for (u_int timo = 0; timo++ < 10000; ) { 891 dcache_inv((vaddr_t)h, sizeof(*h)); 892 if (h->hatch_running == 0) { 893 #if 0 894 printf( 895 "%s: cpu%u cracked in %u spins: (running=%d)\n", 896 __func__, cpu_index(ci), 897 timo, h->hatch_running); 898 #endif 899 break; 900 } 901 } 902 if (h->hatch_running == -1) { 903 aprint_error_dev(self, 904 "hatch failed (timeout): running=%d" 905 ", entry=%#x\n", 906 h->hatch_running, e[i].entry_addr_lower); 907 goto out; 908 } 909 910 /* 911 * First then we do is to synchronize timebases. 912 * TBSYNC_SLOP*16 should be more than enough 913 * instructions. 914 */ 915 while (tbl != mftbl()) 916 continue; 917 h->hatch_running = 1; 918 dcache_wbinv((vaddr_t)h, sizeof(*h)); 919 __asm("sync;isync"); 920 __insn_barrier(); 921 printf("%s: cpu%u set to running\n", 922 __func__, cpu_index(ci)); 923 924 for (u_int timo = 10000; timo-- > 0; ) { 925 dcache_inv((vaddr_t)h, sizeof(*h)); 926 if (h->hatch_running > 1) 927 break; 928 } 929 if (h->hatch_running == 1) { 930 printf( 931 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 932 __func__, 933 ((int64_t)tbu << 32) + tbl, 934 (int64_t) 935 (((uint64_t)h->hatch_tbu << 32) 936 + (uint64_t)h->hatch_tbl), 937 h->hatch_running); 938 goto out; 939 } 940 printf( 941 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 942 __func__, 943 (int64_t) 944 (((uint64_t)h->hatch_tbu << 32) 945 + (uint64_t)h->hatch_tbl), 946 h->hatch_running); 947 /* 948 * Now we wait for the hatching to complete. 30ms 949 * should be long enough. 950 */ 951 for (u_int timo = 30000; timo-- > 0; ) { 952 if (kcpuset_isset(hatchlings, id)) { 953 aprint_normal_dev(self, 954 "hatch successful (%u spins, " 955 "timebase adjusted by %"PRId64")\n", 956 30000 - timo, 957 (int64_t) 958 (((uint64_t)h->hatch_tbu << 32) 959 + (uint64_t)h->hatch_tbl)); 960 goto out; 961 } 962 DELAY(1); 963 } 964 965 aprint_error_dev(self, 966 "hatch failed (timeout): running=%u\n", 967 h->hatch_running); 968 goto out; 969 } 970 } 971 972 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 973 ci->ci_cpuid); 974 out: 975 if (h->hatch_sp == 0) 976 uvm_pglistfree(&splist); 977 } 978 #endif 979 980 void 981 e500_cpu_hatch(struct cpu_info *ci) 982 { 983 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 984 985 /* 986 * Make sure interrupts are blocked. 987 */ 988 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 989 990 intr_cpu_hatch(ci); 991 992 cpu_probe_cache(); 993 cpu_print_info(ci); 994 995 /* 996 */ 997 } 998 999 static void 1000 e500_cpu_attach(device_t self, u_int instance) 1001 { 1002 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 1003 1004 if (instance > 1) { 1005 #if defined(MULTIPROCESSOR) 1006 ci->ci_idepth = -1; 1007 self->dv_private = ci; 1008 1009 ci->ci_cpuid = instance - (instance > 0); 1010 ci->ci_dev = self; 1011 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 1012 1013 mi_cpu_attach(ci); 1014 1015 intr_cpu_attach(ci); 1016 cpu_evcnt_attach(ci); 1017 1018 e500_cpu_spinup(self, ci); 1019 return; 1020 #else 1021 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 1022 return; 1023 #endif 1024 } 1025 1026 self->dv_private = ci; 1027 1028 ci->ci_cpuid = instance - (instance > 0); 1029 ci->ci_dev = self; 1030 1031 intr_cpu_attach(ci); 1032 cpu_evcnt_attach(ci); 1033 1034 KASSERT(ci == curcpu()); 1035 intr_cpu_hatch(ci); 1036 1037 cpu_print_info(ci); 1038 } 1039 1040 void 1041 e500_ipi_halt(void) 1042 { 1043 register_t msr, hid0; 1044 1045 msr = wrtee(0); 1046 1047 hid0 = mfspr(SPR_HID0); 1048 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 1049 mtspr(SPR_HID0, hid0); 1050 1051 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 1052 mtmsr(msr); 1053 for (;;); /* loop forever */ 1054 } 1055 1056 1057 static void 1058 calltozero(void) 1059 { 1060 panic("call to 0 from %p", __builtin_return_address(0)); 1061 } 1062 1063 static void 1064 parse_cmdline(char *cp) 1065 { 1066 int ourhowto = 0; 1067 char c; 1068 bool opt = false; 1069 for (; (c = *cp) != '\0'; cp++) { 1070 if (c == '-') { 1071 opt = true; 1072 continue; 1073 } 1074 if (c == ' ') { 1075 opt = false; 1076 continue; 1077 } 1078 if (opt) { 1079 switch (c) { 1080 case 'a': ourhowto |= RB_ASKNAME; break; 1081 case 'd': ourhowto |= AB_DEBUG; break; 1082 case 'q': ourhowto |= AB_QUIET; break; 1083 case 's': ourhowto |= RB_SINGLE; break; 1084 case 'v': ourhowto |= AB_VERBOSE; break; 1085 } 1086 continue; 1087 } 1088 strlcpy(root_string, cp, sizeof(root_string)); 1089 break; 1090 } 1091 if (ourhowto) { 1092 boothowto |= ourhowto; 1093 printf(" boothowto=%#x(%#x)", boothowto, ourhowto); 1094 } 1095 if (root_string[0]) 1096 printf(" root=%s", root_string); 1097 } 1098 1099 void 1100 initppc(vaddr_t startkernel, vaddr_t endkernel, 1101 void *a0, void *a1, char *a2, char *a3) 1102 { 1103 struct cpu_info * const ci = curcpu(); 1104 struct cpu_softc * const cpu = ci->ci_softc; 1105 1106 cn_tab = &e500_earlycons; 1107 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 1108 startkernel, endkernel, a0, a1, a2, a3); 1109 1110 if (a2[0] != '\0') 1111 printf(" consdev=<%s>", a2); 1112 if (a3[0] != '\0') { 1113 printf(" cmdline=<%s>", a3); 1114 parse_cmdline(a3); 1115 } 1116 1117 /* 1118 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 1119 * DOZE is ok. 1120 */ 1121 const register_t hid0 = mfspr(SPR_HID0); 1122 mtspr(SPR_HID0, 1123 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1124 #ifdef CADMUS 1125 /* 1126 * Need to cache this from cadmus since we need to unmap cadmus since 1127 * it falls in the middle of kernel address space. 1128 */ 1129 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1130 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1131 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1132 printf(" cadmus_pci=%#x", cadmus_pci); 1133 printf(" cadmus_csr=%#x", cadmus_csr); 1134 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1135 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1136 e500_sys_clk *= 2; 1137 } 1138 #endif 1139 #ifdef PIXIS 1140 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1141 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1142 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1143 #ifndef SYS_CLK 1144 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1145 #else 1146 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1147 #endif 1148 #endif 1149 printf(" porpllsr=0x%08x", 1150 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1151 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1152 1153 /* 1154 * Make sure arguments are page aligned. 1155 */ 1156 startkernel = trunc_page(startkernel); 1157 endkernel = round_page(endkernel); 1158 1159 /* 1160 * Initialize the bus space tag used to access the 85xx general 1161 * utility registers. It doesn't need to be extent protected. 1162 * We know the GUR is mapped via a TLB1 entry so we add a limited 1163 * mapiodev which allows mappings in GUR space. 1164 */ 1165 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1166 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1167 bus_space_init(&gur_bst, NULL, NULL, 0); 1168 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1169 cpu->cpu_bst = &gur_bst; 1170 cpu->cpu_le_bst = &gur_le_bst; 1171 cpu->cpu_bsh = gur_bsh; 1172 1173 /* 1174 * Attach the console early, really early. 1175 */ 1176 consinit(); 1177 1178 /* 1179 * Reset the PIC to a known state. 1180 */ 1181 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1182 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1183 ; 1184 #if 0 1185 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1186 #endif 1187 printf(" openpic-reset(ctpr=%u)", 1188 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1189 1190 /* 1191 * fill in with an absolute branch to a routine that will panic. 1192 */ 1193 *(volatile int *)0 = 0x48000002 | (int) calltozero; 1194 1195 /* 1196 * Get the cache sizes. 1197 */ 1198 cpu_probe_cache(); 1199 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1200 ci->ci_ci.dcache_size >> 10, 1201 ci->ci_ci.dcache_line_size, 1202 ci->ci_ci.icache_size >> 10, 1203 ci->ci_ci.icache_line_size); 1204 1205 /* 1206 * Now find out how much memory is attached 1207 */ 1208 pmemsize = memprobe(endkernel); 1209 cpu->cpu_highmem = pmemsize; 1210 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1211 1212 /* 1213 * Now we need cleanout the TLB of stuff that we don't need. 1214 */ 1215 e500_tlb_init(endkernel, pmemsize); 1216 printf(" e500_tlbinit(%#lx,%zuMB)", 1217 endkernel, (size_t) (pmemsize >> 20)); 1218 1219 /* 1220 * 1221 */ 1222 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1223 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1224 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1225 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1226 1227 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1228 1229 /* 1230 * Initialize the message buffer. 1231 */ 1232 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1233 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1234 1235 /* 1236 * Initialize exception vectors and interrupts 1237 */ 1238 exception_init(&e500_intrsw); 1239 1240 printf(" exception_init=%p", &e500_intrsw); 1241 1242 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1243 1244 /* 1245 * Set the page size. 1246 */ 1247 uvm_setpagesize(); 1248 1249 /* 1250 * Initialize the pmap. 1251 */ 1252 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1253 1254 /* 1255 * Let's take all the indirect calls via our stubs and patch 1256 * them to be direct calls. 1257 */ 1258 cpu_fixup_stubs(); 1259 1260 /* 1261 * As a debug measure we can change the TLB entry that maps all of 1262 * memory to one that encompasses the 64KB with the kernel vectors. 1263 * All other pages will be soft faulted into the TLB as needed. 1264 */ 1265 e500_tlb_minimize(endkernel); 1266 1267 /* 1268 * Set some more MD helpers 1269 */ 1270 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1271 cpu_md_ops.md_device_register = e500_device_register; 1272 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1273 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1274 #if NGPIO > 0 1275 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1276 #endif 1277 1278 printf(" initppc done!\n"); 1279 1280 /* 1281 * Look for the Book-E modules in the right place. 1282 */ 1283 module_machine = module_machine_booke; 1284 } 1285 1286 #ifdef MPC8548 1287 static const char * const mpc8548cds_extirq_names[] = { 1288 [0] = "pci inta", 1289 [1] = "pci intb", 1290 [2] = "pci intc", 1291 [3] = "pci intd", 1292 [4] = "irq4", 1293 [5] = "gige phy", 1294 [6] = "atm phy", 1295 [7] = "cpld", 1296 [8] = "irq8", 1297 [9] = "nvram", 1298 [10] = "debug", 1299 [11] = "pci2 inta", 1300 }; 1301 #endif 1302 1303 #ifndef MPC8548 1304 static const char * const mpc85xx_extirq_names[] = { 1305 [0] = "extirq 0", 1306 [1] = "extirq 1", 1307 [2] = "extirq 2", 1308 [3] = "extirq 3", 1309 [4] = "extirq 4", 1310 [5] = "extirq 5", 1311 [6] = "extirq 6", 1312 [7] = "extirq 7", 1313 [8] = "extirq 8", 1314 [9] = "extirq 9", 1315 [10] = "extirq 10", 1316 [11] = "extirq 11", 1317 }; 1318 #endif 1319 1320 static void 1321 mpc85xx_extirq_setup(void) 1322 { 1323 #ifdef MPC8548 1324 const char * const * names = mpc8548cds_extirq_names; 1325 const size_t n = __arraycount(mpc8548cds_extirq_names); 1326 #else 1327 const char * const * names = mpc85xx_extirq_names; 1328 const size_t n = __arraycount(mpc85xx_extirq_names); 1329 #endif 1330 prop_array_t extirqs = prop_array_create_with_capacity(n); 1331 for (u_int i = 0; i < n; i++) { 1332 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1333 prop_array_set(extirqs, i, ps); 1334 prop_object_release(ps); 1335 } 1336 board_info_add_object("external-irqs", extirqs); 1337 prop_object_release(extirqs); 1338 } 1339 1340 static void 1341 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1342 { 1343 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1344 KASSERT(pci_intmap != NULL); 1345 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1346 KASSERT(mask != NULL); 1347 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1348 prop_object_release(mask); 1349 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1350 KASSERT(pn_ist != NULL); 1351 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1352 KASSERT(pn_intr != NULL); 1353 prop_dictionary_t entry = prop_dictionary_create(); 1354 KASSERT(entry != NULL); 1355 prop_dictionary_set(entry, "interrupt", pn_intr); 1356 prop_dictionary_set(entry, "type", pn_ist); 1357 prop_dictionary_set(pci_intmap, "000000", entry); 1358 prop_object_release(pn_intr); 1359 prop_object_release(entry); 1360 va_list ap; 1361 va_start(ap, inta); 1362 u_int intrinc = __LOWEST_SET_BIT(intmask); 1363 for (u_int i = 0; i < intmask; i += intrinc) { 1364 char prop_name[12]; 1365 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1366 entry = prop_dictionary_create(); 1367 KASSERT(entry != NULL); 1368 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1369 KASSERT(pn_intr != NULL); 1370 prop_dictionary_set(entry, "interrupt", pn_intr); 1371 prop_dictionary_set(entry, "type", pn_ist); 1372 prop_dictionary_set(pci_intmap, prop_name, entry); 1373 prop_object_release(pn_intr); 1374 prop_object_release(entry); 1375 } 1376 va_end(ap); 1377 prop_object_release(pn_ist); 1378 board_info_add_object(name, pci_intmap); 1379 prop_object_release(pci_intmap); 1380 } 1381 1382 void 1383 cpu_startup(void) 1384 { 1385 struct cpu_info * const ci = curcpu(); 1386 const uint16_t svr = getsvr(); 1387 1388 powersave = 0; /* we can do it but turn it on by default */ 1389 1390 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1391 1392 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1393 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1394 uint32_t e500_ratio = E500_RATIO_GET(v); 1395 1396 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1397 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1398 1399 ci->ci_khz = (cpu_freq + 500) / 1000; 1400 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1401 1402 board_info_add_number("my-id", svr); 1403 board_info_add_bool("pq3"); 1404 board_info_add_number("mem-size", pmemsize); 1405 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1406 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1407 uint32_t l2banks = l2siz >> 16; 1408 #ifdef MPC85555 1409 if (svr == (MPC8555v1 >> 16)) { 1410 l2siz >>= 1; 1411 l2banks >>= 1; 1412 } 1413 #endif 1414 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1415 if (boot_page & BPTR_EN) { 1416 bool found = false; 1417 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1418 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1419 * const bp = (void *)boot_page; 1420 bp <= dp; dp--) { 1421 if (*dp == boot_page) { 1422 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1423 spinup_table_addr = 1424 roundup2(spinup_table_addr, 32); 1425 board_info_add_number("mp-boot-page", 1426 boot_page); 1427 board_info_add_number("mp-spin-up-table", 1428 spinup_table_addr); 1429 printf("Found MP boot page @ %#"PRIxPADDR". " 1430 "Spin-up table @ %#"PRIxPTR"\n", 1431 boot_page, spinup_table_addr); 1432 found = true; 1433 break; 1434 } 1435 } 1436 if (!found) { 1437 printf("Found MP boot page @ %#"PRIxPADDR 1438 " with missing U-boot signature!\n", boot_page); 1439 board_info_add_number("mp-spin-up-table", 0); 1440 } 1441 } 1442 board_info_add_number("l2-cache-size", l2siz); 1443 board_info_add_number("l2-cache-line-size", 32); 1444 board_info_add_number("l2-cache-banks", l2banks); 1445 board_info_add_number("l2-cache-ways", 8); 1446 1447 board_info_add_number("processor-frequency", cpu_freq); 1448 board_info_add_number("bus-frequency", ccb_freq); 1449 board_info_add_number("pci-frequency", e500_sys_clk); 1450 board_info_add_number("timebase-frequency", ccb_freq / 8); 1451 1452 #ifdef CADMUS 1453 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1454 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1455 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1456 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1457 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1458 #else 1459 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1460 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1461 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1462 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1463 #endif 1464 1465 uint64_t macstnaddr = 1466 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1467 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1468 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1469 1470 #if NPCI > 0 && defined(PCI_MEMBASE) 1471 pcimem_ex = extent_create("pcimem", 1472 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1473 NULL, 0, EX_WAITOK); 1474 #endif 1475 #if NPCI > 0 && defined(PCI_IOBASE) 1476 pciio_ex = extent_create("pciio", 1477 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1478 NULL, 0, EX_WAITOK); 1479 #endif 1480 mpc85xx_extirq_setup(); 1481 /* 1482 * PCI-Express virtual wire interrupts on combined with 1483 * External IRQ0/1/2/3. 1484 */ 1485 switch (svr) { 1486 #if defined(MPC8548) 1487 case SVR_MPC8548v1 >> 16: 1488 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1489 IST_LEVEL, 0, 1, 2, 3); 1490 break; 1491 #endif 1492 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \ 1493 || defined(P1025) || defined(P2020) 1494 case SVR_MPC8536v1 >> 16: 1495 case SVR_MPC8544v1 >> 16: 1496 case SVR_MPC8572v1 >> 16: 1497 case SVR_P1016v1 >> 16: 1498 case SVR_P2010v2 >> 16: 1499 case SVR_P2020v2 >> 16: 1500 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1501 8, 9, 10, 11); 1502 /* FALLTHROUGH */ 1503 case SVR_P1025v1 >> 16: 1504 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1505 4, 5, 6, 7); 1506 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1507 0, 1, 2, 3); 1508 break; 1509 #endif 1510 } 1511 switch (svr) { 1512 #if defined(MPC8536) 1513 case SVR_MPC8536v1 >> 16: 1514 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1515 1, 2, 3, 4); 1516 break; 1517 #endif 1518 #if defined(MPC8544) 1519 case SVR_MPC8544v1 >> 16: 1520 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1521 0, 1, 2, 3); 1522 break; 1523 #endif 1524 #if defined(MPC8548) 1525 case SVR_MPC8548v1 >> 16: 1526 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1527 0, 1, 2, 3); 1528 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1529 11, 1, 2, 3); 1530 break; 1531 #endif 1532 } 1533 } 1534
Indexes created Mon Sep 29 15:09:53 GMT 2025