machdep.c revision 1.37
1 /* $NetBSD: machdep.c,v 1.37 2014/12/27 16:19:33 nonaka Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_altivec.h" 42 #include "opt_ddb.h" 43 #include "opt_mpc85xx.h" 44 #include "opt_pci.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/reboot.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <dev/cons.h> 70 71 #include <dev/ic/comreg.h> 72 #include <dev/ic/comvar.h> 73 74 #include <net/if.h> 75 #include <net/if_media.h> 76 #include <dev/mii/miivar.h> 77 78 #include <powerpc/pcb.h> 79 #include <powerpc/spr.h> 80 #include <powerpc/booke/spr.h> 81 82 #include <powerpc/booke/cpuvar.h> 83 #include <powerpc/booke/e500reg.h> 84 #include <powerpc/booke/e500var.h> 85 #include <powerpc/booke/etsecreg.h> 86 #include <powerpc/booke/openpicreg.h> 87 #ifdef CADMUS 88 #include <evbppc/mpc85xx/cadmusreg.h> 89 #endif 90 #ifdef PIXIS 91 #include <evbppc/mpc85xx/pixisreg.h> 92 #endif 93 94 struct uboot_bdinfo { 95 uint32_t bd_memstart; 96 uint32_t bd_memsize; 97 uint32_t bd_flashstart; 98 uint32_t bd_flashsize; 99 /*10*/ uint32_t bd_flashoffset; 100 uint32_t bd_sramstart; 101 uint32_t bd_sramsize; 102 uint32_t bd_immrbase; 103 /*20*/ uint32_t bd_bootflags; 104 uint32_t bd_ipaddr; 105 uint8_t bd_etheraddr[6]; 106 uint16_t bd_ethspeed; 107 /*30*/ uint32_t bd_intfreq; 108 uint32_t bd_cpufreq; 109 uint32_t bd_baudrate; 110 /*3c*/ uint8_t bd_etheraddr1[6]; 111 /*42*/ uint8_t bd_etheraddr2[6]; 112 /*48*/ uint8_t bd_etheraddr3[6]; 113 /*4e*/ uint16_t bd_pad; 114 }; 115 116 char root_string[16]; 117 118 /* 119 * booke kernels need to set module_machine to this for modules to work. 120 */ 121 char module_machine_booke[] = "powerpc-booke"; 122 123 void initppc(vaddr_t, vaddr_t, void *, void *, char *, char *); 124 125 #define MEMREGIONS 4 126 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 127 phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 128 static u_int nmemr; 129 130 #ifndef CONSFREQ 131 # define CONSFREQ -1 /* inherit from firmware */ 132 #endif 133 #ifndef CONSPEED 134 # define CONSPEED 115200 135 #endif 136 #ifndef CONMODE 137 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 138 #endif 139 #ifndef CONSADDR 140 # define CONSADDR DUART2_BASE 141 #endif 142 143 int comcnfreq = CONSFREQ; 144 int comcnspeed = CONSPEED; 145 tcflag_t comcnmode = CONMODE; 146 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 147 148 #if NPCI > 0 149 struct extent *pcimem_ex; 150 struct extent *pciio_ex; 151 #endif 152 153 struct powerpc_bus_space gur_bst = { 154 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 155 .pbs_offset = GUR_BASE, 156 .pbs_limit = GUR_SIZE, 157 }; 158 159 struct powerpc_bus_space gur_le_bst = { 160 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 161 .pbs_offset = GUR_BASE, 162 .pbs_limit = GUR_SIZE, 163 }; 164 165 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 166 167 #if defined(SYS_CLK) 168 static uint64_t e500_sys_clk = SYS_CLK; 169 #endif 170 #ifdef CADMUS 171 static uint8_t cadmus_pci; 172 static uint8_t cadmus_csr; 173 #ifndef SYS_CLK 174 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 175 #endif 176 #elif defined(PIXIS) 177 static const uint32_t pixis_spd_map[8] = { 178 [PX_SPD_33MHZ] = 33333333, 179 [PX_SPD_40MHZ] = 40000000, 180 [PX_SPD_50MHZ] = 50000000, 181 [PX_SPD_66MHZ] = 66666666, 182 [PX_SPD_83MHZ] = 83333333, 183 [PX_SPD_100MHZ] = 100000000, 184 [PX_SPD_133MHZ] = 133333333, 185 [PX_SPD_166MHZ] = 166666667, 186 }; 187 static uint8_t pixis_spd; 188 #ifndef SYS_CLK 189 static uint64_t e500_sys_clk; 190 #endif 191 #elif !defined(SYS_CLK) 192 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 193 #endif 194 195 static int e500_cngetc(dev_t); 196 static void e500_cnputc(dev_t, int); 197 198 static struct consdev e500_earlycons = { 199 .cn_getc = e500_cngetc, 200 .cn_putc = e500_cnputc, 201 .cn_pollc = nullcnpollc, 202 }; 203 204 /* 205 * List of port-specific devices to attach to the processor local bus. 206 */ 207 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 208 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 209 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 210 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 211 #if defined(MPC8572) || defined(P2020) || defined(P1025) \ 212 || defined(P1023) 213 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 214 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 215 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 216 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 217 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 218 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 219 #endif 220 { "wdog" }, /* not a real device */ 221 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 222 1, { ISOURCE_DUART }, 223 1 + ilog2(DEVDISR_DUART) }, 224 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 225 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 226 1 + ilog2(DEVDISR_TSEC1), 227 { 0xffff, SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 228 #if defined(P1025) 229 { "mdio", ETSEC1_BASE, ETSEC_SIZE, 1, 230 0, { }, 231 1 + ilog2(DEVDISR_TSEC1), 232 { SVR_P1025v1 >> 16 } }, 233 { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1, 234 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 235 1 + ilog2(DEVDISR_TSEC1), 236 { SVR_P1025v1 >> 16 } }, 237 #if 0 238 { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1, 239 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX, 240 ISOURCE_ETSEC1_G1_ERR }, 241 1 + ilog2(DEVDISR_TSEC1), 242 { SVR_P1025v1 >> 16 } }, 243 #endif 244 #endif 245 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \ 246 || defined(P2020) 247 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 248 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 249 1 + ilog2(DEVDISR_TSEC2), 250 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 251 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 252 SVR_P1025v1 >> 16 } }, 253 #endif 254 #if defined(P1025) 255 { "mdio", ETSEC2_BASE, ETSEC_SIZE, 2, 256 0, { }, 257 1 + ilog2(DEVDISR_TSEC2), 258 { SVR_P1025v1 >> 16 } }, 259 { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2, 260 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 261 1 + ilog2(DEVDISR_TSEC2), 262 { SVR_P1025v1 >> 16 } }, 263 #if 0 264 { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5, 265 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX, 266 ISOURCE_ETSEC2_G1_ERR }, 267 1 + ilog2(DEVDISR_TSEC2), 268 { SVR_P1025v1 >> 16 } }, 269 #endif 270 #endif 271 #if defined(MPC8544) || defined(MPC8536) 272 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 273 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 274 1 + ilog2(DEVDISR_TSEC3), 275 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 276 #endif 277 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 278 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 279 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 280 1 + ilog2(DEVDISR_TSEC3), 281 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 282 SVR_P2020v2 >> 16 } }, 283 #endif 284 #if defined(P1025) 285 { "mdio", ETSEC3_BASE, ETSEC_SIZE, 3, 286 0, { }, 287 1 + ilog2(DEVDISR_TSEC3), 288 { SVR_P1025v1 >> 16 } }, 289 { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3, 290 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 291 1 + ilog2(DEVDISR_TSEC3), 292 { SVR_P1025v1 >> 16 } }, 293 #if 0 294 { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3, 295 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX, 296 ISOURCE_ETSEC3_G1_ERR }, 297 1 + ilog2(DEVDISR_TSEC3), 298 { SVR_P1025v1 >> 16 } }, 299 #endif 300 #endif 301 #if defined(MPC8548) || defined(MPC8572) 302 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 303 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 304 1 + ilog2(DEVDISR_TSEC4), 305 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 306 #endif 307 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 308 1, { ISOURCE_I2C }, 309 1 + ilog2(DEVDISR_I2C) }, 310 /* MPC8572 doesn't have any GPIO */ 311 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 312 1, { ISOURCE_GPIO }, 313 0, 314 { 0xffff, SVR_MPC8572v1 >> 16 } }, 315 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 316 1, { ISOURCE_DDR }, 317 1 + ilog2(DEVDISR_DDR_15), 318 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 319 #if defined(MPC8536) 320 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 321 1, { ISOURCE_DDR }, 322 1 + ilog2(DEVDISR_DDR_16), 323 { SVR_MPC8536v1 >> 16 } }, 324 #endif 325 #if defined(MPC8572) 326 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 327 1, { ISOURCE_DDR }, 328 1 + ilog2(DEVDISR_DDR_15), 329 { SVR_MPC8572v1 >> 16 } }, 330 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 331 1, { ISOURCE_DDR }, 332 1 + ilog2(DEVDISR_DDR2_14), 333 { SVR_MPC8572v1 >> 16 } }, 334 #endif 335 { "lbc", LBC_BASE, LBC_SIZE, 0, 336 1, { ISOURCE_LBC }, 337 1 + ilog2(DEVDISR_LBC) }, 338 #if defined(MPC8544) || defined(MPC8536) 339 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 340 1, { ISOURCE_PCIEX }, 341 1 + ilog2(DEVDISR_PCIE), 342 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 343 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 344 1, { ISOURCE_PCIEX2 }, 345 1 + ilog2(DEVDISR_PCIE2), 346 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 347 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 348 1, { ISOURCE_PCIEX3 }, 349 1 + ilog2(DEVDISR_PCIE3), 350 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 351 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 352 1, { ISOURCE_PCI1 }, 353 1 + ilog2(DEVDISR_PCI1), 354 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 355 #endif 356 #ifdef MPC8548 357 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 358 1, { ISOURCE_PCIEX }, 359 1 + ilog2(DEVDISR_PCIE), 360 { SVR_MPC8548v1 >> 16 }, }, 361 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 362 1, { ISOURCE_PCI1 }, 363 1 + ilog2(DEVDISR_PCI1), 364 { SVR_MPC8548v1 >> 16 }, }, 365 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 366 1, { ISOURCE_PCI2 }, 367 1 + ilog2(DEVDISR_PCI2), 368 { SVR_MPC8548v1 >> 16 }, }, 369 #endif 370 #if defined(MPC8572) || defined(P1025) || defined(P2020) \ 371 || defined(P1023) 372 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 373 1, { ISOURCE_PCIEX }, 374 1 + ilog2(DEVDISR_PCIE), 375 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 376 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 377 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 378 1, { ISOURCE_PCIEX2 }, 379 1 + ilog2(DEVDISR_PCIE2), 380 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 381 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 382 #endif 383 #if defined(MPC8572) || defined(P2020) || defined(_P1023) 384 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 385 1, { ISOURCE_PCIEX3_MPC8572 }, 386 1 + ilog2(DEVDISR_PCIE3), 387 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 388 SVR_P1023v1 >> 16 } }, 389 #endif 390 #if defined(MPC8536) || defined(P1025) || defined(P2020) \ 391 || defined(P1023) 392 { "ehci", USB1_BASE, USB_SIZE, 1, 393 1, { ISOURCE_USB1 }, 394 1 + ilog2(DEVDISR_USB1), 395 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16, 396 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 397 #endif 398 #ifdef MPC8536 399 { "ehci", USB2_BASE, USB_SIZE, 2, 400 1, { ISOURCE_USB2 }, 401 1 + ilog2(DEVDISR_USB2), 402 { SVR_MPC8536v1 >> 16 }, }, 403 { "ehci", USB3_BASE, USB_SIZE, 3, 404 1, { ISOURCE_USB3 }, 405 1 + ilog2(DEVDISR_USB3), 406 { SVR_MPC8536v1 >> 16 }, }, 407 { "sata", SATA1_BASE, SATA_SIZE, 1, 408 1, { ISOURCE_SATA1 }, 409 1 + ilog2(DEVDISR_SATA1), 410 { SVR_MPC8536v1 >> 16 }, }, 411 { "sata", SATA2_BASE, SATA_SIZE, 2, 412 1, { ISOURCE_SATA2 }, 413 1 + ilog2(DEVDISR_SATA2), 414 { SVR_MPC8536v1 >> 16 }, }, 415 { "spi", SPI_BASE, SPI_SIZE, 0, 416 1, { ISOURCE_SPI }, 417 1 + ilog2(DEVDISR_SPI_15), 418 { SVR_MPC8536v1 >> 16 }, }, 419 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 420 1, { ISOURCE_ESDHC }, 421 1 + ilog2(DEVDISR_ESDHC_12), 422 { SVR_MPC8536v1 >> 16 }, }, 423 #endif 424 #if defined(P1025) || defined(P2020) || defined(P1023) 425 { "spi", SPI_BASE, SPI_SIZE, 0, 426 1, { ISOURCE_SPI }, 427 1 + ilog2(DEVDISR_SPI_28), 428 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16, 429 SVR_P1023v1 >> 16 }, }, 430 #endif 431 #if defined(P1025) || defined(P2020) 432 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 433 1, { ISOURCE_ESDHC }, 434 1 + ilog2(DEVDISR_ESDHC_10), 435 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 436 #endif 437 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 438 { NULL } 439 }; 440 441 static int 442 e500_cngetc(dev_t dv) 443 { 444 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 445 446 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 447 return -1; 448 449 return com0addr[com_data] & 0xff; 450 } 451 452 static void 453 e500_cnputc(dev_t dv, int c) 454 { 455 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 456 int timo = 150000; 457 458 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 459 ; 460 461 com0addr[com_data] = c; 462 __asm("mbar"); 463 464 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 465 ; 466 } 467 468 static void * 469 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 470 { 471 if (prefetchable) 472 return NULL; 473 if (pa < gur_bst.pbs_offset) 474 return NULL; 475 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 476 return NULL; 477 return (void *)pa; 478 } 479 480 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 481 482 static void 483 e500_cpu_reset(void) 484 { 485 __asm volatile("sync"); 486 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 487 __asm volatile("msync;isync"); 488 } 489 490 static psize_t 491 memprobe(vaddr_t endkernel) 492 { 493 phys_ram_seg_t *mr; 494 paddr_t boot_page = cpu_read_4(GUR_BPTR); 495 printf(" bptr=%"PRIxPADDR, boot_page); 496 if (boot_page & BPTR_EN) { 497 /* 498 * shift it to an address 499 */ 500 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 501 } else { 502 boot_page = ~(paddr_t)0; 503 } 504 505 /* 506 * First we need to find out how much physical memory we have. 507 * We could let our bootloader tell us, but it's almost as easy 508 * to ask the DDR memory controller. 509 */ 510 mr = physmemr; 511 for (u_int i = 0; i < 4; i++) { 512 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 513 if (v & CS_CONFIG_EN) { 514 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 515 if (v == 0) 516 continue; 517 mr->start = BNDS_SA_GET(v); 518 mr->size = BNDS_SIZE_GET(v); 519 #ifdef MEMSIZE 520 if (mr->start >= MEMSIZE) 521 continue; 522 if (mr->start + mr->size > MEMSIZE) 523 mr->size = MEMSIZE - mr->start; 524 #endif 525 #if 0 526 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 527 mr - physmemr, mr->size, mr->start); 528 #endif 529 mr++; 530 } 531 } 532 533 if (mr == physmemr) 534 panic("no memory configured!"); 535 536 /* 537 * Sort memory regions from low to high and coalesce adjacent regions 538 */ 539 u_int cnt = mr - physmemr; 540 if (cnt > 1) { 541 for (u_int i = 0; i < cnt - 1; i++) { 542 for (u_int j = i + 1; j < cnt; j++) { 543 if (physmemr[j].start < physmemr[i].start) { 544 phys_ram_seg_t tmp = physmemr[i]; 545 physmemr[i] = physmemr[j]; 546 physmemr[j] = tmp; 547 } 548 } 549 } 550 mr = physmemr; 551 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 552 if (mr->start + mr->size == mr[1].start) { 553 mr->size += mr[1].size; 554 for (u_int j = 1; i + j + 1 < cnt; j++) 555 mr[j] = mr[j+1]; 556 cnt--; 557 } 558 } 559 } else if (cnt == 0) { 560 panic("%s: no memory found", __func__); 561 } 562 563 /* 564 * Copy physical memory to available memory. 565 */ 566 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 567 568 /* 569 * Adjust available memory to skip kernel at start of memory. 570 */ 571 availmemr[0].size -= endkernel - availmemr[0].start; 572 availmemr[0].start = endkernel; 573 574 mr = availmemr; 575 for (u_int i = 0; i < cnt; i++, mr++) { 576 /* 577 * U-boot reserves a boot-page on multi-core chips. 578 * We need to make sure that we never disturb it. 579 */ 580 const paddr_t mr_end = mr->start + mr->size; 581 if (mr_end > boot_page && boot_page >= mr->start) { 582 /* 583 * Normally u-boot will put in at the end 584 * of memory. But in case it doesn't, deal 585 * with all possibilities. 586 */ 587 if (boot_page + PAGE_SIZE == mr_end) { 588 mr->size -= PAGE_SIZE; 589 } else if (boot_page == mr->start) { 590 mr->start += PAGE_SIZE; 591 mr->size -= PAGE_SIZE; 592 } else { 593 mr->size = boot_page - mr->start; 594 mr++; 595 for (u_int j = cnt; j > i + 1; j--) { 596 availmemr[j] = availmemr[j-1]; 597 } 598 cnt++; 599 mr->start = boot_page + PAGE_SIZE; 600 mr->size = mr_end - mr->start; 601 } 602 break; 603 } 604 } 605 606 /* 607 * Steal pages at the end of memory for the kernel message buffer. 608 */ 609 mr = availmemr + cnt - 1; 610 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 611 mr->size -= round_page(MSGBUFSIZE); 612 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 613 614 /* 615 * Calculate physmem. 616 */ 617 for (u_int i = 0; i < cnt; i++) 618 physmem += atop(physmemr[i].size); 619 620 nmemr = cnt; 621 return physmemr[cnt-1].start + physmemr[cnt-1].size; 622 } 623 624 void 625 consinit(void) 626 { 627 static bool attached = false; 628 629 if (attached) 630 return; 631 attached = true; 632 633 if (comcnfreq == -1) { 634 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 635 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 636 comcnfreq = e500_sys_clk * plat_ratio; 637 printf(" comcnfreq=%u", comcnfreq); 638 } 639 640 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 641 COM_TYPE_NORMAL, comcnmode); 642 } 643 644 void 645 cpu_probe_cache(void) 646 { 647 struct cpu_info * const ci = curcpu(); 648 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 649 const int dcache_assoc = L1CFG_CNWAY_GET(l1cfg0); 650 651 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 652 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 653 654 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 655 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 656 657 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 658 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 659 } else { 660 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 661 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 662 } 663 664 /* 665 * Possibly recolor. 666 */ 667 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / dcache_assoc)); 668 669 #ifdef DEBUG 670 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 671 if ((L1CSR_CE & l1csr0) == 0) 672 printf(" DC=off"); 673 674 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 675 if ((L1CSR_CE & l1csr1) == 0) 676 printf(" IC=off"); 677 #endif 678 } 679 680 static uint16_t 681 getsvr(void) 682 { 683 uint16_t svr = mfspr(SPR_SVR) >> 16; 684 685 svr &= ~0x8; /* clear security bit */ 686 switch (svr) { 687 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 688 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 689 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 690 case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16; 691 case SVR_P1017v1 >> 16: return SVR_P1023v1 >> 16; 692 default: return svr; 693 } 694 } 695 696 static const char * 697 socname(uint32_t svr) 698 { 699 svr &= ~0x80000; /* clear security bit */ 700 switch (svr >> 8) { 701 case SVR_MPC8533 >> 8: return "MPC8533"; 702 case SVR_MPC8536v1 >> 8: return "MPC8536"; 703 case SVR_MPC8541v1 >> 8: return "MPC8541"; 704 case SVR_MPC8543v2 >> 8: return "MPC8543"; 705 case SVR_MPC8544v1 >> 8: return "MPC8544"; 706 case SVR_MPC8545v2 >> 8: return "MPC8545"; 707 case SVR_MPC8547v2 >> 8: return "MPC8547"; 708 case SVR_MPC8548v2 >> 8: return "MPC8548"; 709 case SVR_MPC8555v1 >> 8: return "MPC8555"; 710 case SVR_MPC8568v1 >> 8: return "MPC8568"; 711 case SVR_MPC8567v1 >> 8: return "MPC8567"; 712 case SVR_MPC8572v1 >> 8: return "MPC8572"; 713 case SVR_P2020v2 >> 8: return "P2020"; 714 case SVR_P2010v2 >> 8: return "P2010"; 715 case SVR_P1016v1 >> 8: return "P1016"; 716 case SVR_P1017v1 >> 8: return "P1017"; 717 case SVR_P1023v1 >> 8: return "P1023"; 718 case SVR_P1025v1 >> 8: return "P1025"; 719 default: 720 panic("%s: unknown SVR %#x", __func__, svr); 721 } 722 } 723 724 static void 725 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 726 { 727 static const char units[16] = "KKKKKMMMMMGGGGGT"; 728 729 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 730 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 731 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 732 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 733 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 734 735 aprint_normal_dev(self, "%s:", name); 736 737 aprint_normal(" %u", nentries); 738 if (TLBCFG_AVAIL_P(tlbcfg)) { 739 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 740 minsize, maxsize, units[maxsize_log4k]); 741 } else { 742 aprint_normal(" fixed-size (%uKB)", minsize); 743 } 744 if (assoc == 0 || assoc == nentries) 745 aprint_normal(" fully"); 746 else 747 aprint_normal(" %u-way set", assoc); 748 aprint_normal(" associative entries\n"); 749 } 750 751 static void 752 cpu_print_info(struct cpu_info *ci) 753 { 754 uint64_t freq = board_info_get_number("processor-frequency"); 755 device_t self = ci->ci_dev; 756 757 char freqbuf[10]; 758 if (freq >= 999500000) { 759 const uint32_t freq32 = (freq + 500000) / 10000000; 760 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 761 freq32 / 100, freq32 % 100); 762 } else { 763 const uint32_t freq32 = (freq + 500000) / 1000000; 764 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 765 } 766 767 const uint32_t pvr = mfpvr(); 768 const uint32_t svr = mfspr(SPR_SVR); 769 const uint32_t pir = mfspr(SPR_PIR); 770 771 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 772 "ID %u%s\n", 773 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 774 (svr >> 4) & 15, svr & 15, 775 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 776 (pvr >> 4) & 15, pvr & 15, 777 pir, (pir == 0 ? " (Primary)" : "")); 778 779 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 780 aprint_normal_dev(self, 781 "%uKB/%uB %u-way L1 %s cache\n", 782 L1CFG_CSIZE_GET(l1cfg0) >> 10, 783 32 << L1CFG_CBSIZE_GET(l1cfg0), 784 L1CFG_CNWAY_GET(l1cfg0), 785 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 786 ? "data" : "unified"); 787 788 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 789 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 790 aprint_normal_dev(self, 791 "%uKB/%uB %u-way L1 %s cache\n", 792 L1CFG_CSIZE_GET(l1cfg1) >> 10, 793 32 << L1CFG_CBSIZE_GET(l1cfg1), 794 L1CFG_CNWAY_GET(l1cfg1), 795 "instruction"); 796 } 797 798 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 799 aprint_normal_dev(self, 800 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 801 MMUCFG_NTLBS_GET(mmucfg) + 1, 802 MMUCFG_NPIDS_GET(mmucfg), 803 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 804 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 805 806 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 807 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 808 } 809 810 #ifdef MULTIPROCESSOR 811 static void 812 e500_cpu_spinup(device_t self, struct cpu_info *ci) 813 { 814 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 815 struct pglist splist; 816 817 if (spinup_table_addr == 0) { 818 aprint_error_dev(self, "hatch failed (no spin-up table)"); 819 return; 820 } 821 822 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 823 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 824 const size_t id = cpu_index(ci); 825 kcpuset_t * const hatchlings = cpuset_info.cpus_hatched; 826 827 if (h->hatch_sp == 0) { 828 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 829 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 830 if (error) { 831 aprint_error_dev(self, 832 "unable to allocate hatch stack\n"); 833 return; 834 } 835 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 836 + PAGE_SIZE - CALLFRAMELEN; 837 } 838 839 840 for (size_t i = 1; e[i].entry_pir != 0; i++) { 841 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 842 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 843 if (e[i].entry_pir == ci->ci_cpuid) { 844 845 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 846 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 847 ci->ci_curpm = pmap_kernel(); 848 ci->ci_lasttb = cpu_info[0].ci_lasttb; 849 ci->ci_data.cpu_cc_freq = 850 cpu_info[0].ci_data.cpu_cc_freq; 851 852 h->hatch_self = self; 853 h->hatch_ci = ci; 854 h->hatch_running = -1; 855 h->hatch_pir = e[i].entry_pir; 856 h->hatch_hid0 = mfspr(SPR_HID0); 857 u_int tlbidx; 858 e500_tlb_lookup_xtlb(0, &tlbidx); 859 h->hatch_tlbidx = tlbidx; 860 KASSERT(h->hatch_sp != 0); 861 /* 862 * Get new timebase. We don't want to deal with 863 * timebase crossing a 32-bit boundary so make sure 864 * that we have enough headroom to do the timebase 865 * synchronization. 866 */ 867 #define TBSYNC_SLOP 2000 868 uint32_t tbl; 869 uint32_t tbu; 870 do { 871 tbu = mfspr(SPR_RTBU); 872 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 873 } while (tbl < TBSYNC_SLOP); 874 875 h->hatch_tbu = tbu; 876 h->hatch_tbl = tbl; 877 __asm("sync;isync"); 878 dcache_wbinv((vaddr_t)h, sizeof(*h)); 879 880 /* 881 * And here we go... 882 */ 883 e[i].entry_addr_lower = 884 (uint32_t)e500_spinup_trampoline; 885 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 886 __asm __volatile("sync;isync"); 887 __insn_barrier(); 888 889 for (u_int timo = 0; timo++ < 10000; ) { 890 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 891 if (e[i].entry_addr_lower == 3) { 892 #if 0 893 printf( 894 "%s: cpu%u started in %u spins\n", 895 __func__, cpu_index(ci), timo); 896 #endif 897 break; 898 } 899 } 900 for (u_int timo = 0; timo++ < 10000; ) { 901 dcache_inv((vaddr_t)h, sizeof(*h)); 902 if (h->hatch_running == 0) { 903 #if 0 904 printf( 905 "%s: cpu%u cracked in %u spins: (running=%d)\n", 906 __func__, cpu_index(ci), 907 timo, h->hatch_running); 908 #endif 909 break; 910 } 911 } 912 if (h->hatch_running == -1) { 913 aprint_error_dev(self, 914 "hatch failed (timeout): running=%d" 915 ", entry=%#x\n", 916 h->hatch_running, e[i].entry_addr_lower); 917 goto out; 918 } 919 920 /* 921 * First then we do is to synchronize timebases. 922 * TBSYNC_SLOP*16 should be more than enough 923 * instructions. 924 */ 925 while (tbl != mftbl()) 926 continue; 927 h->hatch_running = 1; 928 dcache_wbinv((vaddr_t)h, sizeof(*h)); 929 __asm("sync;isync"); 930 __insn_barrier(); 931 printf("%s: cpu%u set to running\n", 932 __func__, cpu_index(ci)); 933 934 for (u_int timo = 10000; timo-- > 0; ) { 935 dcache_inv((vaddr_t)h, sizeof(*h)); 936 if (h->hatch_running > 1) 937 break; 938 } 939 if (h->hatch_running == 1) { 940 printf( 941 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 942 __func__, 943 ((int64_t)tbu << 32) + tbl, 944 (int64_t) 945 (((uint64_t)h->hatch_tbu << 32) 946 + (uint64_t)h->hatch_tbl), 947 h->hatch_running); 948 goto out; 949 } 950 printf( 951 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 952 __func__, 953 (int64_t) 954 (((uint64_t)h->hatch_tbu << 32) 955 + (uint64_t)h->hatch_tbl), 956 h->hatch_running); 957 /* 958 * Now we wait for the hatching to complete. 30ms 959 * should be long enough. 960 */ 961 for (u_int timo = 30000; timo-- > 0; ) { 962 if (kcpuset_isset(hatchlings, id)) { 963 aprint_normal_dev(self, 964 "hatch successful (%u spins, " 965 "timebase adjusted by %"PRId64")\n", 966 30000 - timo, 967 (int64_t) 968 (((uint64_t)h->hatch_tbu << 32) 969 + (uint64_t)h->hatch_tbl)); 970 goto out; 971 } 972 DELAY(1); 973 } 974 975 aprint_error_dev(self, 976 "hatch failed (timeout): running=%u\n", 977 h->hatch_running); 978 goto out; 979 } 980 } 981 982 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 983 ci->ci_cpuid); 984 out: 985 if (h->hatch_sp == 0) 986 uvm_pglistfree(&splist); 987 } 988 #endif 989 990 void 991 e500_cpu_hatch(struct cpu_info *ci) 992 { 993 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 994 995 /* 996 * Make sure interrupts are blocked. 997 */ 998 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 999 1000 intr_cpu_hatch(ci); 1001 1002 cpu_probe_cache(); 1003 cpu_print_info(ci); 1004 1005 /* 1006 */ 1007 } 1008 1009 static void 1010 e500_cpu_attach(device_t self, u_int instance) 1011 { 1012 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 1013 1014 if (instance > 1) { 1015 #if defined(MULTIPROCESSOR) 1016 ci->ci_idepth = -1; 1017 self->dv_private = ci; 1018 1019 ci->ci_cpuid = instance - (instance > 0); 1020 ci->ci_dev = self; 1021 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 1022 1023 mi_cpu_attach(ci); 1024 1025 intr_cpu_attach(ci); 1026 cpu_evcnt_attach(ci); 1027 1028 e500_cpu_spinup(self, ci); 1029 return; 1030 #else 1031 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 1032 return; 1033 #endif 1034 } 1035 1036 self->dv_private = ci; 1037 1038 ci->ci_cpuid = instance - (instance > 0); 1039 ci->ci_dev = self; 1040 1041 intr_cpu_attach(ci); 1042 cpu_evcnt_attach(ci); 1043 1044 KASSERT(ci == curcpu()); 1045 intr_cpu_hatch(ci); 1046 1047 cpu_print_info(ci); 1048 } 1049 1050 void 1051 e500_ipi_halt(void) 1052 { 1053 register_t msr, hid0; 1054 1055 msr = wrtee(0); 1056 1057 hid0 = mfspr(SPR_HID0); 1058 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 1059 mtspr(SPR_HID0, hid0); 1060 1061 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 1062 mtmsr(msr); 1063 for (;;); /* loop forever */ 1064 } 1065 1066 1067 static void 1068 calltozero(void) 1069 { 1070 panic("call to 0 from %p", __builtin_return_address(0)); 1071 } 1072 1073 static void 1074 parse_cmdline(char *cp) 1075 { 1076 int ourhowto = 0; 1077 char c; 1078 bool opt = false; 1079 for (; (c = *cp) != '\0'; cp++) { 1080 if (c == '-') { 1081 opt = true; 1082 continue; 1083 } 1084 if (c == ' ') { 1085 opt = false; 1086 continue; 1087 } 1088 if (opt) { 1089 switch (c) { 1090 case 'a': ourhowto |= RB_ASKNAME; break; 1091 case 'd': ourhowto |= AB_DEBUG; break; 1092 case 'q': ourhowto |= AB_QUIET; break; 1093 case 's': ourhowto |= RB_SINGLE; break; 1094 case 'v': ourhowto |= AB_VERBOSE; break; 1095 } 1096 continue; 1097 } 1098 strlcpy(root_string, cp, sizeof(root_string)); 1099 break; 1100 } 1101 if (ourhowto) { 1102 boothowto |= ourhowto; 1103 printf(" boothowto=%#x(%#x)", boothowto, ourhowto); 1104 } 1105 if (root_string[0]) 1106 printf(" root=%s", root_string); 1107 } 1108 1109 void 1110 initppc(vaddr_t startkernel, vaddr_t endkernel, 1111 void *a0, void *a1, char *a2, char *a3) 1112 { 1113 struct cpu_info * const ci = curcpu(); 1114 struct cpu_softc * const cpu = ci->ci_softc; 1115 1116 cn_tab = &e500_earlycons; 1117 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 1118 startkernel, endkernel, a0, a1, a2, a3); 1119 1120 if (a2[0] != '\0') 1121 printf(" consdev=<%s>", a2); 1122 if (a3[0] != '\0') { 1123 printf(" cmdline=<%s>", a3); 1124 parse_cmdline(a3); 1125 } 1126 1127 /* 1128 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 1129 * DOZE is ok. 1130 */ 1131 const register_t hid0 = mfspr(SPR_HID0); 1132 mtspr(SPR_HID0, 1133 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1134 #ifdef CADMUS 1135 /* 1136 * Need to cache this from cadmus since we need to unmap cadmus since 1137 * it falls in the middle of kernel address space. 1138 */ 1139 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1140 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1141 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1142 printf(" cadmus_pci=%#x", cadmus_pci); 1143 printf(" cadmus_csr=%#x", cadmus_csr); 1144 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1145 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1146 e500_sys_clk *= 2; 1147 } 1148 #endif 1149 #ifdef PIXIS 1150 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1151 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1152 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1153 #ifndef SYS_CLK 1154 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1155 #else 1156 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1157 #endif 1158 #endif 1159 printf(" porpllsr=0x%08x", 1160 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1161 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1162 1163 /* 1164 * Make sure arguments are page aligned. 1165 */ 1166 startkernel = trunc_page(startkernel); 1167 endkernel = round_page(endkernel); 1168 1169 /* 1170 * Initialize the bus space tag used to access the 85xx general 1171 * utility registers. It doesn't need to be extent protected. 1172 * We know the GUR is mapped via a TLB1 entry so we add a limited 1173 * mapiodev which allows mappings in GUR space. 1174 */ 1175 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1176 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1177 bus_space_init(&gur_bst, NULL, NULL, 0); 1178 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1179 cpu->cpu_bst = &gur_bst; 1180 cpu->cpu_le_bst = &gur_le_bst; 1181 cpu->cpu_bsh = gur_bsh; 1182 1183 /* 1184 * Attach the console early, really early. 1185 */ 1186 consinit(); 1187 1188 /* 1189 * Reset the PIC to a known state. 1190 */ 1191 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1192 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1193 ; 1194 #if 0 1195 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1196 #endif 1197 printf(" openpic-reset(ctpr=%u)", 1198 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1199 1200 /* 1201 * fill in with an absolute branch to a routine that will panic. 1202 */ 1203 *(volatile int *)0 = 0x48000002 | (int) calltozero; 1204 1205 /* 1206 * Get the cache sizes. 1207 */ 1208 cpu_probe_cache(); 1209 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1210 ci->ci_ci.dcache_size >> 10, 1211 ci->ci_ci.dcache_line_size, 1212 ci->ci_ci.icache_size >> 10, 1213 ci->ci_ci.icache_line_size); 1214 1215 /* 1216 * Now find out how much memory is attached 1217 */ 1218 pmemsize = memprobe(endkernel); 1219 cpu->cpu_highmem = pmemsize; 1220 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1221 1222 /* 1223 * Now we need cleanout the TLB of stuff that we don't need. 1224 */ 1225 e500_tlb_init(endkernel, pmemsize); 1226 printf(" e500_tlbinit(%#lx,%zuMB)", 1227 endkernel, (size_t) (pmemsize >> 20)); 1228 1229 /* 1230 * 1231 */ 1232 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1233 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1234 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1235 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1236 1237 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1238 1239 /* 1240 * Initialize the message buffer. 1241 */ 1242 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1243 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1244 1245 /* 1246 * Initialize exception vectors and interrupts 1247 */ 1248 exception_init(&e500_intrsw); 1249 1250 printf(" exception_init=%p", &e500_intrsw); 1251 1252 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1253 1254 /* 1255 * Set the page size. 1256 */ 1257 uvm_setpagesize(); 1258 1259 /* 1260 * Initialize the pmap. 1261 */ 1262 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1263 1264 /* 1265 * Let's take all the indirect calls via our stubs and patch 1266 * them to be direct calls. 1267 */ 1268 cpu_fixup_stubs(); 1269 1270 /* 1271 * As a debug measure we can change the TLB entry that maps all of 1272 * memory to one that encompasses the 64KB with the kernel vectors. 1273 * All other pages will be soft faulted into the TLB as needed. 1274 */ 1275 e500_tlb_minimize(endkernel); 1276 1277 /* 1278 * Set some more MD helpers 1279 */ 1280 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1281 cpu_md_ops.md_device_register = e500_device_register; 1282 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1283 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1284 #if NGPIO > 0 1285 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1286 #endif 1287 1288 printf(" initppc done!\n"); 1289 1290 /* 1291 * Look for the Book-E modules in the right place. 1292 */ 1293 module_machine = module_machine_booke; 1294 } 1295 1296 #ifdef MPC8548 1297 static const char * const mpc8548cds_extirq_names[] = { 1298 [0] = "pci inta", 1299 [1] = "pci intb", 1300 [2] = "pci intc", 1301 [3] = "pci intd", 1302 [4] = "irq4", 1303 [5] = "gige phy", 1304 [6] = "atm phy", 1305 [7] = "cpld", 1306 [8] = "irq8", 1307 [9] = "nvram", 1308 [10] = "debug", 1309 [11] = "pci2 inta", 1310 }; 1311 #endif 1312 1313 #ifndef MPC8548 1314 static const char * const mpc85xx_extirq_names[] = { 1315 [0] = "extirq 0", 1316 [1] = "extirq 1", 1317 [2] = "extirq 2", 1318 [3] = "extirq 3", 1319 [4] = "extirq 4", 1320 [5] = "extirq 5", 1321 [6] = "extirq 6", 1322 [7] = "extirq 7", 1323 [8] = "extirq 8", 1324 [9] = "extirq 9", 1325 [10] = "extirq 10", 1326 [11] = "extirq 11", 1327 }; 1328 #endif 1329 1330 static void 1331 mpc85xx_extirq_setup(void) 1332 { 1333 #ifdef MPC8548 1334 const char * const * names = mpc8548cds_extirq_names; 1335 const size_t n = __arraycount(mpc8548cds_extirq_names); 1336 #else 1337 const char * const * names = mpc85xx_extirq_names; 1338 const size_t n = __arraycount(mpc85xx_extirq_names); 1339 #endif 1340 prop_array_t extirqs = prop_array_create_with_capacity(n); 1341 for (u_int i = 0; i < n; i++) { 1342 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1343 prop_array_set(extirqs, i, ps); 1344 prop_object_release(ps); 1345 } 1346 board_info_add_object("external-irqs", extirqs); 1347 prop_object_release(extirqs); 1348 } 1349 1350 static void 1351 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1352 { 1353 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1354 KASSERT(pci_intmap != NULL); 1355 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1356 KASSERT(mask != NULL); 1357 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1358 prop_object_release(mask); 1359 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1360 KASSERT(pn_ist != NULL); 1361 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1362 KASSERT(pn_intr != NULL); 1363 prop_dictionary_t entry = prop_dictionary_create(); 1364 KASSERT(entry != NULL); 1365 prop_dictionary_set(entry, "interrupt", pn_intr); 1366 prop_dictionary_set(entry, "type", pn_ist); 1367 prop_dictionary_set(pci_intmap, "000000", entry); 1368 prop_object_release(pn_intr); 1369 prop_object_release(entry); 1370 va_list ap; 1371 va_start(ap, inta); 1372 u_int intrinc = __LOWEST_SET_BIT(intmask); 1373 for (u_int i = 0; i < intmask; i += intrinc) { 1374 char prop_name[12]; 1375 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1376 entry = prop_dictionary_create(); 1377 KASSERT(entry != NULL); 1378 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1379 KASSERT(pn_intr != NULL); 1380 prop_dictionary_set(entry, "interrupt", pn_intr); 1381 prop_dictionary_set(entry, "type", pn_ist); 1382 prop_dictionary_set(pci_intmap, prop_name, entry); 1383 prop_object_release(pn_intr); 1384 prop_object_release(entry); 1385 } 1386 va_end(ap); 1387 prop_object_release(pn_ist); 1388 board_info_add_object(name, pci_intmap); 1389 prop_object_release(pci_intmap); 1390 } 1391 1392 void 1393 cpu_startup(void) 1394 { 1395 struct cpu_info * const ci = curcpu(); 1396 const uint16_t svr = getsvr(); 1397 1398 powersave = 0; /* we can do it but turn it on by default */ 1399 1400 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1401 1402 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1403 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1404 uint32_t e500_ratio = E500_RATIO_GET(v); 1405 1406 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1407 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1408 1409 ci->ci_khz = (cpu_freq + 500) / 1000; 1410 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1411 1412 board_info_add_number("my-id", svr); 1413 board_info_add_bool("pq3"); 1414 board_info_add_number("mem-size", pmemsize); 1415 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1416 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1417 uint32_t l2banks = l2siz >> 16; 1418 #ifdef MPC85555 1419 if (svr == (MPC8555v1 >> 16)) { 1420 l2siz >>= 1; 1421 l2banks >>= 1; 1422 } 1423 #endif 1424 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1425 if (boot_page & BPTR_EN) { 1426 bool found = false; 1427 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1428 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1429 * const bp = (void *)boot_page; 1430 bp <= dp; dp--) { 1431 if (*dp == boot_page) { 1432 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1433 spinup_table_addr = 1434 roundup2(spinup_table_addr, 32); 1435 board_info_add_number("mp-boot-page", 1436 boot_page); 1437 board_info_add_number("mp-spin-up-table", 1438 spinup_table_addr); 1439 printf("Found MP boot page @ %#"PRIxPADDR". " 1440 "Spin-up table @ %#"PRIxPTR"\n", 1441 boot_page, spinup_table_addr); 1442 found = true; 1443 break; 1444 } 1445 } 1446 if (!found) { 1447 printf("Found MP boot page @ %#"PRIxPADDR 1448 " with missing U-boot signature!\n", boot_page); 1449 board_info_add_number("mp-spin-up-table", 0); 1450 } 1451 } 1452 board_info_add_number("l2-cache-size", l2siz); 1453 board_info_add_number("l2-cache-line-size", 32); 1454 board_info_add_number("l2-cache-banks", l2banks); 1455 board_info_add_number("l2-cache-ways", 8); 1456 1457 board_info_add_number("processor-frequency", cpu_freq); 1458 board_info_add_number("bus-frequency", ccb_freq); 1459 board_info_add_number("pci-frequency", e500_sys_clk); 1460 board_info_add_number("timebase-frequency", ccb_freq / 8); 1461 1462 #ifdef CADMUS 1463 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1464 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1465 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1466 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1467 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1468 #else 1469 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1470 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1471 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1472 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1473 #endif 1474 1475 uint64_t macstnaddr = 1476 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1477 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1478 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1479 1480 #if NPCI > 0 && defined(PCI_MEMBASE) 1481 pcimem_ex = extent_create("pcimem", 1482 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1483 NULL, 0, EX_WAITOK); 1484 #endif 1485 #if NPCI > 0 && defined(PCI_IOBASE) 1486 pciio_ex = extent_create("pciio", 1487 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1488 NULL, 0, EX_WAITOK); 1489 #endif 1490 mpc85xx_extirq_setup(); 1491 /* 1492 * PCI-Express virtual wire interrupts on combined with 1493 * External IRQ0/1/2/3. 1494 */ 1495 switch (svr) { 1496 #if defined(MPC8548) 1497 case SVR_MPC8548v1 >> 16: 1498 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1499 IST_LEVEL, 0, 1, 2, 3); 1500 break; 1501 #endif 1502 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \ 1503 || defined(P1025) || defined(P2020) || defined(P1023) 1504 case SVR_MPC8536v1 >> 16: 1505 case SVR_MPC8544v1 >> 16: 1506 case SVR_MPC8572v1 >> 16: 1507 case SVR_P1016v1 >> 16: 1508 case SVR_P1017v1 >> 16: 1509 case SVR_P1023v1 >> 16: 1510 case SVR_P2010v2 >> 16: 1511 case SVR_P2020v2 >> 16: 1512 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1513 8, 9, 10, 11); 1514 /* FALLTHROUGH */ 1515 case SVR_P1025v1 >> 16: 1516 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1517 4, 5, 6, 7); 1518 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1519 0, 1, 2, 3); 1520 break; 1521 #endif 1522 } 1523 switch (svr) { 1524 #if defined(MPC8536) 1525 case SVR_MPC8536v1 >> 16: 1526 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1527 1, 2, 3, 4); 1528 break; 1529 #endif 1530 #if defined(MPC8544) 1531 case SVR_MPC8544v1 >> 16: 1532 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1533 0, 1, 2, 3); 1534 break; 1535 #endif 1536 #if defined(MPC8548) 1537 case SVR_MPC8548v1 >> 16: 1538 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1539 0, 1, 2, 3); 1540 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1541 11, 1, 2, 3); 1542 break; 1543 #endif 1544 } 1545 } 1546
Indexes created Mon Sep 29 13:09:55 GMT 2025