machdep.c revision 1.43
1 /* $NetBSD: machdep.c,v 1.43 2018/01/27 10:07:41 flxd Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_altivec.h" 42 #include "opt_ddb.h" 43 #include "opt_mpc85xx.h" 44 #include "opt_multiprocessor.h" 45 #include "opt_pci.h" 46 #include "gpio.h" 47 #include "pci.h" 48 49 #define DDRC_PRIVATE 50 #define GLOBAL_PRIVATE 51 #define L2CACHE_PRIVATE 52 #define _POWERPC_BUS_DMA_PRIVATE 53 54 #include <sys/param.h> 55 #include <sys/cpu.h> 56 #include <sys/intr.h> 57 #include <sys/msgbuf.h> 58 #include <sys/tty.h> 59 #include <sys/kcore.h> 60 #include <sys/bitops.h> 61 #include <sys/bus.h> 62 #include <sys/extent.h> 63 #include <sys/reboot.h> 64 #include <sys/module.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <prop/proplib.h> 69 70 #include <dev/cons.h> 71 72 #include <dev/ic/comreg.h> 73 #include <dev/ic/comvar.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 #include <dev/mii/miivar.h> 78 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 struct uboot_bdinfo { 96 uint32_t bd_memstart; 97 uint32_t bd_memsize; 98 uint32_t bd_flashstart; 99 uint32_t bd_flashsize; 100 /*10*/ uint32_t bd_flashoffset; 101 uint32_t bd_sramstart; 102 uint32_t bd_sramsize; 103 uint32_t bd_immrbase; 104 /*20*/ uint32_t bd_bootflags; 105 uint32_t bd_ipaddr; 106 uint8_t bd_etheraddr[6]; 107 uint16_t bd_ethspeed; 108 /*30*/ uint32_t bd_intfreq; 109 uint32_t bd_cpufreq; 110 uint32_t bd_baudrate; 111 /*3c*/ uint8_t bd_etheraddr1[6]; 112 /*42*/ uint8_t bd_etheraddr2[6]; 113 /*48*/ uint8_t bd_etheraddr3[6]; 114 /*4e*/ uint16_t bd_pad; 115 }; 116 117 char root_string[16]; 118 119 /* 120 * booke kernels need to set module_machine to this for modules to work. 121 */ 122 char module_machine_booke[] = "powerpc-booke"; 123 124 void initppc(vaddr_t, vaddr_t, void *, void *, char *, char *); 125 126 #define MEMREGIONS 4 127 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 128 phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 129 static u_int nmemr; 130 131 #ifndef CONSFREQ 132 # define CONSFREQ -1 /* inherit from firmware */ 133 #endif 134 #ifndef CONSPEED 135 # define CONSPEED 115200 136 #endif 137 #ifndef CONMODE 138 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 139 #endif 140 #ifndef CONSADDR 141 # define CONSADDR DUART2_BASE 142 #endif 143 144 int comcnfreq = CONSFREQ; 145 int comcnspeed = CONSPEED; 146 tcflag_t comcnmode = CONMODE; 147 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 148 149 #if NPCI > 0 150 struct extent *pcimem_ex; 151 struct extent *pciio_ex; 152 #endif 153 154 struct powerpc_bus_space gur_bst = { 155 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 156 .pbs_offset = GUR_BASE, 157 .pbs_limit = GUR_SIZE, 158 }; 159 160 struct powerpc_bus_space gur_le_bst = { 161 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 162 .pbs_offset = GUR_BASE, 163 .pbs_limit = GUR_SIZE, 164 }; 165 166 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 167 168 #if defined(SYS_CLK) 169 static uint64_t e500_sys_clk = SYS_CLK; 170 #endif 171 #ifdef CADMUS 172 static uint8_t cadmus_pci; 173 static uint8_t cadmus_csr; 174 #ifndef SYS_CLK 175 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 176 #endif 177 #elif defined(PIXIS) 178 static const uint32_t pixis_spd_map[8] = { 179 [PX_SPD_33MHZ] = 33333333, 180 [PX_SPD_40MHZ] = 40000000, 181 [PX_SPD_50MHZ] = 50000000, 182 [PX_SPD_66MHZ] = 66666666, 183 [PX_SPD_83MHZ] = 83333333, 184 [PX_SPD_100MHZ] = 100000000, 185 [PX_SPD_133MHZ] = 133333333, 186 [PX_SPD_166MHZ] = 166666667, 187 }; 188 static uint8_t pixis_spd; 189 #ifndef SYS_CLK 190 static uint64_t e500_sys_clk; 191 #endif 192 #elif !defined(SYS_CLK) 193 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 194 #endif 195 196 static int e500_cngetc(dev_t); 197 static void e500_cnputc(dev_t, int); 198 199 static struct consdev e500_earlycons = { 200 .cn_getc = e500_cngetc, 201 .cn_putc = e500_cnputc, 202 .cn_pollc = nullcnpollc, 203 }; 204 205 /* 206 * List of port-specific devices to attach to the processor local bus. 207 */ 208 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 209 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 210 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 211 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 212 #if defined(MPC8572) || defined(P2020) || defined(P1025) \ 213 || defined(P1023) 214 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 215 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 216 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 217 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 218 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 219 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 220 #endif 221 { "wdog" }, /* not a real device */ 222 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 223 1, { ISOURCE_DUART }, 224 1 + ilog2(DEVDISR_DUART) }, 225 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 226 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 227 1 + ilog2(DEVDISR_TSEC1), 228 { 0xffff, SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 229 #if defined(P1025) 230 { "mdio", ETSEC1_BASE, ETSEC_SIZE, 1, 231 0, { }, 232 1 + ilog2(DEVDISR_TSEC1), 233 { SVR_P1025v1 >> 16 } }, 234 { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1, 235 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 236 1 + ilog2(DEVDISR_TSEC1), 237 { SVR_P1025v1 >> 16 } }, 238 #if 0 239 { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1, 240 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX, 241 ISOURCE_ETSEC1_G1_ERR }, 242 1 + ilog2(DEVDISR_TSEC1), 243 { SVR_P1025v1 >> 16 } }, 244 #endif 245 #endif 246 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \ 247 || defined(P2020) 248 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 249 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 250 1 + ilog2(DEVDISR_TSEC2), 251 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 252 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 253 SVR_P1025v1 >> 16 } }, 254 #endif 255 #if defined(P1025) 256 { "mdio", ETSEC2_BASE, ETSEC_SIZE, 2, 257 0, { }, 258 1 + ilog2(DEVDISR_TSEC2), 259 { SVR_P1025v1 >> 16 } }, 260 { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2, 261 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 262 1 + ilog2(DEVDISR_TSEC2), 263 { SVR_P1025v1 >> 16 } }, 264 #if 0 265 { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5, 266 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX, 267 ISOURCE_ETSEC2_G1_ERR }, 268 1 + ilog2(DEVDISR_TSEC2), 269 { SVR_P1025v1 >> 16 } }, 270 #endif 271 #endif 272 #if defined(MPC8544) || defined(MPC8536) 273 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 274 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 275 1 + ilog2(DEVDISR_TSEC3), 276 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 277 #endif 278 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 279 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 280 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 281 1 + ilog2(DEVDISR_TSEC3), 282 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 283 SVR_P2020v2 >> 16 } }, 284 #endif 285 #if defined(P1025) 286 { "mdio", ETSEC3_BASE, ETSEC_SIZE, 3, 287 0, { }, 288 1 + ilog2(DEVDISR_TSEC3), 289 { SVR_P1025v1 >> 16 } }, 290 { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3, 291 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 292 1 + ilog2(DEVDISR_TSEC3), 293 { SVR_P1025v1 >> 16 } }, 294 #if 0 295 { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3, 296 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX, 297 ISOURCE_ETSEC3_G1_ERR }, 298 1 + ilog2(DEVDISR_TSEC3), 299 { SVR_P1025v1 >> 16 } }, 300 #endif 301 #endif 302 #if defined(MPC8548) || defined(MPC8572) 303 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 304 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 305 1 + ilog2(DEVDISR_TSEC4), 306 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 307 #endif 308 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 309 1, { ISOURCE_I2C }, 310 1 + ilog2(DEVDISR_I2C) }, 311 /* MPC8572 doesn't have any GPIO */ 312 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 313 1, { ISOURCE_GPIO }, 314 0, 315 { 0xffff, SVR_MPC8572v1 >> 16 } }, 316 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 317 1, { ISOURCE_DDR }, 318 1 + ilog2(DEVDISR_DDR_15), 319 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 320 #if defined(MPC8536) 321 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 322 1, { ISOURCE_DDR }, 323 1 + ilog2(DEVDISR_DDR_16), 324 { SVR_MPC8536v1 >> 16 } }, 325 #endif 326 #if defined(MPC8572) 327 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 328 1, { ISOURCE_DDR }, 329 1 + ilog2(DEVDISR_DDR_15), 330 { SVR_MPC8572v1 >> 16 } }, 331 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 332 1, { ISOURCE_DDR }, 333 1 + ilog2(DEVDISR_DDR2_14), 334 { SVR_MPC8572v1 >> 16 } }, 335 #endif 336 { "lbc", LBC_BASE, LBC_SIZE, 0, 337 1, { ISOURCE_LBC }, 338 1 + ilog2(DEVDISR_LBC) }, 339 #if defined(MPC8544) || defined(MPC8536) 340 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 341 1, { ISOURCE_PCIEX }, 342 1 + ilog2(DEVDISR_PCIE), 343 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 344 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 345 1, { ISOURCE_PCIEX2 }, 346 1 + ilog2(DEVDISR_PCIE2), 347 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 348 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 349 1, { ISOURCE_PCIEX3 }, 350 1 + ilog2(DEVDISR_PCIE3), 351 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 352 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 353 1, { ISOURCE_PCI1 }, 354 1 + ilog2(DEVDISR_PCI1), 355 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 356 #endif 357 #ifdef MPC8548 358 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 359 1, { ISOURCE_PCIEX }, 360 1 + ilog2(DEVDISR_PCIE), 361 { SVR_MPC8548v1 >> 16 }, }, 362 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 363 1, { ISOURCE_PCI1 }, 364 1 + ilog2(DEVDISR_PCI1), 365 { SVR_MPC8548v1 >> 16 }, }, 366 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 367 1, { ISOURCE_PCI2 }, 368 1 + ilog2(DEVDISR_PCI2), 369 { SVR_MPC8548v1 >> 16 }, }, 370 #endif 371 #if defined(MPC8572) || defined(P1025) || defined(P2020) \ 372 || defined(P1023) 373 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 374 1, { ISOURCE_PCIEX }, 375 1 + ilog2(DEVDISR_PCIE), 376 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 377 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 378 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 379 1, { ISOURCE_PCIEX2 }, 380 1 + ilog2(DEVDISR_PCIE2), 381 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 382 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 383 #endif 384 #if defined(MPC8572) || defined(P2020) || defined(_P1023) 385 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 386 1, { ISOURCE_PCIEX3_MPC8572 }, 387 1 + ilog2(DEVDISR_PCIE3), 388 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 389 SVR_P1023v1 >> 16 } }, 390 #endif 391 #if defined(MPC8536) || defined(P1025) || defined(P2020) \ 392 || defined(P1023) 393 { "ehci", USB1_BASE, USB_SIZE, 1, 394 1, { ISOURCE_USB1 }, 395 1 + ilog2(DEVDISR_USB1), 396 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16, 397 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 398 #endif 399 #ifdef MPC8536 400 { "ehci", USB2_BASE, USB_SIZE, 2, 401 1, { ISOURCE_USB2 }, 402 1 + ilog2(DEVDISR_USB2), 403 { SVR_MPC8536v1 >> 16 }, }, 404 { "ehci", USB3_BASE, USB_SIZE, 3, 405 1, { ISOURCE_USB3 }, 406 1 + ilog2(DEVDISR_USB3), 407 { SVR_MPC8536v1 >> 16 }, }, 408 { "sata", SATA1_BASE, SATA_SIZE, 1, 409 1, { ISOURCE_SATA1 }, 410 1 + ilog2(DEVDISR_SATA1), 411 { SVR_MPC8536v1 >> 16 }, }, 412 { "sata", SATA2_BASE, SATA_SIZE, 2, 413 1, { ISOURCE_SATA2 }, 414 1 + ilog2(DEVDISR_SATA2), 415 { SVR_MPC8536v1 >> 16 }, }, 416 { "spi", SPI_BASE, SPI_SIZE, 0, 417 1, { ISOURCE_SPI }, 418 1 + ilog2(DEVDISR_SPI_15), 419 { SVR_MPC8536v1 >> 16 }, }, 420 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 421 1, { ISOURCE_ESDHC }, 422 1 + ilog2(DEVDISR_ESDHC_12), 423 { SVR_MPC8536v1 >> 16 }, }, 424 #endif 425 #if defined(P1025) || defined(P2020) || defined(P1023) 426 { "spi", SPI_BASE, SPI_SIZE, 0, 427 1, { ISOURCE_SPI }, 428 1 + ilog2(DEVDISR_SPI_28), 429 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16, 430 SVR_P1023v1 >> 16 }, }, 431 #endif 432 #if defined(P1025) || defined(P2020) 433 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 434 1, { ISOURCE_ESDHC }, 435 1 + ilog2(DEVDISR_ESDHC_10), 436 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 437 #endif 438 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 439 { NULL } 440 }; 441 442 static int 443 e500_cngetc(dev_t dv) 444 { 445 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 446 447 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 448 return -1; 449 450 return com0addr[com_data] & 0xff; 451 } 452 453 static void 454 e500_cnputc(dev_t dv, int c) 455 { 456 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 457 int timo = 150000; 458 459 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 460 ; 461 462 com0addr[com_data] = c; 463 __asm("mbar"); 464 465 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 466 ; 467 } 468 469 static void * 470 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 471 { 472 if (prefetchable) 473 return NULL; 474 if (pa < gur_bst.pbs_offset) 475 return NULL; 476 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 477 return NULL; 478 return (void *)pa; 479 } 480 481 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 482 483 static void 484 e500_cpu_reset(void) 485 { 486 __asm volatile("sync"); 487 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 488 __asm volatile("msync;isync"); 489 } 490 491 static psize_t 492 memprobe(vaddr_t endkernel) 493 { 494 phys_ram_seg_t *mr; 495 paddr_t boot_page = cpu_read_4(GUR_BPTR); 496 printf(" bptr=%"PRIxPADDR, boot_page); 497 if (boot_page & BPTR_EN) { 498 /* 499 * shift it to an address 500 */ 501 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 502 } else { 503 boot_page = ~(paddr_t)0; 504 } 505 506 /* 507 * First we need to find out how much physical memory we have. 508 * We could let our bootloader tell us, but it's almost as easy 509 * to ask the DDR memory controller. 510 */ 511 mr = physmemr; 512 for (u_int i = 0; i < 4; i++) { 513 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 514 if (v & CS_CONFIG_EN) { 515 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 516 if (v == 0) 517 continue; 518 mr->start = BNDS_SA_GET(v); 519 mr->size = BNDS_SIZE_GET(v); 520 #ifdef MEMSIZE 521 if (mr->start >= MEMSIZE) 522 continue; 523 if (mr->start + mr->size > MEMSIZE) 524 mr->size = MEMSIZE - mr->start; 525 #endif 526 #if 0 527 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 528 mr - physmemr, mr->size, mr->start); 529 #endif 530 mr++; 531 } 532 } 533 534 if (mr == physmemr) 535 panic("no memory configured!"); 536 537 /* 538 * Sort memory regions from low to high and coalesce adjacent regions 539 */ 540 u_int cnt = mr - physmemr; 541 if (cnt > 1) { 542 for (u_int i = 0; i < cnt - 1; i++) { 543 for (u_int j = i + 1; j < cnt; j++) { 544 if (physmemr[j].start < physmemr[i].start) { 545 phys_ram_seg_t tmp = physmemr[i]; 546 physmemr[i] = physmemr[j]; 547 physmemr[j] = tmp; 548 } 549 } 550 } 551 mr = physmemr; 552 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 553 if (mr->start + mr->size == mr[1].start) { 554 mr->size += mr[1].size; 555 for (u_int j = 1; i + j + 1 < cnt; j++) 556 mr[j] = mr[j+1]; 557 cnt--; 558 } 559 } 560 } else if (cnt == 0) { 561 panic("%s: no memory found", __func__); 562 } 563 564 /* 565 * Copy physical memory to available memory. 566 */ 567 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 568 569 /* 570 * Adjust available memory to skip kernel at start of memory. 571 */ 572 availmemr[0].size -= endkernel - availmemr[0].start; 573 availmemr[0].start = endkernel; 574 575 mr = availmemr; 576 for (u_int i = 0; i < cnt; i++, mr++) { 577 /* 578 * U-boot reserves a boot-page on multi-core chips. 579 * We need to make sure that we never disturb it. 580 */ 581 const paddr_t mr_end = mr->start + mr->size; 582 if (mr_end > boot_page && boot_page >= mr->start) { 583 /* 584 * Normally u-boot will put in at the end 585 * of memory. But in case it doesn't, deal 586 * with all possibilities. 587 */ 588 if (boot_page + PAGE_SIZE == mr_end) { 589 mr->size -= PAGE_SIZE; 590 } else if (boot_page == mr->start) { 591 mr->start += PAGE_SIZE; 592 mr->size -= PAGE_SIZE; 593 } else { 594 mr->size = boot_page - mr->start; 595 mr++; 596 for (u_int j = cnt; j > i + 1; j--) { 597 availmemr[j] = availmemr[j-1]; 598 } 599 cnt++; 600 mr->start = boot_page + PAGE_SIZE; 601 mr->size = mr_end - mr->start; 602 } 603 break; 604 } 605 } 606 607 /* 608 * Steal pages at the end of memory for the kernel message buffer. 609 */ 610 mr = availmemr + cnt - 1; 611 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 612 mr->size -= round_page(MSGBUFSIZE); 613 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 614 615 /* 616 * Calculate physmem. 617 */ 618 for (u_int i = 0; i < cnt; i++) 619 physmem += atop(physmemr[i].size); 620 621 nmemr = cnt; 622 return physmemr[cnt-1].start + physmemr[cnt-1].size; 623 } 624 625 void 626 consinit(void) 627 { 628 static bool attached = false; 629 630 if (attached) 631 return; 632 attached = true; 633 634 if (comcnfreq == -1) { 635 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 636 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 637 comcnfreq = e500_sys_clk * plat_ratio; 638 printf(" comcnfreq=%u", comcnfreq); 639 } 640 641 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 642 COM_TYPE_NORMAL, comcnmode); 643 } 644 645 void 646 cpu_probe_cache(void) 647 { 648 struct cpu_info * const ci = curcpu(); 649 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 650 const int dcache_assoc = L1CFG_CNWAY_GET(l1cfg0); 651 652 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 653 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 654 655 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 656 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 657 658 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 659 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 660 } else { 661 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 662 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 663 } 664 665 /* 666 * Possibly recolor. 667 */ 668 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / dcache_assoc)); 669 670 #ifdef DEBUG 671 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 672 if ((L1CSR_CE & l1csr0) == 0) 673 printf(" DC=off"); 674 675 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 676 if ((L1CSR_CE & l1csr1) == 0) 677 printf(" IC=off"); 678 #endif 679 } 680 681 static uint16_t 682 getsvr(void) 683 { 684 uint16_t svr = mfspr(SPR_SVR) >> 16; 685 686 svr &= ~0x8; /* clear security bit */ 687 switch (svr) { 688 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 689 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 690 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 691 case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16; 692 case SVR_P1017v1 >> 16: return SVR_P1023v1 >> 16; 693 default: return svr; 694 } 695 } 696 697 static const char * 698 socname(uint32_t svr) 699 { 700 svr &= ~0x80000; /* clear security bit */ 701 switch (svr >> 8) { 702 case SVR_MPC8533 >> 8: return "MPC8533"; 703 case SVR_MPC8536v1 >> 8: return "MPC8536"; 704 case SVR_MPC8541v1 >> 8: return "MPC8541"; 705 case SVR_MPC8543v2 >> 8: return "MPC8543"; 706 case SVR_MPC8544v1 >> 8: return "MPC8544"; 707 case SVR_MPC8545v2 >> 8: return "MPC8545"; 708 case SVR_MPC8547v2 >> 8: return "MPC8547"; 709 case SVR_MPC8548v2 >> 8: return "MPC8548"; 710 case SVR_MPC8555v1 >> 8: return "MPC8555"; 711 case SVR_MPC8568v1 >> 8: return "MPC8568"; 712 case SVR_MPC8567v1 >> 8: return "MPC8567"; 713 case SVR_MPC8572v1 >> 8: return "MPC8572"; 714 case SVR_P2020v2 >> 8: return "P2020"; 715 case SVR_P2010v2 >> 8: return "P2010"; 716 case SVR_P1016v1 >> 8: return "P1016"; 717 case SVR_P1017v1 >> 8: return "P1017"; 718 case SVR_P1023v1 >> 8: return "P1023"; 719 case SVR_P1025v1 >> 8: return "P1025"; 720 default: 721 panic("%s: unknown SVR %#x", __func__, svr); 722 } 723 } 724 725 static void 726 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 727 { 728 static const char units[16] = "KKKKKMMMMMGGGGGT"; 729 730 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 731 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 732 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 733 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 734 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 735 736 aprint_normal_dev(self, "%s:", name); 737 738 aprint_normal(" %u", nentries); 739 if (TLBCFG_AVAIL_P(tlbcfg)) { 740 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 741 minsize, maxsize, units[maxsize_log4k]); 742 } else { 743 aprint_normal(" fixed-size (%uKB)", minsize); 744 } 745 if (assoc == 0 || assoc == nentries) 746 aprint_normal(" fully"); 747 else 748 aprint_normal(" %u-way set", assoc); 749 aprint_normal(" associative entries\n"); 750 } 751 752 static void 753 cpu_print_info(struct cpu_info *ci) 754 { 755 uint64_t freq = board_info_get_number("processor-frequency"); 756 device_t self = ci->ci_dev; 757 758 char freqbuf[10]; 759 if (freq >= 999500000) { 760 const uint32_t freq32 = (freq + 500000) / 10000000; 761 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 762 freq32 / 100, freq32 % 100); 763 } else { 764 const uint32_t freq32 = (freq + 500000) / 1000000; 765 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 766 } 767 768 const uint32_t pvr = mfpvr(); 769 const uint32_t svr = mfspr(SPR_SVR); 770 const uint32_t pir = mfspr(SPR_PIR); 771 772 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 773 "ID %u%s\n", 774 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 775 (svr >> 4) & 15, svr & 15, 776 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 777 (pvr >> 4) & 15, pvr & 15, 778 pir, (pir == 0 ? " (Primary)" : "")); 779 780 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 781 aprint_normal_dev(self, 782 "%uKB/%uB %u-way L1 %s cache\n", 783 L1CFG_CSIZE_GET(l1cfg0) >> 10, 784 32 << L1CFG_CBSIZE_GET(l1cfg0), 785 L1CFG_CNWAY_GET(l1cfg0), 786 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 787 ? "data" : "unified"); 788 789 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 790 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 791 aprint_normal_dev(self, 792 "%uKB/%uB %u-way L1 %s cache\n", 793 L1CFG_CSIZE_GET(l1cfg1) >> 10, 794 32 << L1CFG_CBSIZE_GET(l1cfg1), 795 L1CFG_CNWAY_GET(l1cfg1), 796 "instruction"); 797 } 798 799 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 800 aprint_normal_dev(self, 801 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 802 MMUCFG_NTLBS_GET(mmucfg) + 1, 803 MMUCFG_NPIDS_GET(mmucfg), 804 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 805 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 806 807 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 808 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 809 } 810 811 #ifdef MULTIPROCESSOR 812 static void 813 e500_cpu_spinup(device_t self, struct cpu_info *ci) 814 { 815 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 816 struct pglist splist; 817 818 if (spinup_table_addr == 0) { 819 aprint_error_dev(self, "hatch failed (no spin-up table)"); 820 return; 821 } 822 823 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 824 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 825 const size_t id = cpu_index(ci); 826 kcpuset_t * const hatchlings = cpuset_info.cpus_hatched; 827 828 if (h->hatch_sp == 0) { 829 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 830 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 831 if (error) { 832 aprint_error_dev(self, 833 "unable to allocate hatch stack\n"); 834 return; 835 } 836 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 837 + PAGE_SIZE - CALLFRAMELEN; 838 } 839 840 841 for (size_t i = 1; e[i].entry_pir != 0; i++) { 842 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 843 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 844 if (e[i].entry_pir == ci->ci_cpuid) { 845 846 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 847 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 848 ci->ci_curpm = pmap_kernel(); 849 ci->ci_lasttb = cpu_info[0].ci_lasttb; 850 ci->ci_data.cpu_cc_freq = 851 cpu_info[0].ci_data.cpu_cc_freq; 852 853 h->hatch_self = self; 854 h->hatch_ci = ci; 855 h->hatch_running = -1; 856 h->hatch_pir = e[i].entry_pir; 857 h->hatch_hid0 = mfspr(SPR_HID0); 858 u_int tlbidx; 859 e500_tlb_lookup_xtlb(0, &tlbidx); 860 h->hatch_tlbidx = tlbidx; 861 KASSERT(h->hatch_sp != 0); 862 /* 863 * Get new timebase. We don't want to deal with 864 * timebase crossing a 32-bit boundary so make sure 865 * that we have enough headroom to do the timebase 866 * synchronization. 867 */ 868 #define TBSYNC_SLOP 2000 869 uint32_t tbl; 870 uint32_t tbu; 871 do { 872 tbu = mfspr(SPR_RTBU); 873 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 874 } while (tbl < TBSYNC_SLOP); 875 876 h->hatch_tbu = tbu; 877 h->hatch_tbl = tbl; 878 __asm("sync;isync"); 879 dcache_wbinv((vaddr_t)h, sizeof(*h)); 880 881 /* 882 * And here we go... 883 */ 884 e[i].entry_addr_lower = 885 (uint32_t)e500_spinup_trampoline; 886 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 887 __asm __volatile("sync;isync"); 888 __insn_barrier(); 889 890 for (u_int timo = 0; timo++ < 10000; ) { 891 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 892 if (e[i].entry_addr_lower == 3) { 893 #if 0 894 printf( 895 "%s: cpu%u started in %u spins\n", 896 __func__, cpu_index(ci), timo); 897 #endif 898 break; 899 } 900 } 901 for (u_int timo = 0; timo++ < 10000; ) { 902 dcache_inv((vaddr_t)h, sizeof(*h)); 903 if (h->hatch_running == 0) { 904 #if 0 905 printf( 906 "%s: cpu%u cracked in %u spins: (running=%d)\n", 907 __func__, cpu_index(ci), 908 timo, h->hatch_running); 909 #endif 910 break; 911 } 912 } 913 if (h->hatch_running == -1) { 914 aprint_error_dev(self, 915 "hatch failed (timeout): running=%d" 916 ", entry=%#x\n", 917 h->hatch_running, e[i].entry_addr_lower); 918 goto out; 919 } 920 921 /* 922 * First then we do is to synchronize timebases. 923 * TBSYNC_SLOP*16 should be more than enough 924 * instructions. 925 */ 926 while (tbl != mftbl()) 927 continue; 928 h->hatch_running = 1; 929 dcache_wbinv((vaddr_t)h, sizeof(*h)); 930 __asm("sync;isync"); 931 __insn_barrier(); 932 printf("%s: cpu%u set to running\n", 933 __func__, cpu_index(ci)); 934 935 for (u_int timo = 10000; timo-- > 0; ) { 936 dcache_inv((vaddr_t)h, sizeof(*h)); 937 if (h->hatch_running > 1) 938 break; 939 } 940 if (h->hatch_running == 1) { 941 printf( 942 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 943 __func__, 944 ((int64_t)tbu << 32) + tbl, 945 (int64_t) 946 (((uint64_t)h->hatch_tbu << 32) 947 + (uint64_t)h->hatch_tbl), 948 h->hatch_running); 949 goto out; 950 } 951 printf( 952 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 953 __func__, 954 (int64_t) 955 (((uint64_t)h->hatch_tbu << 32) 956 + (uint64_t)h->hatch_tbl), 957 h->hatch_running); 958 /* 959 * Now we wait for the hatching to complete. 30ms 960 * should be long enough. 961 */ 962 for (u_int timo = 30000; timo-- > 0; ) { 963 if (kcpuset_isset(hatchlings, id)) { 964 aprint_normal_dev(self, 965 "hatch successful (%u spins, " 966 "timebase adjusted by %"PRId64")\n", 967 30000 - timo, 968 (int64_t) 969 (((uint64_t)h->hatch_tbu << 32) 970 + (uint64_t)h->hatch_tbl)); 971 goto out; 972 } 973 DELAY(1); 974 } 975 976 aprint_error_dev(self, 977 "hatch failed (timeout): running=%u\n", 978 h->hatch_running); 979 goto out; 980 } 981 } 982 983 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 984 ci->ci_cpuid); 985 out: 986 if (h->hatch_sp == 0) 987 uvm_pglistfree(&splist); 988 } 989 #endif 990 991 void 992 e500_cpu_hatch(struct cpu_info *ci) 993 { 994 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 995 996 /* 997 * Make sure interrupts are blocked. 998 */ 999 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1000 1001 /* Set the MAS4 defaults */ 1002 mtspr(SPR_MAS4, MAS4_TSIZED_4KB | MAS4_MD); 1003 tlb_invalidate_all(); 1004 1005 intr_cpu_hatch(ci); 1006 1007 cpu_probe_cache(); 1008 cpu_print_info(ci); 1009 1010 /* 1011 */ 1012 } 1013 1014 static void 1015 e500_cpu_attach(device_t self, u_int instance) 1016 { 1017 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 1018 1019 if (instance > 1) { 1020 #if defined(MULTIPROCESSOR) 1021 ci->ci_idepth = -1; 1022 self->dv_private = ci; 1023 1024 ci->ci_cpuid = instance - (instance > 0); 1025 ci->ci_dev = self; 1026 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 1027 1028 mi_cpu_attach(ci); 1029 1030 intr_cpu_attach(ci); 1031 cpu_evcnt_attach(ci); 1032 1033 e500_cpu_spinup(self, ci); 1034 return; 1035 #else 1036 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 1037 return; 1038 #endif 1039 } 1040 1041 self->dv_private = ci; 1042 1043 ci->ci_cpuid = instance - (instance > 0); 1044 ci->ci_dev = self; 1045 1046 intr_cpu_attach(ci); 1047 cpu_evcnt_attach(ci); 1048 1049 KASSERT(ci == curcpu()); 1050 intr_cpu_hatch(ci); 1051 1052 cpu_print_info(ci); 1053 } 1054 1055 void 1056 e500_ipi_halt(void) 1057 { 1058 #ifdef MULTIPROCESSOR 1059 struct cpuset_info * const csi = &cpuset_info; 1060 const cpuid_t index = cpu_index(curcpu()); 1061 1062 printf("cpu%lu: shutting down\n", index); 1063 kcpuset_set(csi->cpus_halted, index); 1064 #endif 1065 register_t msr, hid0; 1066 1067 msr = wrtee(0); 1068 1069 hid0 = mfspr(SPR_HID0); 1070 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 1071 mtspr(SPR_HID0, hid0); 1072 1073 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 1074 mtmsr(msr); 1075 for (;;); /* loop forever */ 1076 } 1077 1078 1079 static void 1080 calltozero(void) 1081 { 1082 panic("call to 0 from %p", __builtin_return_address(0)); 1083 } 1084 1085 #if !defined(ROUTERBOOT) 1086 static void 1087 parse_cmdline(char *cp) 1088 { 1089 int ourhowto = 0; 1090 char c; 1091 bool opt = false; 1092 for (; (c = *cp) != '\0'; cp++) { 1093 if (c == '-') { 1094 opt = true; 1095 continue; 1096 } 1097 if (c == ' ') { 1098 opt = false; 1099 continue; 1100 } 1101 if (opt) { 1102 switch (c) { 1103 case 'a': ourhowto |= RB_ASKNAME; break; 1104 case 'd': ourhowto |= AB_DEBUG; break; 1105 case 'q': ourhowto |= AB_QUIET; break; 1106 case 's': ourhowto |= RB_SINGLE; break; 1107 case 'v': ourhowto |= AB_VERBOSE; break; 1108 } 1109 continue; 1110 } 1111 strlcpy(root_string, cp, sizeof(root_string)); 1112 break; 1113 } 1114 if (ourhowto) { 1115 boothowto |= ourhowto; 1116 printf(" boothowto=%#x(%#x)", boothowto, ourhowto); 1117 } 1118 if (root_string[0]) 1119 printf(" root=%s", root_string); 1120 } 1121 #endif /* !ROUTERBOOT */ 1122 1123 void 1124 initppc(vaddr_t startkernel, vaddr_t endkernel, 1125 void *a0, void *a1, char *a2, char *a3) 1126 { 1127 struct cpu_info * const ci = curcpu(); 1128 struct cpu_softc * const cpu = ci->ci_softc; 1129 1130 cn_tab = &e500_earlycons; 1131 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 1132 startkernel, endkernel, a0, a1, a2, a3); 1133 1134 #if !defined(ROUTERBOOT) 1135 if (a2[0] != '\0') 1136 printf(" consdev=<%s>", a2); 1137 if (a3[0] != '\0') { 1138 printf(" cmdline=<%s>", a3); 1139 parse_cmdline(a3); 1140 } 1141 #endif /* !ROUTERBOOT */ 1142 1143 /* 1144 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 1145 * DOZE is ok. 1146 */ 1147 const register_t hid0 = mfspr(SPR_HID0); 1148 mtspr(SPR_HID0, 1149 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1150 #ifdef CADMUS 1151 /* 1152 * Need to cache this from cadmus since we need to unmap cadmus since 1153 * it falls in the middle of kernel address space. 1154 */ 1155 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1156 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1157 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1158 printf(" cadmus_pci=%#x", cadmus_pci); 1159 printf(" cadmus_csr=%#x", cadmus_csr); 1160 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1161 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1162 e500_sys_clk *= 2; 1163 } 1164 #endif 1165 #ifdef PIXIS 1166 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1167 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1168 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1169 #ifndef SYS_CLK 1170 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1171 #else 1172 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1173 #endif 1174 #endif 1175 printf(" porpllsr=0x%08x", 1176 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1177 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1178 1179 /* 1180 * Make sure arguments are page aligned. 1181 */ 1182 startkernel = trunc_page(startkernel); 1183 endkernel = round_page(endkernel); 1184 1185 /* 1186 * Initialize the bus space tag used to access the 85xx general 1187 * utility registers. It doesn't need to be extent protected. 1188 * We know the GUR is mapped via a TLB1 entry so we add a limited 1189 * mapiodev which allows mappings in GUR space. 1190 */ 1191 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1192 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1193 bus_space_init(&gur_bst, NULL, NULL, 0); 1194 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1195 cpu->cpu_bst = &gur_bst; 1196 cpu->cpu_le_bst = &gur_le_bst; 1197 cpu->cpu_bsh = gur_bsh; 1198 1199 /* 1200 * Attach the console early, really early. 1201 */ 1202 consinit(); 1203 1204 /* 1205 * Reset the PIC to a known state. 1206 */ 1207 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1208 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1209 ; 1210 #if 0 1211 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1212 #endif 1213 printf(" openpic-reset(ctpr=%u)", 1214 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1215 1216 /* 1217 * fill in with an absolute branch to a routine that will panic. 1218 */ 1219 *(volatile int *)0 = 0x48000002 | (int) calltozero; 1220 1221 /* 1222 * Get the cache sizes. 1223 */ 1224 cpu_probe_cache(); 1225 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1226 ci->ci_ci.dcache_size >> 10, 1227 ci->ci_ci.dcache_line_size, 1228 ci->ci_ci.icache_size >> 10, 1229 ci->ci_ci.icache_line_size); 1230 1231 /* 1232 * Now find out how much memory is attached 1233 */ 1234 pmemsize = memprobe(endkernel); 1235 cpu->cpu_highmem = pmemsize; 1236 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1237 1238 /* 1239 * Now we need cleanout the TLB of stuff that we don't need. 1240 */ 1241 e500_tlb_init(endkernel, pmemsize); 1242 printf(" e500_tlbinit(%#lx,%zuMB)", 1243 endkernel, (size_t) (pmemsize >> 20)); 1244 1245 /* 1246 * 1247 */ 1248 printf(" hid0=%#lx/%#jx", hid0, (uintmax_t)mfspr(SPR_HID0)); 1249 printf(" hid1=%#jx", (uintmax_t)mfspr(SPR_HID1)); 1250 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1251 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1252 1253 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1254 1255 /* 1256 * Initialize the message buffer. 1257 */ 1258 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1259 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1260 1261 /* 1262 * Initialize exception vectors and interrupts 1263 */ 1264 exception_init(&e500_intrsw); 1265 1266 printf(" exception_init=%p", &e500_intrsw); 1267 1268 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1269 1270 uvm_md_init(); 1271 1272 /* 1273 * Initialize the pmap. 1274 */ 1275 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1276 1277 /* 1278 * Let's take all the indirect calls via our stubs and patch 1279 * them to be direct calls. 1280 */ 1281 cpu_fixup_stubs(); 1282 1283 /* 1284 * As a debug measure we can change the TLB entry that maps all of 1285 * memory to one that encompasses the 64KB with the kernel vectors. 1286 * All other pages will be soft faulted into the TLB as needed. 1287 */ 1288 e500_tlb_minimize(endkernel); 1289 1290 /* 1291 * Set some more MD helpers 1292 */ 1293 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1294 cpu_md_ops.md_device_register = e500_device_register; 1295 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1296 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1297 #if NGPIO > 0 1298 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1299 #endif 1300 1301 printf(" initppc done!\n"); 1302 1303 /* 1304 * Look for the Book-E modules in the right place. 1305 */ 1306 module_machine = module_machine_booke; 1307 } 1308 1309 #ifdef MPC8548 1310 static const char * const mpc8548cds_extirq_names[] = { 1311 [0] = "pci inta", 1312 [1] = "pci intb", 1313 [2] = "pci intc", 1314 [3] = "pci intd", 1315 [4] = "irq4", 1316 [5] = "gige phy", 1317 [6] = "atm phy", 1318 [7] = "cpld", 1319 [8] = "irq8", 1320 [9] = "nvram", 1321 [10] = "debug", 1322 [11] = "pci2 inta", 1323 }; 1324 #endif 1325 1326 #ifndef MPC8548 1327 static const char * const mpc85xx_extirq_names[] = { 1328 [0] = "extirq 0", 1329 [1] = "extirq 1", 1330 [2] = "extirq 2", 1331 [3] = "extirq 3", 1332 [4] = "extirq 4", 1333 [5] = "extirq 5", 1334 [6] = "extirq 6", 1335 [7] = "extirq 7", 1336 [8] = "extirq 8", 1337 [9] = "extirq 9", 1338 [10] = "extirq 10", 1339 [11] = "extirq 11", 1340 }; 1341 #endif 1342 1343 static void 1344 mpc85xx_extirq_setup(void) 1345 { 1346 #ifdef MPC8548 1347 const char * const * names = mpc8548cds_extirq_names; 1348 const size_t n = __arraycount(mpc8548cds_extirq_names); 1349 #else 1350 const char * const * names = mpc85xx_extirq_names; 1351 const size_t n = __arraycount(mpc85xx_extirq_names); 1352 #endif 1353 prop_array_t extirqs = prop_array_create_with_capacity(n); 1354 for (u_int i = 0; i < n; i++) { 1355 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1356 prop_array_set(extirqs, i, ps); 1357 prop_object_release(ps); 1358 } 1359 board_info_add_object("external-irqs", extirqs); 1360 prop_object_release(extirqs); 1361 } 1362 1363 static void 1364 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1365 { 1366 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1367 KASSERT(pci_intmap != NULL); 1368 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1369 KASSERT(mask != NULL); 1370 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1371 prop_object_release(mask); 1372 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1373 KASSERT(pn_ist != NULL); 1374 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1375 KASSERT(pn_intr != NULL); 1376 prop_dictionary_t entry = prop_dictionary_create(); 1377 KASSERT(entry != NULL); 1378 prop_dictionary_set(entry, "interrupt", pn_intr); 1379 prop_dictionary_set(entry, "type", pn_ist); 1380 prop_dictionary_set(pci_intmap, "000000", entry); 1381 prop_object_release(pn_intr); 1382 prop_object_release(entry); 1383 va_list ap; 1384 va_start(ap, inta); 1385 u_int intrinc = __LOWEST_SET_BIT(intmask); 1386 for (u_int i = 0; i < intmask; i += intrinc) { 1387 char prop_name[12]; 1388 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1389 entry = prop_dictionary_create(); 1390 KASSERT(entry != NULL); 1391 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1392 KASSERT(pn_intr != NULL); 1393 prop_dictionary_set(entry, "interrupt", pn_intr); 1394 prop_dictionary_set(entry, "type", pn_ist); 1395 prop_dictionary_set(pci_intmap, prop_name, entry); 1396 prop_object_release(pn_intr); 1397 prop_object_release(entry); 1398 } 1399 va_end(ap); 1400 prop_object_release(pn_ist); 1401 board_info_add_object(name, pci_intmap); 1402 prop_object_release(pci_intmap); 1403 } 1404 1405 void 1406 cpu_startup(void) 1407 { 1408 struct cpu_info * const ci = curcpu(); 1409 const uint16_t svr = getsvr(); 1410 1411 powersave = 0; /* we can do it but turn it on by default */ 1412 1413 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1414 1415 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1416 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1417 uint32_t e500_ratio = E500_RATIO_GET(v); 1418 1419 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1420 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1421 1422 ci->ci_khz = (cpu_freq + 500) / 1000; 1423 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1424 1425 board_info_add_number("my-id", svr); 1426 board_info_add_bool("pq3"); 1427 board_info_add_number("mem-size", pmemsize); 1428 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1429 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1430 uint32_t l2banks = l2siz >> 16; 1431 #ifdef MPC85555 1432 if (svr == (MPC8555v1 >> 16)) { 1433 l2siz >>= 1; 1434 l2banks >>= 1; 1435 } 1436 #endif 1437 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1438 if (boot_page & BPTR_EN) { 1439 bool found = false; 1440 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1441 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1442 * const bp = (void *)boot_page; 1443 bp <= dp; dp--) { 1444 if (*dp == boot_page) { 1445 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1446 spinup_table_addr = 1447 roundup2(spinup_table_addr, 32); 1448 board_info_add_number("mp-boot-page", 1449 boot_page); 1450 board_info_add_number("mp-spin-up-table", 1451 spinup_table_addr); 1452 printf("Found MP boot page @ %#"PRIxPADDR". " 1453 "Spin-up table @ %#"PRIxPTR"\n", 1454 boot_page, spinup_table_addr); 1455 found = true; 1456 break; 1457 } 1458 } 1459 if (!found) { 1460 printf("Found MP boot page @ %#"PRIxPADDR 1461 " with missing U-boot signature!\n", boot_page); 1462 board_info_add_number("mp-spin-up-table", 0); 1463 } 1464 } 1465 board_info_add_number("l2-cache-size", l2siz); 1466 board_info_add_number("l2-cache-line-size", 32); 1467 board_info_add_number("l2-cache-banks", l2banks); 1468 board_info_add_number("l2-cache-ways", 8); 1469 1470 board_info_add_number("processor-frequency", cpu_freq); 1471 board_info_add_number("bus-frequency", ccb_freq); 1472 board_info_add_number("pci-frequency", e500_sys_clk); 1473 board_info_add_number("timebase-frequency", ccb_freq / 8); 1474 1475 #ifdef CADMUS 1476 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1477 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1478 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1479 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1480 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1481 #else 1482 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1483 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1484 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1485 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1486 #endif 1487 1488 uint64_t macstnaddr = 1489 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1490 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1491 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1492 1493 #if NPCI > 0 && defined(PCI_MEMBASE) 1494 pcimem_ex = extent_create("pcimem", 1495 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1496 NULL, 0, EX_WAITOK); 1497 #endif 1498 #if NPCI > 0 && defined(PCI_IOBASE) 1499 pciio_ex = extent_create("pciio", 1500 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1501 NULL, 0, EX_WAITOK); 1502 #endif 1503 mpc85xx_extirq_setup(); 1504 /* 1505 * PCI-Express virtual wire interrupts on combined with 1506 * External IRQ0/1/2/3. 1507 */ 1508 switch (svr) { 1509 #if defined(MPC8548) 1510 case SVR_MPC8548v1 >> 16: 1511 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1512 IST_LEVEL, 0, 1, 2, 3); 1513 break; 1514 #endif 1515 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \ 1516 || defined(P1025) || defined(P2020) || defined(P1023) 1517 case SVR_MPC8536v1 >> 16: 1518 case SVR_MPC8544v1 >> 16: 1519 case SVR_MPC8572v1 >> 16: 1520 case SVR_P1016v1 >> 16: 1521 case SVR_P1017v1 >> 16: 1522 case SVR_P1023v1 >> 16: 1523 case SVR_P2010v2 >> 16: 1524 case SVR_P2020v2 >> 16: 1525 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1526 8, 9, 10, 11); 1527 /* FALLTHROUGH */ 1528 case SVR_P1025v1 >> 16: 1529 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1530 4, 5, 6, 7); 1531 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1532 0, 1, 2, 3); 1533 break; 1534 #endif 1535 } 1536 switch (svr) { 1537 #if defined(MPC8536) 1538 case SVR_MPC8536v1 >> 16: 1539 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1540 1, 2, 3, 4); 1541 break; 1542 #endif 1543 #if defined(MPC8544) 1544 case SVR_MPC8544v1 >> 16: 1545 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1546 0, 1, 2, 3); 1547 break; 1548 #endif 1549 #if defined(MPC8548) 1550 case SVR_MPC8548v1 >> 16: 1551 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1552 0, 1, 2, 3); 1553 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1554 11, 1, 2, 3); 1555 break; 1556 #endif 1557 } 1558 } 1559
Indexes created Mon Sep 29 03:10:08 GMT 2025