machdep.c revision 1.5
1 /* $NetBSD: machdep.c,v 1.5 2011/02/17 13:57:12 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 64 #include <uvm/uvm_extern.h> 65 66 #include <prop/proplib.h> 67 68 #include <machine/stdarg.h> 69 70 #include <dev/cons.h> 71 72 #include <dev/ic/comreg.h> 73 #include <dev/ic/comvar.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 #include <dev/mii/miivar.h> 78 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 void initppc(vaddr_t, vaddr_t); 96 97 #define MEMREGIONS 4 98 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 99 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 100 static u_int nmemr; 101 102 #ifndef CONSFREQ 103 # define CONSFREQ -1 /* inherit from firmware */ 104 #endif 105 #ifndef CONSPEED 106 # define CONSPEED 115200 107 #endif 108 #ifndef CONMODE 109 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 110 #endif 111 #ifndef CONSADDR 112 # define CONSADDR DUART2_BASE 113 #endif 114 115 int comcnfreq = CONSFREQ; 116 int comcnspeed = CONSPEED; 117 tcflag_t comcnmode = CONMODE; 118 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 119 120 #if NPCI > 0 121 struct extent *pcimem_ex; 122 struct extent *pciio_ex; 123 #endif 124 125 struct powerpc_bus_space gur_bst = { 126 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 127 .pbs_offset = GUR_BASE, 128 .pbs_limit = GUR_SIZE, 129 }; 130 131 struct powerpc_bus_space gur_le_bst = { 132 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 133 .pbs_offset = GUR_BASE, 134 .pbs_limit = GUR_SIZE, 135 }; 136 137 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 138 139 #ifdef CADMUS 140 static uint8_t cadmus_pci; 141 static uint8_t cadmus_csr; 142 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 143 #elif defined(PIXIS) 144 static const uint32_t pixis_spd_map[8] = { 145 [PX_SPD_33MHZ] = 33333333, 146 [PX_SPD_40MHZ] = 40000000, 147 [PX_SPD_50MHZ] = 50000000, 148 [PX_SPD_66MHZ] = 66666666, 149 [PX_SPD_83MHZ] = 83333333, 150 [PX_SPD_133MHZ] = 100000000, 151 [PX_SPD_133MHZ] = 133333333, 152 [PX_SPD_166MHZ] = 166666667, 153 }; 154 static uint8_t pixis_spd; 155 static uint64_t e500_sys_clk; 156 #elif defined(SYS_CLK) 157 static uint64_t e500_sys_clk = SYS_CLK; 158 #else 159 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 160 #endif 161 162 static int e500_cngetc(dev_t); 163 static void e500_cnputc(dev_t, int); 164 165 static struct consdev e500_earlycons = { 166 .cn_getc = e500_cngetc, 167 .cn_putc = e500_cnputc, 168 .cn_pollc = nullcnpollc, 169 }; 170 171 /* 172 * List of port-specific devices to attach to the processor local bus. 173 */ 174 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 175 { "cpu" }, /* not a real device */ 176 { "wdog" }, /* not a real device */ 177 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 178 1, { ISOURCE_DUART }, 179 1 + ilog2(DEVDISR_DUART) }, 180 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 181 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 182 1 + ilog2(DEVDISR_TSEC1) }, 183 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 184 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 185 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 186 1 + ilog2(DEVDISR_TSEC2), 187 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 188 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 189 #endif 190 #if defined(MPC8544) || defined(MPC8536) 191 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 192 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 193 1 + ilog2(DEVDISR_TSEC3), 194 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 195 #endif 196 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 197 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 198 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 199 1 + ilog2(DEVDISR_TSEC3), 200 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 201 SVR_P2020v2 >> 16 } }, 202 #endif 203 #if defined(MPC8548) || defined(MPC8572) 204 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 205 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 206 1 + ilog2(DEVDISR_TSEC4), 207 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 208 #endif 209 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 210 1, { ISOURCE_I2C }, 211 1 + ilog2(DEVDISR_I2C) }, 212 /* MPC8572 doesn't have any GPIO */ 213 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 214 1, { ISOURCE_GPIO }, 215 0, 216 { 0xffff, SVR_MPC8572v1 >> 16 } }, 217 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 218 1, { ISOURCE_DDR }, 219 1 + ilog2(DEVDISR_DDR_15), 220 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 221 #if defined(MPC8536) 222 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 223 1, { ISOURCE_DDR }, 224 1 + ilog2(DEVDISR_DDR_16), 225 { SVR_MPC8536v1 >> 16 } }, 226 #endif 227 #if defined(MPC8572) 228 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 229 1, { ISOURCE_DDR }, 230 1 + ilog2(DEVDISR_DDR_15), 231 { SVR_MPC8572v1 >> 16 } }, 232 { "ddrc", DDRC1_BASE, DDRC_SIZE, 2, 233 1, { ISOURCE_DDR }, 234 1 + ilog2(DEVDISR_DDR2_14), 235 { SVR_MPC8572v1 >> 16 } }, 236 #endif 237 #if defined(MPC8544) || defined(MPC8536) 238 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 239 1, { ISOURCE_PCIEX }, 240 1 + ilog2(DEVDISR_PCIE), 241 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 242 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 243 1, { ISOURCE_PCIEX2 }, 244 1 + ilog2(DEVDISR_PCIE2), 245 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 246 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 247 1, { ISOURCE_PCIEX3 }, 248 1 + ilog2(DEVDISR_PCIE3), 249 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 250 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 251 1, { ISOURCE_PCI1 }, 252 1 + ilog2(DEVDISR_PCI1), 253 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 254 #endif 255 #ifdef MPC8548 256 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 257 1, { ISOURCE_PCIEX }, 258 1 + ilog2(DEVDISR_PCIE), 259 { SVR_MPC8548v1 >> 16 }, }, 260 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 261 1, { ISOURCE_PCI1 }, 262 1 + ilog2(DEVDISR_PCI1), 263 { SVR_MPC8548v1 >> 16 }, }, 264 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 265 1, { ISOURCE_PCI2 }, 266 1 + ilog2(DEVDISR_PCI2), 267 { SVR_MPC8548v1 >> 16 }, }, 268 #endif 269 #if defined(MPC8572) || defined(P2020) 270 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 271 1, { ISOURCE_PCIEX }, 272 1 + ilog2(DEVDISR_PCIE), 273 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 274 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 275 1, { ISOURCE_PCIEX2 }, 276 1 + ilog2(DEVDISR_PCIE2), 277 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 278 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 279 1, { ISOURCE_PCIEX3_MPC8572 }, 280 1 + ilog2(DEVDISR_PCIE3), 281 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 282 #endif 283 #if defined(MPC8536) || defined(P2020) 284 { "ehci", USB1_BASE, USB_SIZE, 1, 285 1, { ISOURCE_USB1 }, 286 1 + ilog2(DEVDISR_USB1), 287 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 288 #endif 289 #ifdef MPC8536 290 { "ehci", USB2_BASE, USB_SIZE, 2, 291 1, { ISOURCE_USB2 }, 292 1 + ilog2(DEVDISR_USB2), 293 { SVR_MPC8536v1 >> 16 }, }, 294 { "ehci", USB3_BASE, USB_SIZE, 3, 295 1, { ISOURCE_USB3 }, 296 1 + ilog2(DEVDISR_USB3), 297 { SVR_MPC8536v1 >> 16 }, }, 298 { "sata", SATA1_BASE, SATA_SIZE, 1, 299 1, { ISOURCE_SATA1 }, 300 1 + ilog2(DEVDISR_SATA1), 301 { SVR_MPC8536v1 >> 16 }, }, 302 { "sata", SATA2_BASE, SATA_SIZE, 2, 303 1, { ISOURCE_SATA2 }, 304 1 + ilog2(DEVDISR_SATA2), 305 { SVR_MPC8536v1 >> 16 }, }, 306 { "spi", SPI_BASE, SPI_SIZE, 0, 307 1, { ISOURCE_SPI }, 308 1 + ilog2(DEVDISR_SPI_15), 309 { SVR_MPC8536v1 >> 16 }, }, 310 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 311 1, { ISOURCE_ESDHC }, 312 1 + ilog2(DEVDISR_ESDHC_12), 313 { SVR_MPC8536v1 >> 16 }, }, 314 #endif 315 #if defined(P2020) 316 { "spi", SPI_BASE, SPI_SIZE, 0, 317 1, { ISOURCE_SPI }, 318 1 + ilog2(DEVDISR_SPI_28), 319 { SVR_P2020v2 >> 16 }, }, 320 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 321 1, { ISOURCE_ESDHC }, 322 1 + ilog2(DEVDISR_ESDHC_10), 323 { SVR_P2020v2 >> 16 }, }, 324 #endif 325 { "lbc", LBC_BASE, LBC_SIZE, 0, 326 1, { ISOURCE_LBC }, 327 1 + ilog2(DEVDISR_LBC) }, 328 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 329 { NULL } 330 }; 331 332 static int 333 e500_cngetc(dev_t dv) 334 { 335 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 336 337 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 338 return -1; 339 340 return com0addr[com_data] & 0xff; 341 } 342 343 static void 344 e500_cnputc(dev_t dv, int c) 345 { 346 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 347 int timo = 150000; 348 349 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 350 ; 351 352 com0addr[com_data] = c; 353 __asm("mbar"); 354 355 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 356 ; 357 } 358 359 static void * 360 gur_tlb_mapiodev(paddr_t pa, psize_t len) 361 { 362 if (pa < gur_bst.pbs_offset) 363 return NULL; 364 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 365 return NULL; 366 return (void *)pa; 367 } 368 369 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 370 371 static void 372 e500_cpu_reset(void) 373 { 374 __asm volatile("sync"); 375 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 376 __asm volatile("msync;isync"); 377 } 378 379 static psize_t 380 memprobe(vaddr_t endkernel) 381 { 382 phys_ram_seg_t *mr; 383 384 /* 385 * First we need to find out how much physical memory we have. 386 * We could let our bootloader tell us, but it's almost as easy 387 * to ask the DDR memory controller. 388 */ 389 mr = physmemr; 390 #if 1 391 for (u_int i = 0; i < 4; i++) { 392 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 393 if (v & CS_CONFIG_EN) { 394 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 395 mr->start = BNDS_SA_GET(v); 396 mr->size = BNDS_SIZE_GET(v); 397 mr++; 398 } 399 } 400 401 if (mr == physmemr) 402 panic("no memory configured!"); 403 #else 404 mr->start = 0; 405 mr->size = 32 << 20; 406 mr++; 407 #endif 408 409 /* 410 * Sort memory regions from low to high and coalesce adjacent regions 411 */ 412 u_int cnt = mr - physmemr; 413 if (cnt > 1) { 414 for (u_int i = 0; i < cnt - 1; i++) { 415 for (u_int j = i + 1; j < cnt; j++) { 416 if (physmemr[j].start < physmemr[i].start) { 417 phys_ram_seg_t tmp = physmemr[i]; 418 physmemr[i] = physmemr[j]; 419 physmemr[j] = tmp; 420 } 421 } 422 } 423 mr = physmemr; 424 for (u_int i = 0; i < cnt; i++, mr++) { 425 if (mr->start + mr->size == mr[1].start) { 426 mr->size += mr[1].size; 427 for (u_int j = 1; j < cnt - i; j++) 428 mr[j] = mr[j+1]; 429 cnt--; 430 } 431 } 432 } 433 434 /* 435 * Copy physical memory to available memory. 436 */ 437 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 438 439 /* 440 * Adjust available memory to skip kernel at start of memory. 441 */ 442 availmemr[0].size -= endkernel - availmemr[0].start; 443 availmemr[0].start = endkernel; 444 445 /* 446 * Steal pages at the end of memory for the kernel message buffer. 447 */ 448 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 449 msgbuf_paddr = 450 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 451 452 /* 453 * Calculate physmem. 454 */ 455 for (u_int i = 0; i < cnt; i++) 456 physmem += atop(physmemr[i].size); 457 458 nmemr = cnt; 459 return physmemr[cnt-1].start + physmemr[cnt-1].size; 460 } 461 462 void 463 consinit(void) 464 { 465 static bool attached = false; 466 467 if (attached) 468 return; 469 attached = true; 470 471 if (comcnfreq == -1) { 472 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 473 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 474 comcnfreq = e500_sys_clk * plat_ratio; 475 printf(" comcnfreq=%u", comcnfreq); 476 } 477 478 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 479 COM_TYPE_NORMAL, comcnmode); 480 } 481 482 void 483 cpu_probe_cache(void) 484 { 485 struct cpu_info * const ci = curcpu(); 486 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 487 488 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 489 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 490 491 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 492 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 493 494 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 495 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 496 } else { 497 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 498 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 499 } 500 501 #ifdef DEBUG 502 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 503 if ((L1CSR_CE & l1csr0) == 0) 504 printf(" DC=off"); 505 506 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 507 if ((L1CSR_CE & l1csr1) == 0) 508 printf(" IC=off"); 509 #endif 510 } 511 512 static uint16_t 513 getsvr(void) 514 { 515 uint16_t svr = mfspr(SPR_SVR) >> 16; 516 517 svr &= ~0x8; /* clear security bit */ 518 switch (svr) { 519 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 520 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 521 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 522 default: return svr; 523 } 524 } 525 526 static const char * 527 socname(uint32_t svr) 528 { 529 svr &= ~0x80000; /* clear security bit */ 530 switch (svr >> 8) { 531 case SVR_MPC8533 >> 8: return "MPC8533"; 532 case SVR_MPC8536v1 >> 8: return "MPC8536"; 533 case SVR_MPC8541v1 >> 8: return "MPC8541"; 534 case SVR_MPC8543v2 >> 8: return "MPC8543"; 535 case SVR_MPC8544v1 >> 8: return "MPC8544"; 536 case SVR_MPC8545v2 >> 8: return "MPC8545"; 537 case SVR_MPC8547v2 >> 8: return "MPC8547"; 538 case SVR_MPC8548v2 >> 8: return "MPC8548"; 539 case SVR_MPC8555v1 >> 8: return "MPC8555"; 540 case SVR_MPC8568v1 >> 8: return "MPC8568"; 541 case SVR_MPC8567v1 >> 8: return "MPC8567"; 542 case SVR_MPC8572v1 >> 8: return "MPC8572"; 543 case SVR_P2020v2 >> 8: return "P2020"; 544 case SVR_P2010v2 >> 8: return "P2010"; 545 default: 546 panic("%s: unknown SVR %#x", __func__, svr); 547 } 548 } 549 550 static void 551 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 552 { 553 static const char units[16] = "KKKKKMMMMMGGGGGT"; 554 555 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 556 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 557 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 558 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 559 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 560 561 aprint_normal_dev(self, "%s:", name); 562 563 aprint_normal(" %u", nentries); 564 if (TLBCFG_AVAIL_P(tlbcfg)) { 565 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 566 minsize, maxsize, units[maxsize_log4k]); 567 } else { 568 aprint_normal(" fixed-size (%uKB)", minsize); 569 } 570 if (assoc == 0 || assoc == nentries) 571 aprint_normal(" fully"); 572 else 573 aprint_normal(" %u-way set", assoc); 574 aprint_normal(" associative entries\n"); 575 } 576 577 static void 578 e500_cpu_attach(device_t self, u_int instance) 579 { 580 struct cpu_info * const ci = &cpu_info[instance]; 581 582 KASSERT(instance == 0); 583 self->dv_private = ci; 584 585 ci->ci_cpuid = instance; 586 ci->ci_dev = self; 587 //ci->ci_idlespin = cpu_idlespin; 588 if (instance > 0) { 589 ci->ci_idepth = -1; 590 cpu_probe_cache(); 591 } 592 593 uint64_t freq = board_info_get_number("processor-frequency"); 594 char freqbuf[10]; 595 if (freq >= 999500000) { 596 const uint32_t freq32 = (freq + 500000) / 10000000; 597 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 598 freq32 / 100, freq32 % 100); 599 } else { 600 const uint32_t freq32 = (freq + 500000) / 1000000; 601 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 602 } 603 604 const uint32_t pvr = mfpvr(); 605 const uint32_t svr = mfspr(SPR_SVR); 606 const uint32_t pir = mfspr(SPR_PIR); 607 608 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 609 "ID %u%s\n", 610 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 611 (svr >> 4) & 15, svr & 15, 612 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 613 (pvr >> 4) & 15, pvr & 15, 614 pir, (pir == 0 ? " (Primary)" : "")); 615 616 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 617 aprint_normal_dev(self, 618 "%uKB/%uB %u-way L1 %s cache\n", 619 L1CFG_CSIZE_GET(l1cfg0) >> 10, 620 32 << L1CFG_CBSIZE_GET(l1cfg0), 621 L1CFG_CNWAY_GET(l1cfg0), 622 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 623 ? "data" : "unified"); 624 625 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 626 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 627 aprint_normal_dev(self, 628 "%uKB/%uB %u-way L1 %s cache\n", 629 L1CFG_CSIZE_GET(l1cfg1) >> 10, 630 32 << L1CFG_CBSIZE_GET(l1cfg1), 631 L1CFG_CNWAY_GET(l1cfg1), 632 "instruction"); 633 } 634 635 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 636 aprint_normal_dev(self, 637 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 638 MMUCFG_NTLBS_GET(mmucfg) + 1, 639 MMUCFG_NPIDS_GET(mmucfg), 640 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 641 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 642 643 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 644 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 645 646 intr_cpu_init(ci); 647 cpu_evcnt_attach(ci); 648 } 649 650 static void 651 calltozero(void) 652 { 653 panic("call to 0 from %p", __builtin_return_address(0)); 654 } 655 656 void 657 initppc(vaddr_t startkernel, vaddr_t endkernel) 658 { 659 struct cpu_info * const ci = curcpu(); 660 struct cpu_softc * const cpu = ci->ci_softc; 661 662 cn_tab = &e500_earlycons; 663 printf(" initppc<enter>"); 664 665 const register_t hid0 = mfspr(SPR_HID0); 666 mtspr(SPR_HID0, hid0 | HID0_TBEN | HID0_EMCP); 667 #ifdef CADMUS 668 /* 669 * Need to cache this from cadmus since we need to unmap cadmus since 670 * it falls in the middle of kernel address space. 671 */ 672 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 673 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 674 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 675 printf(" cadmus_pci=%#x", cadmus_pci); 676 printf(" cadmus_csr=%#x", cadmus_csr); 677 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 678 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 679 e500_sys_clk *= 2; 680 } 681 #endif 682 #ifdef PIXIS 683 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 684 printf(" pixis_spd=%#x ", pixis_spd); 685 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 686 #endif 687 printf(" porpllsr=0x%08x", 688 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 689 printf(" sys_clk=%"PRIu64, e500_sys_clk); 690 691 /* 692 * Make sure arguments are page aligned. 693 */ 694 startkernel = trunc_page(startkernel); 695 endkernel = round_page(endkernel); 696 697 /* 698 * Initialize the bus space tag used to access the 85xx general 699 * utility registers. It doesn't need to be extent protected. 700 * We know the GUR is mapped via a TLB1 entry so we add a limited 701 * mapiodev which allows mappings in GUR space. 702 */ 703 CTASSERT(offsetof(struct tlb_md_ops, md_tlb_mapiodev) == 0); 704 cpu_md_ops.md_tlb_ops = (const void *)&early_tlb_mapiodev; 705 bus_space_init(&gur_bst, NULL, NULL, 0); 706 bus_space_init(&gur_le_bst, NULL, NULL, 0); 707 cpu->cpu_bst = &gur_bst; 708 cpu->cpu_le_bst = &gur_le_bst; 709 cpu->cpu_bsh = gur_bsh; 710 711 /* 712 * Attach the console early, really early. 713 */ 714 consinit(); 715 716 /* 717 * Reset the PIC to a known state. 718 */ 719 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 720 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 721 ; 722 #if 0 723 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 724 #endif 725 printf(" openpic-reset(ctpr=%u)", 726 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 727 728 /* 729 * fill in with an absolute branch to a routine that will panic. 730 */ 731 *(int *)0 = 0x48000002 | (int) calltozero; 732 733 /* 734 * Get the cache sizes. 735 */ 736 cpu_probe_cache(); 737 printf(" cache(DC=%u/%u,IC=%u/%u)", 738 ci->ci_ci.dcache_size >> 10, 739 ci->ci_ci.dcache_line_size, 740 ci->ci_ci.icache_size >> 10, 741 ci->ci_ci.icache_line_size); 742 743 /* 744 * Now find out how much memory is attached 745 */ 746 pmemsize = memprobe(endkernel); 747 cpu->cpu_highmem = pmemsize; 748 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 749 750 /* 751 * Now we need cleanout the TLB of stuff that we don't need. 752 */ 753 e500_tlb_init(endkernel, pmemsize); 754 printf(" e500_tlbinit(%#lx,%zuMB)", 755 endkernel, (size_t) (pmemsize >> 20)); 756 757 /* 758 * 759 */ 760 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 761 printf(" hid1=%#lx", mfspr(SPR_HID1)); 762 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 763 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 764 765 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 766 767 /* 768 * Initialize the message buffer. 769 */ 770 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 771 printf(" msgbuf=%p", (void *)msgbuf_paddr); 772 773 /* 774 * Initialize exception vectors and interrupts 775 */ 776 exception_init(&e500_intrsw); 777 printf(" exception_init=%p", &e500_intrsw); 778 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 779 780 /* 781 * Set the page size. 782 */ 783 uvm_setpagesize(); 784 785 /* 786 * Initialize the pmap. 787 */ 788 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 789 790 /* 791 * Let's take all the indirect calls via our stubs and patch 792 * them to be direct calls. 793 */ 794 booke_fixup_stubs(); 795 #if 0 796 /* 797 * As a debug measure we can change the TLB entry that maps all of 798 * memory to one that encompasses the 64KB with the kernel vectors. 799 * All other pages will be soft faulted into the TLB as needed. 800 */ 801 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 802 mtspr(SPR_MAS6, 0); 803 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 804 uint32_t mas0 = mfspr(SPR_MAS0); 805 uint32_t mas1 = mfspr(SPR_MAS1); 806 uint32_t mas2 = mfspr(SPR_MAS2); 807 uint32_t mas3 = mfspr(SPR_MAS3); 808 KASSERT(mas3 & MAS3_SW); 809 KASSERT(mas3 & MAS3_SR); 810 KASSERT(mas3 & MAS3_SX); 811 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 812 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 813 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 814 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 815 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 816 #if 1 817 mtspr(SPR_MAS1, mas1); 818 mtspr(SPR_MAS2, mas2); 819 mtspr(SPR_MAS3, mas3); 820 extern void tlbwe(void); 821 tlbwe(); 822 mtspr(SPR_MAS0, saved_mas0); 823 printf("(ok)"); 824 #endif 825 #endif 826 827 /* 828 * Set some more MD helpers 829 */ 830 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 831 cpu_md_ops.md_device_register = e500_device_register; 832 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 833 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 834 #if NGPIO > 0 835 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 836 #endif 837 838 printf(" initppc done!\n"); 839 } 840 841 #ifdef MPC8548 842 static const char * const mpc8548cds_extirq_names[] = { 843 [0] = "pci inta", 844 [1] = "pci intb", 845 [2] = "pci intc", 846 [3] = "pci intd", 847 [4] = "irq4", 848 [5] = "gige phy", 849 [6] = "atm phy", 850 [7] = "cpld", 851 [8] = "irq8", 852 [9] = "nvram", 853 [10] = "debug", 854 [11] = "pci2 inta", 855 }; 856 #endif 857 858 static const char * const mpc85xx_extirq_names[] = { 859 [0] = "extirq 0", 860 [1] = "extirq 1", 861 [2] = "extirq 2", 862 [3] = "extirq 3", 863 [4] = "extirq 4", 864 [5] = "extirq 5", 865 [6] = "extirq 6", 866 [7] = "extirq 7", 867 [8] = "extirq 8", 868 [9] = "extirq 9", 869 [10] = "extirq 10", 870 [11] = "extirq 11", 871 }; 872 873 static void 874 mpc85xx_extirq_setup(void) 875 { 876 #ifdef MPC8548 877 const char * const * names = mpc8548cds_extirq_names; 878 const size_t n = __arraycount(mpc8548cds_extirq_names); 879 #else 880 const char * const * names = mpc85xx_extirq_names; 881 const size_t n = __arraycount(mpc85xx_extirq_names); 882 #endif 883 prop_array_t extirqs = prop_array_create_with_capacity(n); 884 for (u_int i = 0; i < n; i++) { 885 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 886 prop_array_set(extirqs, i, ps); 887 prop_object_release(ps); 888 } 889 board_info_add_object("external-irqs", extirqs); 890 prop_object_release(extirqs); 891 } 892 893 static void 894 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 895 { 896 prop_dictionary_t pci_intmap = prop_dictionary_create(); 897 KASSERT(pci_intmap != NULL); 898 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 899 KASSERT(mask != NULL); 900 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 901 prop_object_release(mask); 902 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 903 KASSERT(pn_ist != NULL); 904 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 905 KASSERT(pn_intr != NULL); 906 prop_dictionary_t entry = prop_dictionary_create(); 907 KASSERT(entry != NULL); 908 prop_dictionary_set(entry, "interrupt", pn_intr); 909 prop_dictionary_set(entry, "type", pn_ist); 910 prop_dictionary_set(pci_intmap, "000000", entry); 911 prop_object_release(pn_intr); 912 prop_object_release(entry); 913 va_list ap; 914 va_start(ap, inta); 915 u_int intrinc = __LOWEST_SET_BIT(intmask); 916 for (u_int i = 0; i < intmask; i += intrinc) { 917 char prop_name[12]; 918 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 919 entry = prop_dictionary_create(); 920 KASSERT(entry != NULL); 921 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 922 KASSERT(pn_intr != NULL); 923 prop_dictionary_set(entry, "interrupt", pn_intr); 924 prop_dictionary_set(entry, "type", pn_ist); 925 prop_dictionary_set(pci_intmap, prop_name, entry); 926 prop_object_release(pn_intr); 927 prop_object_release(entry); 928 } 929 va_end(ap); 930 prop_object_release(pn_ist); 931 board_info_add_object(name, pci_intmap); 932 prop_object_release(pci_intmap); 933 } 934 935 void 936 cpu_startup(void) 937 { 938 struct cpu_info * const ci = curcpu(); 939 const uint16_t svr = getsvr(); 940 941 booke_cpu_startup(socname(mfspr(SPR_SVR))); 942 943 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 944 uint32_t plat_ratio = PLAT_RATIO_GET(v); 945 uint32_t e500_ratio = E500_RATIO_GET(v); 946 947 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 948 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 949 950 ci->ci_khz = (cpu_freq + 500) / 1000; 951 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 952 953 board_info_add_number("my-id", svr); 954 board_info_add_bool("pq3"); 955 board_info_add_number("mem-size", pmemsize); 956 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 957 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 958 uint32_t l2banks = l2siz >> 16; 959 #ifdef MPC85555 960 if (svr == (MPC8555v1 >> 16)) { 961 l2siz >>= 1; 962 l2banks >>= 1; 963 } 964 #endif 965 board_info_add_number("l2-cache-size", l2siz); 966 board_info_add_number("l2-cache-line-size", 32); 967 board_info_add_number("l2-cache-banks", l2banks); 968 board_info_add_number("l2-cache-ways", 8); 969 970 board_info_add_number("processor-frequency", cpu_freq); 971 board_info_add_number("bus-frequency", ccb_freq); 972 board_info_add_number("pci-frequency", e500_sys_clk); 973 board_info_add_number("timebase-frequency", ccb_freq / 8); 974 975 #ifdef CADMUS 976 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 977 board_info_add_number("tsec1-phy-addr", phy_base + 0); 978 board_info_add_number("tsec2-phy-addr", phy_base + 1); 979 board_info_add_number("tsec3-phy-addr", phy_base + 2); 980 board_info_add_number("tsec4-phy-addr", phy_base + 3); 981 #else 982 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 983 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 984 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 985 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 986 #endif 987 988 uint64_t macstnaddr = 989 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 990 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 991 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 992 993 #if NPCI > 0 && defined(PCI_MEMBASE) 994 pcimem_ex = extent_create("pcimem", 995 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 996 M_DEVBUF, NULL, 0, EX_WAITOK); 997 #endif 998 #if NPCI > 0 && defined(PCI_IOBASE) 999 pciio_ex = extent_create("pciio", 1000 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1001 M_DEVBUF, NULL, 0, EX_WAITOK); 1002 #endif 1003 mpc85xx_extirq_setup(); 1004 /* 1005 * PCI-Express virtual wire interrupts on combined with 1006 * External IRQ0/1/2/3. 1007 */ 1008 switch (svr) { 1009 #if defined(MPC8548) 1010 case SVR_MPC8548v1 >> 16: 1011 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1012 IST_LEVEL, 0, 1, 2, 3); 1013 break; 1014 #endif 1015 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1016 case SVR_MPC8536v1 >> 16: 1017 case SVR_MPC8544v1 >> 16: 1018 case SVR_MPC8572v1 >> 16: 1019 case SVR_P2010v2 >> 16: 1020 case SVR_P2020v2 >> 16: 1021 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1022 0, 1, 2, 3); 1023 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1024 4, 5, 6, 7); 1025 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1026 8, 9, 10, 11); 1027 break; 1028 #endif 1029 } 1030 switch (svr) { 1031 #if defined(MPC8536) 1032 case SVR_MPC8536v1 >> 16: 1033 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1034 1, 2, 3, 4); 1035 break; 1036 #endif 1037 #if defined(MPC8544) 1038 case SVR_MPC8544v1 >> 16: 1039 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1040 0, 1, 2, 3); 1041 break; 1042 #endif 1043 #if defined(MPC8548) 1044 case SVR_MPC8548v1 >> 16: 1045 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1046 0, 1, 2, 3); 1047 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1048 11, 1, 2, 3); 1049 break; 1050 #endif 1051 } 1052 } 1053
Indexes created Mon Sep 29 18:09:42 GMT 2025