machdep.c revision 1.5.2.4
1 /* $NetBSD: machdep.c,v 1.5.2.4 2011/06/12 00:23:57 rmind Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 64 #include <uvm/uvm_extern.h> 65 66 #include <prop/proplib.h> 67 68 #include <machine/stdarg.h> 69 70 #include <dev/cons.h> 71 72 #include <dev/ic/comreg.h> 73 #include <dev/ic/comvar.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 #include <dev/mii/miivar.h> 78 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 void initppc(vaddr_t, vaddr_t); 96 97 #define MEMREGIONS 4 98 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 99 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 100 static u_int nmemr; 101 102 #ifndef CONSFREQ 103 # define CONSFREQ -1 /* inherit from firmware */ 104 #endif 105 #ifndef CONSPEED 106 # define CONSPEED 115200 107 #endif 108 #ifndef CONMODE 109 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 110 #endif 111 #ifndef CONSADDR 112 # define CONSADDR DUART2_BASE 113 #endif 114 115 int comcnfreq = CONSFREQ; 116 int comcnspeed = CONSPEED; 117 tcflag_t comcnmode = CONMODE; 118 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 119 120 #if NPCI > 0 121 struct extent *pcimem_ex; 122 struct extent *pciio_ex; 123 #endif 124 125 struct powerpc_bus_space gur_bst = { 126 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 127 .pbs_offset = GUR_BASE, 128 .pbs_limit = GUR_SIZE, 129 }; 130 131 struct powerpc_bus_space gur_le_bst = { 132 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 133 .pbs_offset = GUR_BASE, 134 .pbs_limit = GUR_SIZE, 135 }; 136 137 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 138 139 #if defined(SYS_CLK) 140 static uint64_t e500_sys_clk = SYS_CLK; 141 #endif 142 #ifdef CADMUS 143 static uint8_t cadmus_pci; 144 static uint8_t cadmus_csr; 145 #ifndef SYS_CLK 146 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 147 #endif 148 #elif defined(PIXIS) 149 static const uint32_t pixis_spd_map[8] = { 150 [PX_SPD_33MHZ] = 33333333, 151 [PX_SPD_40MHZ] = 40000000, 152 [PX_SPD_50MHZ] = 50000000, 153 [PX_SPD_66MHZ] = 66666666, 154 [PX_SPD_83MHZ] = 83333333, 155 [PX_SPD_100MHZ] = 100000000, 156 [PX_SPD_133MHZ] = 133333333, 157 [PX_SPD_166MHZ] = 166666667, 158 }; 159 static uint8_t pixis_spd; 160 #ifndef SYS_CLK 161 static uint64_t e500_sys_clk; 162 #endif 163 #elif !defined(SYS_CLK) 164 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 165 #endif 166 167 static int e500_cngetc(dev_t); 168 static void e500_cnputc(dev_t, int); 169 170 static struct consdev e500_earlycons = { 171 .cn_getc = e500_cngetc, 172 .cn_putc = e500_cnputc, 173 .cn_pollc = nullcnpollc, 174 }; 175 176 /* 177 * List of port-specific devices to attach to the processor local bus. 178 */ 179 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 180 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 181 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 182 #if defined(MPC8572) || defined(P2020) 183 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 184 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 185 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 186 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 187 #endif 188 { "wdog" }, /* not a real device */ 189 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 190 1, { ISOURCE_DUART }, 191 1 + ilog2(DEVDISR_DUART) }, 192 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 193 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 194 1 + ilog2(DEVDISR_TSEC1) }, 195 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 196 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 197 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 198 1 + ilog2(DEVDISR_TSEC2), 199 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 200 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 201 #endif 202 #if defined(MPC8544) || defined(MPC8536) 203 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 204 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 205 1 + ilog2(DEVDISR_TSEC3), 206 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 207 #endif 208 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 209 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 210 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 211 1 + ilog2(DEVDISR_TSEC3), 212 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 213 SVR_P2020v2 >> 16 } }, 214 #endif 215 #if defined(MPC8548) || defined(MPC8572) 216 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 217 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 218 1 + ilog2(DEVDISR_TSEC4), 219 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 220 #endif 221 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 222 1, { ISOURCE_I2C }, 223 1 + ilog2(DEVDISR_I2C) }, 224 /* MPC8572 doesn't have any GPIO */ 225 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 226 1, { ISOURCE_GPIO }, 227 0, 228 { 0xffff, SVR_MPC8572v1 >> 16 } }, 229 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 230 1, { ISOURCE_DDR }, 231 1 + ilog2(DEVDISR_DDR_15), 232 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 233 #if defined(MPC8536) 234 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 235 1, { ISOURCE_DDR }, 236 1 + ilog2(DEVDISR_DDR_16), 237 { SVR_MPC8536v1 >> 16 } }, 238 #endif 239 #if defined(MPC8572) 240 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 241 1, { ISOURCE_DDR }, 242 1 + ilog2(DEVDISR_DDR_15), 243 { SVR_MPC8572v1 >> 16 } }, 244 { "ddrc", DDRC1_BASE, DDRC_SIZE, 2, 245 1, { ISOURCE_DDR }, 246 1 + ilog2(DEVDISR_DDR2_14), 247 { SVR_MPC8572v1 >> 16 } }, 248 #endif 249 { "lbc", LBC_BASE, LBC_SIZE, 0, 250 1, { ISOURCE_LBC }, 251 1 + ilog2(DEVDISR_LBC) }, 252 #if defined(MPC8544) || defined(MPC8536) 253 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 254 1, { ISOURCE_PCIEX }, 255 1 + ilog2(DEVDISR_PCIE), 256 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 257 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 258 1, { ISOURCE_PCIEX2 }, 259 1 + ilog2(DEVDISR_PCIE2), 260 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 261 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 262 1, { ISOURCE_PCIEX3 }, 263 1 + ilog2(DEVDISR_PCIE3), 264 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 265 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 266 1, { ISOURCE_PCI1 }, 267 1 + ilog2(DEVDISR_PCI1), 268 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 269 #endif 270 #ifdef MPC8548 271 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 272 1, { ISOURCE_PCIEX }, 273 1 + ilog2(DEVDISR_PCIE), 274 { SVR_MPC8548v1 >> 16 }, }, 275 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 276 1, { ISOURCE_PCI1 }, 277 1 + ilog2(DEVDISR_PCI1), 278 { SVR_MPC8548v1 >> 16 }, }, 279 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 280 1, { ISOURCE_PCI2 }, 281 1 + ilog2(DEVDISR_PCI2), 282 { SVR_MPC8548v1 >> 16 }, }, 283 #endif 284 #if defined(MPC8572) || defined(P2020) 285 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 286 1, { ISOURCE_PCIEX }, 287 1 + ilog2(DEVDISR_PCIE), 288 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 289 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 290 1, { ISOURCE_PCIEX2 }, 291 1 + ilog2(DEVDISR_PCIE2), 292 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 293 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 294 1, { ISOURCE_PCIEX3_MPC8572 }, 295 1 + ilog2(DEVDISR_PCIE3), 296 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 297 #endif 298 #if defined(MPC8536) || defined(P2020) 299 { "ehci", USB1_BASE, USB_SIZE, 1, 300 1, { ISOURCE_USB1 }, 301 1 + ilog2(DEVDISR_USB1), 302 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 303 #endif 304 #ifdef MPC8536 305 { "ehci", USB2_BASE, USB_SIZE, 2, 306 1, { ISOURCE_USB2 }, 307 1 + ilog2(DEVDISR_USB2), 308 { SVR_MPC8536v1 >> 16 }, }, 309 { "ehci", USB3_BASE, USB_SIZE, 3, 310 1, { ISOURCE_USB3 }, 311 1 + ilog2(DEVDISR_USB3), 312 { SVR_MPC8536v1 >> 16 }, }, 313 { "sata", SATA1_BASE, SATA_SIZE, 1, 314 1, { ISOURCE_SATA1 }, 315 1 + ilog2(DEVDISR_SATA1), 316 { SVR_MPC8536v1 >> 16 }, }, 317 { "sata", SATA2_BASE, SATA_SIZE, 2, 318 1, { ISOURCE_SATA2 }, 319 1 + ilog2(DEVDISR_SATA2), 320 { SVR_MPC8536v1 >> 16 }, }, 321 { "spi", SPI_BASE, SPI_SIZE, 0, 322 1, { ISOURCE_SPI }, 323 1 + ilog2(DEVDISR_SPI_15), 324 { SVR_MPC8536v1 >> 16 }, }, 325 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 326 1, { ISOURCE_ESDHC }, 327 1 + ilog2(DEVDISR_ESDHC_12), 328 { SVR_MPC8536v1 >> 16 }, }, 329 #endif 330 #if defined(P2020) 331 { "spi", SPI_BASE, SPI_SIZE, 0, 332 1, { ISOURCE_SPI }, 333 1 + ilog2(DEVDISR_SPI_28), 334 { SVR_P2020v2 >> 16 }, }, 335 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 336 1, { ISOURCE_ESDHC }, 337 1 + ilog2(DEVDISR_ESDHC_10), 338 { SVR_P2020v2 >> 16 }, }, 339 #endif 340 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 341 { NULL } 342 }; 343 344 static int 345 e500_cngetc(dev_t dv) 346 { 347 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 348 349 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 350 return -1; 351 352 return com0addr[com_data] & 0xff; 353 } 354 355 static void 356 e500_cnputc(dev_t dv, int c) 357 { 358 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 359 int timo = 150000; 360 361 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 362 ; 363 364 com0addr[com_data] = c; 365 __asm("mbar"); 366 367 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 368 ; 369 } 370 371 static void * 372 gur_tlb_mapiodev(paddr_t pa, psize_t len) 373 { 374 if (pa < gur_bst.pbs_offset) 375 return NULL; 376 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 377 return NULL; 378 return (void *)pa; 379 } 380 381 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 382 383 static void 384 e500_cpu_reset(void) 385 { 386 __asm volatile("sync"); 387 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 388 __asm volatile("msync;isync"); 389 } 390 391 static psize_t 392 memprobe(vaddr_t endkernel) 393 { 394 phys_ram_seg_t *mr; 395 paddr_t boot_page = cpu_read_4(GUR_BPTR); 396 printf(" bptr=%"PRIxPADDR, boot_page); 397 if (boot_page & BPTR_EN) { 398 /* 399 * shift it to an address 400 */ 401 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 402 } else { 403 boot_page = ~(paddr_t)0; 404 } 405 406 /* 407 * First we need to find out how much physical memory we have. 408 * We could let our bootloader tell us, but it's almost as easy 409 * to ask the DDR memory controller. 410 */ 411 mr = physmemr; 412 #if 1 413 for (u_int i = 0; i < 4; i++) { 414 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 415 if (v & CS_CONFIG_EN) { 416 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 417 if (v == 0) 418 continue; 419 mr->start = BNDS_SA_GET(v); 420 mr->size = BNDS_SIZE_GET(v); 421 #if 0 422 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 423 mr - physmemr, mr->size, mr->start); 424 #endif 425 mr++; 426 } 427 } 428 429 if (mr == physmemr) 430 panic("no memory configured!"); 431 #else 432 mr->start = 0; 433 mr->size = 32 << 20; 434 mr++; 435 #endif 436 437 /* 438 * Sort memory regions from low to high and coalesce adjacent regions 439 */ 440 u_int cnt = mr - physmemr; 441 if (cnt > 1) { 442 for (u_int i = 0; i < cnt - 1; i++) { 443 for (u_int j = i + 1; j < cnt; j++) { 444 if (physmemr[j].start < physmemr[i].start) { 445 phys_ram_seg_t tmp = physmemr[i]; 446 physmemr[i] = physmemr[j]; 447 physmemr[j] = tmp; 448 } 449 } 450 } 451 mr = physmemr; 452 for (u_int i = 0; i < cnt; i++, mr++) { 453 if (mr->start + mr->size == mr[1].start) { 454 mr->size += mr[1].size; 455 for (u_int j = 1; j < cnt - i; j++) 456 mr[j] = mr[j+1]; 457 cnt--; 458 } 459 } 460 } 461 462 /* 463 * Copy physical memory to available memory. 464 */ 465 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 466 467 /* 468 * Adjust available memory to skip kernel at start of memory. 469 */ 470 availmemr[0].size -= endkernel - availmemr[0].start; 471 availmemr[0].start = endkernel; 472 473 mr = availmemr; 474 for (u_int i = 0; i < cnt; i++, mr++) { 475 /* 476 * U-boot reserves a boot-page on multi-core chips. 477 * We need to make sure that we never disturb it. 478 */ 479 const paddr_t mr_end = mr->start + mr->size; 480 if (mr_end > boot_page && boot_page >= mr->start) { 481 /* 482 * Normally u-boot will put in at the end 483 * of memory. But in case it doesn't, deal 484 * with all possibilities. 485 */ 486 if (boot_page + PAGE_SIZE == mr_end) { 487 mr->size -= PAGE_SIZE; 488 } else if (boot_page == mr->start) { 489 mr->start += PAGE_SIZE; 490 mr->size -= PAGE_SIZE; 491 } else { 492 mr->size = boot_page - mr->start; 493 mr++; 494 for (u_int j = cnt; j > i + 1; j--) { 495 availmemr[j] = availmemr[j-1]; 496 } 497 cnt++; 498 mr->start = boot_page + PAGE_SIZE; 499 mr->size = mr_end - mr->start; 500 } 501 break; 502 } 503 } 504 505 /* 506 * Steal pages at the end of memory for the kernel message buffer. 507 */ 508 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 509 msgbuf_paddr = 510 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 511 512 /* 513 * Calculate physmem. 514 */ 515 for (u_int i = 0; i < cnt; i++) 516 physmem += atop(physmemr[i].size); 517 518 nmemr = cnt; 519 return physmemr[cnt-1].start + physmemr[cnt-1].size; 520 } 521 522 void 523 consinit(void) 524 { 525 static bool attached = false; 526 527 if (attached) 528 return; 529 attached = true; 530 531 if (comcnfreq == -1) { 532 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 533 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 534 comcnfreq = e500_sys_clk * plat_ratio; 535 printf(" comcnfreq=%u", comcnfreq); 536 } 537 538 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 539 COM_TYPE_NORMAL, comcnmode); 540 } 541 542 void 543 cpu_probe_cache(void) 544 { 545 struct cpu_info * const ci = curcpu(); 546 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 547 548 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 549 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 550 551 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 552 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 553 554 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 555 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 556 } else { 557 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 558 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 559 } 560 561 #ifdef DEBUG 562 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 563 if ((L1CSR_CE & l1csr0) == 0) 564 printf(" DC=off"); 565 566 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 567 if ((L1CSR_CE & l1csr1) == 0) 568 printf(" IC=off"); 569 #endif 570 } 571 572 static uint16_t 573 getsvr(void) 574 { 575 uint16_t svr = mfspr(SPR_SVR) >> 16; 576 577 svr &= ~0x8; /* clear security bit */ 578 switch (svr) { 579 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 580 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 581 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 582 default: return svr; 583 } 584 } 585 586 static const char * 587 socname(uint32_t svr) 588 { 589 svr &= ~0x80000; /* clear security bit */ 590 switch (svr >> 8) { 591 case SVR_MPC8533 >> 8: return "MPC8533"; 592 case SVR_MPC8536v1 >> 8: return "MPC8536"; 593 case SVR_MPC8541v1 >> 8: return "MPC8541"; 594 case SVR_MPC8543v2 >> 8: return "MPC8543"; 595 case SVR_MPC8544v1 >> 8: return "MPC8544"; 596 case SVR_MPC8545v2 >> 8: return "MPC8545"; 597 case SVR_MPC8547v2 >> 8: return "MPC8547"; 598 case SVR_MPC8548v2 >> 8: return "MPC8548"; 599 case SVR_MPC8555v1 >> 8: return "MPC8555"; 600 case SVR_MPC8568v1 >> 8: return "MPC8568"; 601 case SVR_MPC8567v1 >> 8: return "MPC8567"; 602 case SVR_MPC8572v1 >> 8: return "MPC8572"; 603 case SVR_P2020v2 >> 8: return "P2020"; 604 case SVR_P2010v2 >> 8: return "P2010"; 605 default: 606 panic("%s: unknown SVR %#x", __func__, svr); 607 } 608 } 609 610 static void 611 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 612 { 613 static const char units[16] = "KKKKKMMMMMGGGGGT"; 614 615 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 616 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 617 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 618 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 619 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 620 621 aprint_normal_dev(self, "%s:", name); 622 623 aprint_normal(" %u", nentries); 624 if (TLBCFG_AVAIL_P(tlbcfg)) { 625 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 626 minsize, maxsize, units[maxsize_log4k]); 627 } else { 628 aprint_normal(" fixed-size (%uKB)", minsize); 629 } 630 if (assoc == 0 || assoc == nentries) 631 aprint_normal(" fully"); 632 else 633 aprint_normal(" %u-way set", assoc); 634 aprint_normal(" associative entries\n"); 635 } 636 637 static void 638 e500_cpu_attach(device_t self, u_int instance) 639 { 640 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 641 642 if (instance > 1) { 643 #ifdef MULTIPROCESSOR 644 #error still needs to be written 645 ci->ci_idepth = -1; 646 cpu_probe_cache(); 647 #else 648 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 649 return; 650 #endif 651 } 652 653 self->dv_private = ci; 654 655 ci->ci_cpuid = instance - (instance > 0); 656 ci->ci_dev = self; 657 //ci->ci_idlespin = cpu_idlespin; 658 uint64_t freq = board_info_get_number("processor-frequency"); 659 660 char freqbuf[10]; 661 if (freq >= 999500000) { 662 const uint32_t freq32 = (freq + 500000) / 10000000; 663 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 664 freq32 / 100, freq32 % 100); 665 } else { 666 const uint32_t freq32 = (freq + 500000) / 1000000; 667 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 668 } 669 670 const uint32_t pvr = mfpvr(); 671 const uint32_t svr = mfspr(SPR_SVR); 672 const uint32_t pir = mfspr(SPR_PIR); 673 674 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 675 "ID %u%s\n", 676 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 677 (svr >> 4) & 15, svr & 15, 678 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 679 (pvr >> 4) & 15, pvr & 15, 680 pir, (pir == 0 ? " (Primary)" : "")); 681 682 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 683 aprint_normal_dev(self, 684 "%uKB/%uB %u-way L1 %s cache\n", 685 L1CFG_CSIZE_GET(l1cfg0) >> 10, 686 32 << L1CFG_CBSIZE_GET(l1cfg0), 687 L1CFG_CNWAY_GET(l1cfg0), 688 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 689 ? "data" : "unified"); 690 691 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 692 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 693 aprint_normal_dev(self, 694 "%uKB/%uB %u-way L1 %s cache\n", 695 L1CFG_CSIZE_GET(l1cfg1) >> 10, 696 32 << L1CFG_CBSIZE_GET(l1cfg1), 697 L1CFG_CNWAY_GET(l1cfg1), 698 "instruction"); 699 } 700 701 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 702 aprint_normal_dev(self, 703 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 704 MMUCFG_NTLBS_GET(mmucfg) + 1, 705 MMUCFG_NPIDS_GET(mmucfg), 706 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 707 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 708 709 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 710 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 711 712 intr_cpu_attach(ci); 713 cpu_evcnt_attach(ci); 714 715 if (ci == curcpu()) 716 intr_cpu_hatch(ci); 717 } 718 719 void 720 e500_ipi_halt(void) 721 { 722 register_t msr, hid0; 723 724 msr = wrtee(0); 725 726 hid0 = mfspr(SPR_HID0); 727 hid0 = (hid0 & ~HID0_TBEN) | HID0_DOZE; 728 mtspr(SPR_HID0, hid0); 729 730 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 731 mtmsr(msr); 732 for (;;); /* loop forever */ 733 } 734 735 736 static void 737 calltozero(void) 738 { 739 panic("call to 0 from %p", __builtin_return_address(0)); 740 } 741 742 void 743 initppc(vaddr_t startkernel, vaddr_t endkernel) 744 { 745 struct cpu_info * const ci = curcpu(); 746 struct cpu_softc * const cpu = ci->ci_softc; 747 748 cn_tab = &e500_earlycons; 749 printf(" initppc<enter>"); 750 751 const register_t hid0 = mfspr(SPR_HID0); 752 mtspr(SPR_HID0, hid0 | HID0_TBEN | HID0_EMCP); 753 #ifdef CADMUS 754 /* 755 * Need to cache this from cadmus since we need to unmap cadmus since 756 * it falls in the middle of kernel address space. 757 */ 758 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 759 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 760 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 761 printf(" cadmus_pci=%#x", cadmus_pci); 762 printf(" cadmus_csr=%#x", cadmus_csr); 763 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 764 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 765 e500_sys_clk *= 2; 766 } 767 #endif 768 #ifdef PIXIS 769 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 770 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 771 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 772 #ifndef SYS_CLK 773 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 774 #else 775 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 776 #endif 777 #endif 778 printf(" porpllsr=0x%08x", 779 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 780 printf(" sys_clk=%"PRIu64, e500_sys_clk); 781 782 /* 783 * Make sure arguments are page aligned. 784 */ 785 startkernel = trunc_page(startkernel); 786 endkernel = round_page(endkernel); 787 788 /* 789 * Initialize the bus space tag used to access the 85xx general 790 * utility registers. It doesn't need to be extent protected. 791 * We know the GUR is mapped via a TLB1 entry so we add a limited 792 * mapiodev which allows mappings in GUR space. 793 */ 794 CTASSERT(offsetof(struct tlb_md_ops, md_tlb_mapiodev) == 0); 795 cpu_md_ops.md_tlb_ops = (const void *)&early_tlb_mapiodev; 796 bus_space_init(&gur_bst, NULL, NULL, 0); 797 bus_space_init(&gur_le_bst, NULL, NULL, 0); 798 cpu->cpu_bst = &gur_bst; 799 cpu->cpu_le_bst = &gur_le_bst; 800 cpu->cpu_bsh = gur_bsh; 801 802 /* 803 * Attach the console early, really early. 804 */ 805 consinit(); 806 807 /* 808 * Reset the PIC to a known state. 809 */ 810 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 811 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 812 ; 813 #if 0 814 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 815 #endif 816 printf(" openpic-reset(ctpr=%u)", 817 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 818 819 /* 820 * fill in with an absolute branch to a routine that will panic. 821 */ 822 *(int *)0 = 0x48000002 | (int) calltozero; 823 824 /* 825 * Get the cache sizes. 826 */ 827 cpu_probe_cache(); 828 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 829 ci->ci_ci.dcache_size >> 10, 830 ci->ci_ci.dcache_line_size, 831 ci->ci_ci.icache_size >> 10, 832 ci->ci_ci.icache_line_size); 833 834 /* 835 * Now find out how much memory is attached 836 */ 837 pmemsize = memprobe(endkernel); 838 cpu->cpu_highmem = pmemsize; 839 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 840 841 /* 842 * Now we need cleanout the TLB of stuff that we don't need. 843 */ 844 e500_tlb_init(endkernel, pmemsize); 845 printf(" e500_tlbinit(%#lx,%zuMB)", 846 endkernel, (size_t) (pmemsize >> 20)); 847 848 /* 849 * 850 */ 851 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 852 printf(" hid1=%#lx", mfspr(SPR_HID1)); 853 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 854 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 855 856 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 857 858 /* 859 * Initialize the message buffer. 860 */ 861 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 862 printf(" msgbuf=%p", (void *)msgbuf_paddr); 863 864 /* 865 * Initialize exception vectors and interrupts 866 */ 867 exception_init(&e500_intrsw); 868 printf(" exception_init=%p", &e500_intrsw); 869 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 870 871 /* 872 * Set the page size. 873 */ 874 uvm_setpagesize(); 875 876 /* 877 * Initialize the pmap. 878 */ 879 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 880 881 /* 882 * Let's take all the indirect calls via our stubs and patch 883 * them to be direct calls. 884 */ 885 booke_fixup_stubs(); 886 #if 0 887 /* 888 * As a debug measure we can change the TLB entry that maps all of 889 * memory to one that encompasses the 64KB with the kernel vectors. 890 * All other pages will be soft faulted into the TLB as needed. 891 */ 892 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 893 mtspr(SPR_MAS6, 0); 894 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 895 uint32_t mas0 = mfspr(SPR_MAS0); 896 uint32_t mas1 = mfspr(SPR_MAS1); 897 uint32_t mas2 = mfspr(SPR_MAS2); 898 uint32_t mas3 = mfspr(SPR_MAS3); 899 KASSERT(mas3 & MAS3_SW); 900 KASSERT(mas3 & MAS3_SR); 901 KASSERT(mas3 & MAS3_SX); 902 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 903 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 904 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 905 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 906 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 907 #if 1 908 mtspr(SPR_MAS1, mas1); 909 mtspr(SPR_MAS2, mas2); 910 mtspr(SPR_MAS3, mas3); 911 extern void tlbwe(void); 912 tlbwe(); 913 mtspr(SPR_MAS0, saved_mas0); 914 printf("(ok)"); 915 #endif 916 #endif 917 918 /* 919 * Set some more MD helpers 920 */ 921 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 922 cpu_md_ops.md_device_register = e500_device_register; 923 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 924 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 925 #if NGPIO > 0 926 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 927 #endif 928 929 printf(" initppc done!\n"); 930 } 931 932 #ifdef MPC8548 933 static const char * const mpc8548cds_extirq_names[] = { 934 [0] = "pci inta", 935 [1] = "pci intb", 936 [2] = "pci intc", 937 [3] = "pci intd", 938 [4] = "irq4", 939 [5] = "gige phy", 940 [6] = "atm phy", 941 [7] = "cpld", 942 [8] = "irq8", 943 [9] = "nvram", 944 [10] = "debug", 945 [11] = "pci2 inta", 946 }; 947 #endif 948 949 static const char * const mpc85xx_extirq_names[] = { 950 [0] = "extirq 0", 951 [1] = "extirq 1", 952 [2] = "extirq 2", 953 [3] = "extirq 3", 954 [4] = "extirq 4", 955 [5] = "extirq 5", 956 [6] = "extirq 6", 957 [7] = "extirq 7", 958 [8] = "extirq 8", 959 [9] = "extirq 9", 960 [10] = "extirq 10", 961 [11] = "extirq 11", 962 }; 963 964 static void 965 mpc85xx_extirq_setup(void) 966 { 967 #ifdef MPC8548 968 const char * const * names = mpc8548cds_extirq_names; 969 const size_t n = __arraycount(mpc8548cds_extirq_names); 970 #else 971 const char * const * names = mpc85xx_extirq_names; 972 const size_t n = __arraycount(mpc85xx_extirq_names); 973 #endif 974 prop_array_t extirqs = prop_array_create_with_capacity(n); 975 for (u_int i = 0; i < n; i++) { 976 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 977 prop_array_set(extirqs, i, ps); 978 prop_object_release(ps); 979 } 980 board_info_add_object("external-irqs", extirqs); 981 prop_object_release(extirqs); 982 } 983 984 static void 985 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 986 { 987 prop_dictionary_t pci_intmap = prop_dictionary_create(); 988 KASSERT(pci_intmap != NULL); 989 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 990 KASSERT(mask != NULL); 991 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 992 prop_object_release(mask); 993 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 994 KASSERT(pn_ist != NULL); 995 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 996 KASSERT(pn_intr != NULL); 997 prop_dictionary_t entry = prop_dictionary_create(); 998 KASSERT(entry != NULL); 999 prop_dictionary_set(entry, "interrupt", pn_intr); 1000 prop_dictionary_set(entry, "type", pn_ist); 1001 prop_dictionary_set(pci_intmap, "000000", entry); 1002 prop_object_release(pn_intr); 1003 prop_object_release(entry); 1004 va_list ap; 1005 va_start(ap, inta); 1006 u_int intrinc = __LOWEST_SET_BIT(intmask); 1007 for (u_int i = 0; i < intmask; i += intrinc) { 1008 char prop_name[12]; 1009 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1010 entry = prop_dictionary_create(); 1011 KASSERT(entry != NULL); 1012 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1013 KASSERT(pn_intr != NULL); 1014 prop_dictionary_set(entry, "interrupt", pn_intr); 1015 prop_dictionary_set(entry, "type", pn_ist); 1016 prop_dictionary_set(pci_intmap, prop_name, entry); 1017 prop_object_release(pn_intr); 1018 prop_object_release(entry); 1019 } 1020 va_end(ap); 1021 prop_object_release(pn_ist); 1022 board_info_add_object(name, pci_intmap); 1023 prop_object_release(pci_intmap); 1024 } 1025 1026 void 1027 cpu_startup(void) 1028 { 1029 struct cpu_info * const ci = curcpu(); 1030 const uint16_t svr = getsvr(); 1031 1032 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1033 1034 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1035 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1036 uint32_t e500_ratio = E500_RATIO_GET(v); 1037 1038 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1039 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1040 1041 ci->ci_khz = (cpu_freq + 500) / 1000; 1042 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1043 1044 board_info_add_number("my-id", svr); 1045 board_info_add_bool("pq3"); 1046 board_info_add_number("mem-size", pmemsize); 1047 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1048 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1049 uint32_t l2banks = l2siz >> 16; 1050 #ifdef MPC85555 1051 if (svr == (MPC8555v1 >> 16)) { 1052 l2siz >>= 1; 1053 l2banks >>= 1; 1054 } 1055 #endif 1056 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1057 if (boot_page & BPTR_EN) { 1058 bool found = false; 1059 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1060 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1061 * const bp = (void *)boot_page; 1062 bp <= dp; dp--) { 1063 if (*dp == boot_page) { 1064 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1065 spinup_table_addr = 1066 roundup2(spinup_table_addr, 32); 1067 board_info_add_number("mp-boot-page", 1068 boot_page); 1069 board_info_add_number("mp-spin-up-table", 1070 spinup_table_addr); 1071 printf("Found MP boot page @ %#"PRIxPADDR". " 1072 "Spin-up table @ %#"PRIxPTR"\n", 1073 boot_page, spinup_table_addr); 1074 found = true; 1075 break; 1076 } 1077 } 1078 if (!found) 1079 printf("Found MP boot page @ %#"PRIxPADDR 1080 " with missing U-boot signature!\n", boot_page); 1081 } 1082 board_info_add_number("l2-cache-size", l2siz); 1083 board_info_add_number("l2-cache-line-size", 32); 1084 board_info_add_number("l2-cache-banks", l2banks); 1085 board_info_add_number("l2-cache-ways", 8); 1086 1087 board_info_add_number("processor-frequency", cpu_freq); 1088 board_info_add_number("bus-frequency", ccb_freq); 1089 board_info_add_number("pci-frequency", e500_sys_clk); 1090 board_info_add_number("timebase-frequency", ccb_freq / 8); 1091 1092 #ifdef CADMUS 1093 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1094 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1095 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1096 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1097 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1098 #else 1099 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1100 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1101 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1102 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1103 #endif 1104 1105 uint64_t macstnaddr = 1106 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1107 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1108 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1109 1110 #if NPCI > 0 && defined(PCI_MEMBASE) 1111 pcimem_ex = extent_create("pcimem", 1112 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1113 M_DEVBUF, NULL, 0, EX_WAITOK); 1114 #endif 1115 #if NPCI > 0 && defined(PCI_IOBASE) 1116 pciio_ex = extent_create("pciio", 1117 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1118 M_DEVBUF, NULL, 0, EX_WAITOK); 1119 #endif 1120 mpc85xx_extirq_setup(); 1121 /* 1122 * PCI-Express virtual wire interrupts on combined with 1123 * External IRQ0/1/2/3. 1124 */ 1125 switch (svr) { 1126 #if defined(MPC8548) 1127 case SVR_MPC8548v1 >> 16: 1128 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1129 IST_LEVEL, 0, 1, 2, 3); 1130 break; 1131 #endif 1132 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1133 case SVR_MPC8536v1 >> 16: 1134 case SVR_MPC8544v1 >> 16: 1135 case SVR_MPC8572v1 >> 16: 1136 case SVR_P2010v2 >> 16: 1137 case SVR_P2020v2 >> 16: 1138 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1139 0, 1, 2, 3); 1140 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1141 4, 5, 6, 7); 1142 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1143 8, 9, 10, 11); 1144 break; 1145 #endif 1146 } 1147 switch (svr) { 1148 #if defined(MPC8536) 1149 case SVR_MPC8536v1 >> 16: 1150 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1151 1, 2, 3, 4); 1152 break; 1153 #endif 1154 #if defined(MPC8544) 1155 case SVR_MPC8544v1 >> 16: 1156 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1157 0, 1, 2, 3); 1158 break; 1159 #endif 1160 #if defined(MPC8548) 1161 case SVR_MPC8548v1 >> 16: 1162 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1163 0, 1, 2, 3); 1164 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1165 11, 1, 2, 3); 1166 break; 1167 #endif 1168 } 1169 } 1170
Indexes created Wed Oct 22 13:09:56 GMT 2025