machdep.c revision 1.9
1 /* $NetBSD: machdep.c,v 1.9 2011/06/12 04:20:18 mrg Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 #include <sys/module.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <prop/proplib.h> 68 69 #include <machine/stdarg.h> 70 71 #include <dev/cons.h> 72 73 #include <dev/ic/comreg.h> 74 #include <dev/ic/comvar.h> 75 76 #include <net/if.h> 77 #include <net/if_media.h> 78 #include <dev/mii/miivar.h> 79 80 #include <powerpc/pcb.h> 81 #include <powerpc/spr.h> 82 #include <powerpc/booke/spr.h> 83 84 #include <powerpc/booke/cpuvar.h> 85 #include <powerpc/booke/e500reg.h> 86 #include <powerpc/booke/e500var.h> 87 #include <powerpc/booke/etsecreg.h> 88 #include <powerpc/booke/openpicreg.h> 89 #ifdef CADMUS 90 #include <evbppc/mpc85xx/cadmusreg.h> 91 #endif 92 #ifdef PIXIS 93 #include <evbppc/mpc85xx/pixisreg.h> 94 #endif 95 96 /* 97 * booke kernels need to set module_machine to this for modules to work. 98 */ 99 char module_machine_booke[] = "powerpc-booke"; 100 101 void initppc(vaddr_t, vaddr_t); 102 103 #define MEMREGIONS 4 104 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 105 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 106 static u_int nmemr; 107 108 #ifndef CONSFREQ 109 # define CONSFREQ -1 /* inherit from firmware */ 110 #endif 111 #ifndef CONSPEED 112 # define CONSPEED 115200 113 #endif 114 #ifndef CONMODE 115 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 116 #endif 117 #ifndef CONSADDR 118 # define CONSADDR DUART2_BASE 119 #endif 120 121 int comcnfreq = CONSFREQ; 122 int comcnspeed = CONSPEED; 123 tcflag_t comcnmode = CONMODE; 124 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 125 126 #if NPCI > 0 127 struct extent *pcimem_ex; 128 struct extent *pciio_ex; 129 #endif 130 131 struct powerpc_bus_space gur_bst = { 132 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 133 .pbs_offset = GUR_BASE, 134 .pbs_limit = GUR_SIZE, 135 }; 136 137 struct powerpc_bus_space gur_le_bst = { 138 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 139 .pbs_offset = GUR_BASE, 140 .pbs_limit = GUR_SIZE, 141 }; 142 143 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 144 145 #if defined(SYS_CLK) 146 static uint64_t e500_sys_clk = SYS_CLK; 147 #endif 148 #ifdef CADMUS 149 static uint8_t cadmus_pci; 150 static uint8_t cadmus_csr; 151 #ifndef SYS_CLK 152 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 153 #endif 154 #elif defined(PIXIS) 155 static const uint32_t pixis_spd_map[8] = { 156 [PX_SPD_33MHZ] = 33333333, 157 [PX_SPD_40MHZ] = 40000000, 158 [PX_SPD_50MHZ] = 50000000, 159 [PX_SPD_66MHZ] = 66666666, 160 [PX_SPD_83MHZ] = 83333333, 161 [PX_SPD_100MHZ] = 100000000, 162 [PX_SPD_133MHZ] = 133333333, 163 [PX_SPD_166MHZ] = 166666667, 164 }; 165 static uint8_t pixis_spd; 166 #ifndef SYS_CLK 167 static uint64_t e500_sys_clk; 168 #endif 169 #elif !defined(SYS_CLK) 170 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 171 #endif 172 173 static int e500_cngetc(dev_t); 174 static void e500_cnputc(dev_t, int); 175 176 static struct consdev e500_earlycons = { 177 .cn_getc = e500_cngetc, 178 .cn_putc = e500_cnputc, 179 .cn_pollc = nullcnpollc, 180 }; 181 182 /* 183 * List of port-specific devices to attach to the processor local bus. 184 */ 185 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 186 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 187 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 188 #if defined(MPC8572) || defined(P2020) 189 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 190 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 191 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 192 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 193 #endif 194 { "wdog" }, /* not a real device */ 195 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 196 1, { ISOURCE_DUART }, 197 1 + ilog2(DEVDISR_DUART) }, 198 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 199 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 200 1 + ilog2(DEVDISR_TSEC1) }, 201 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 202 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 203 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 204 1 + ilog2(DEVDISR_TSEC2), 205 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 206 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 207 #endif 208 #if defined(MPC8544) || defined(MPC8536) 209 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 210 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 211 1 + ilog2(DEVDISR_TSEC3), 212 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 213 #endif 214 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 215 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 216 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 217 1 + ilog2(DEVDISR_TSEC3), 218 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 219 SVR_P2020v2 >> 16 } }, 220 #endif 221 #if defined(MPC8548) || defined(MPC8572) 222 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 223 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 224 1 + ilog2(DEVDISR_TSEC4), 225 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 226 #endif 227 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 228 1, { ISOURCE_I2C }, 229 1 + ilog2(DEVDISR_I2C) }, 230 /* MPC8572 doesn't have any GPIO */ 231 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 232 1, { ISOURCE_GPIO }, 233 0, 234 { 0xffff, SVR_MPC8572v1 >> 16 } }, 235 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 236 1, { ISOURCE_DDR }, 237 1 + ilog2(DEVDISR_DDR_15), 238 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 239 #if defined(MPC8536) 240 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 241 1, { ISOURCE_DDR }, 242 1 + ilog2(DEVDISR_DDR_16), 243 { SVR_MPC8536v1 >> 16 } }, 244 #endif 245 #if defined(MPC8572) 246 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 247 1, { ISOURCE_DDR }, 248 1 + ilog2(DEVDISR_DDR_15), 249 { SVR_MPC8572v1 >> 16 } }, 250 { "ddrc", DDRC1_BASE, DDRC_SIZE, 2, 251 1, { ISOURCE_DDR }, 252 1 + ilog2(DEVDISR_DDR2_14), 253 { SVR_MPC8572v1 >> 16 } }, 254 #endif 255 { "lbc", LBC_BASE, LBC_SIZE, 0, 256 1, { ISOURCE_LBC }, 257 1 + ilog2(DEVDISR_LBC) }, 258 #if defined(MPC8544) || defined(MPC8536) 259 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 260 1, { ISOURCE_PCIEX }, 261 1 + ilog2(DEVDISR_PCIE), 262 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 263 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 264 1, { ISOURCE_PCIEX2 }, 265 1 + ilog2(DEVDISR_PCIE2), 266 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 267 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 268 1, { ISOURCE_PCIEX3 }, 269 1 + ilog2(DEVDISR_PCIE3), 270 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 271 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 272 1, { ISOURCE_PCI1 }, 273 1 + ilog2(DEVDISR_PCI1), 274 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 275 #endif 276 #ifdef MPC8548 277 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 278 1, { ISOURCE_PCIEX }, 279 1 + ilog2(DEVDISR_PCIE), 280 { SVR_MPC8548v1 >> 16 }, }, 281 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 282 1, { ISOURCE_PCI1 }, 283 1 + ilog2(DEVDISR_PCI1), 284 { SVR_MPC8548v1 >> 16 }, }, 285 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 286 1, { ISOURCE_PCI2 }, 287 1 + ilog2(DEVDISR_PCI2), 288 { SVR_MPC8548v1 >> 16 }, }, 289 #endif 290 #if defined(MPC8572) || defined(P2020) 291 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 292 1, { ISOURCE_PCIEX }, 293 1 + ilog2(DEVDISR_PCIE), 294 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 295 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 296 1, { ISOURCE_PCIEX2 }, 297 1 + ilog2(DEVDISR_PCIE2), 298 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 299 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 300 1, { ISOURCE_PCIEX3_MPC8572 }, 301 1 + ilog2(DEVDISR_PCIE3), 302 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 303 #endif 304 #if defined(MPC8536) || defined(P2020) 305 { "ehci", USB1_BASE, USB_SIZE, 1, 306 1, { ISOURCE_USB1 }, 307 1 + ilog2(DEVDISR_USB1), 308 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 309 #endif 310 #ifdef MPC8536 311 { "ehci", USB2_BASE, USB_SIZE, 2, 312 1, { ISOURCE_USB2 }, 313 1 + ilog2(DEVDISR_USB2), 314 { SVR_MPC8536v1 >> 16 }, }, 315 { "ehci", USB3_BASE, USB_SIZE, 3, 316 1, { ISOURCE_USB3 }, 317 1 + ilog2(DEVDISR_USB3), 318 { SVR_MPC8536v1 >> 16 }, }, 319 { "sata", SATA1_BASE, SATA_SIZE, 1, 320 1, { ISOURCE_SATA1 }, 321 1 + ilog2(DEVDISR_SATA1), 322 { SVR_MPC8536v1 >> 16 }, }, 323 { "sata", SATA2_BASE, SATA_SIZE, 2, 324 1, { ISOURCE_SATA2 }, 325 1 + ilog2(DEVDISR_SATA2), 326 { SVR_MPC8536v1 >> 16 }, }, 327 { "spi", SPI_BASE, SPI_SIZE, 0, 328 1, { ISOURCE_SPI }, 329 1 + ilog2(DEVDISR_SPI_15), 330 { SVR_MPC8536v1 >> 16 }, }, 331 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 332 1, { ISOURCE_ESDHC }, 333 1 + ilog2(DEVDISR_ESDHC_12), 334 { SVR_MPC8536v1 >> 16 }, }, 335 #endif 336 #if defined(P2020) 337 { "spi", SPI_BASE, SPI_SIZE, 0, 338 1, { ISOURCE_SPI }, 339 1 + ilog2(DEVDISR_SPI_28), 340 { SVR_P2020v2 >> 16 }, }, 341 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 342 1, { ISOURCE_ESDHC }, 343 1 + ilog2(DEVDISR_ESDHC_10), 344 { SVR_P2020v2 >> 16 }, }, 345 #endif 346 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 347 { NULL } 348 }; 349 350 static int 351 e500_cngetc(dev_t dv) 352 { 353 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 354 355 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 356 return -1; 357 358 return com0addr[com_data] & 0xff; 359 } 360 361 static void 362 e500_cnputc(dev_t dv, int c) 363 { 364 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 365 int timo = 150000; 366 367 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 368 ; 369 370 com0addr[com_data] = c; 371 __asm("mbar"); 372 373 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 374 ; 375 } 376 377 static void * 378 gur_tlb_mapiodev(paddr_t pa, psize_t len) 379 { 380 if (pa < gur_bst.pbs_offset) 381 return NULL; 382 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 383 return NULL; 384 return (void *)pa; 385 } 386 387 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 388 389 static void 390 e500_cpu_reset(void) 391 { 392 __asm volatile("sync"); 393 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 394 __asm volatile("msync;isync"); 395 } 396 397 static psize_t 398 memprobe(vaddr_t endkernel) 399 { 400 phys_ram_seg_t *mr; 401 paddr_t boot_page = cpu_read_4(GUR_BPTR); 402 printf(" bptr=%"PRIxPADDR, boot_page); 403 if (boot_page & BPTR_EN) { 404 /* 405 * shift it to an address 406 */ 407 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 408 } else { 409 boot_page = ~(paddr_t)0; 410 } 411 412 /* 413 * First we need to find out how much physical memory we have. 414 * We could let our bootloader tell us, but it's almost as easy 415 * to ask the DDR memory controller. 416 */ 417 mr = physmemr; 418 #if 1 419 for (u_int i = 0; i < 4; i++) { 420 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 421 if (v & CS_CONFIG_EN) { 422 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 423 if (v == 0) 424 continue; 425 mr->start = BNDS_SA_GET(v); 426 mr->size = BNDS_SIZE_GET(v); 427 #if 0 428 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 429 mr - physmemr, mr->size, mr->start); 430 #endif 431 mr++; 432 } 433 } 434 435 if (mr == physmemr) 436 panic("no memory configured!"); 437 #else 438 mr->start = 0; 439 mr->size = 32 << 20; 440 mr++; 441 #endif 442 443 /* 444 * Sort memory regions from low to high and coalesce adjacent regions 445 */ 446 u_int cnt = mr - physmemr; 447 if (cnt > 1) { 448 for (u_int i = 0; i < cnt - 1; i++) { 449 for (u_int j = i + 1; j < cnt; j++) { 450 if (physmemr[j].start < physmemr[i].start) { 451 phys_ram_seg_t tmp = physmemr[i]; 452 physmemr[i] = physmemr[j]; 453 physmemr[j] = tmp; 454 } 455 } 456 } 457 mr = physmemr; 458 for (u_int i = 0; i < cnt; i++, mr++) { 459 if (mr->start + mr->size == mr[1].start) { 460 mr->size += mr[1].size; 461 for (u_int j = 1; j < cnt - i; j++) 462 mr[j] = mr[j+1]; 463 cnt--; 464 } 465 } 466 } 467 468 /* 469 * Copy physical memory to available memory. 470 */ 471 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 472 473 /* 474 * Adjust available memory to skip kernel at start of memory. 475 */ 476 availmemr[0].size -= endkernel - availmemr[0].start; 477 availmemr[0].start = endkernel; 478 479 mr = availmemr; 480 for (u_int i = 0; i < cnt; i++, mr++) { 481 /* 482 * U-boot reserves a boot-page on multi-core chips. 483 * We need to make sure that we never disturb it. 484 */ 485 const paddr_t mr_end = mr->start + mr->size; 486 if (mr_end > boot_page && boot_page >= mr->start) { 487 /* 488 * Normally u-boot will put in at the end 489 * of memory. But in case it doesn't, deal 490 * with all possibilities. 491 */ 492 if (boot_page + PAGE_SIZE == mr_end) { 493 mr->size -= PAGE_SIZE; 494 } else if (boot_page == mr->start) { 495 mr->start += PAGE_SIZE; 496 mr->size -= PAGE_SIZE; 497 } else { 498 mr->size = boot_page - mr->start; 499 mr++; 500 for (u_int j = cnt; j > i + 1; j--) { 501 availmemr[j] = availmemr[j-1]; 502 } 503 cnt++; 504 mr->start = boot_page + PAGE_SIZE; 505 mr->size = mr_end - mr->start; 506 } 507 break; 508 } 509 } 510 511 /* 512 * Steal pages at the end of memory for the kernel message buffer. 513 */ 514 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 515 msgbuf_paddr = 516 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 517 518 /* 519 * Calculate physmem. 520 */ 521 for (u_int i = 0; i < cnt; i++) 522 physmem += atop(physmemr[i].size); 523 524 nmemr = cnt; 525 return physmemr[cnt-1].start + physmemr[cnt-1].size; 526 } 527 528 void 529 consinit(void) 530 { 531 static bool attached = false; 532 533 if (attached) 534 return; 535 attached = true; 536 537 if (comcnfreq == -1) { 538 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 539 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 540 comcnfreq = e500_sys_clk * plat_ratio; 541 printf(" comcnfreq=%u", comcnfreq); 542 } 543 544 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 545 COM_TYPE_NORMAL, comcnmode); 546 } 547 548 void 549 cpu_probe_cache(void) 550 { 551 struct cpu_info * const ci = curcpu(); 552 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 553 554 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 555 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 556 557 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 558 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 559 560 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 561 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 562 } else { 563 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 564 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 565 } 566 567 #ifdef DEBUG 568 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 569 if ((L1CSR_CE & l1csr0) == 0) 570 printf(" DC=off"); 571 572 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 573 if ((L1CSR_CE & l1csr1) == 0) 574 printf(" IC=off"); 575 #endif 576 } 577 578 static uint16_t 579 getsvr(void) 580 { 581 uint16_t svr = mfspr(SPR_SVR) >> 16; 582 583 svr &= ~0x8; /* clear security bit */ 584 switch (svr) { 585 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 586 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 587 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 588 default: return svr; 589 } 590 } 591 592 static const char * 593 socname(uint32_t svr) 594 { 595 svr &= ~0x80000; /* clear security bit */ 596 switch (svr >> 8) { 597 case SVR_MPC8533 >> 8: return "MPC8533"; 598 case SVR_MPC8536v1 >> 8: return "MPC8536"; 599 case SVR_MPC8541v1 >> 8: return "MPC8541"; 600 case SVR_MPC8543v2 >> 8: return "MPC8543"; 601 case SVR_MPC8544v1 >> 8: return "MPC8544"; 602 case SVR_MPC8545v2 >> 8: return "MPC8545"; 603 case SVR_MPC8547v2 >> 8: return "MPC8547"; 604 case SVR_MPC8548v2 >> 8: return "MPC8548"; 605 case SVR_MPC8555v1 >> 8: return "MPC8555"; 606 case SVR_MPC8568v1 >> 8: return "MPC8568"; 607 case SVR_MPC8567v1 >> 8: return "MPC8567"; 608 case SVR_MPC8572v1 >> 8: return "MPC8572"; 609 case SVR_P2020v2 >> 8: return "P2020"; 610 case SVR_P2010v2 >> 8: return "P2010"; 611 default: 612 panic("%s: unknown SVR %#x", __func__, svr); 613 } 614 } 615 616 static void 617 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 618 { 619 static const char units[16] = "KKKKKMMMMMGGGGGT"; 620 621 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 622 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 623 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 624 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 625 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 626 627 aprint_normal_dev(self, "%s:", name); 628 629 aprint_normal(" %u", nentries); 630 if (TLBCFG_AVAIL_P(tlbcfg)) { 631 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 632 minsize, maxsize, units[maxsize_log4k]); 633 } else { 634 aprint_normal(" fixed-size (%uKB)", minsize); 635 } 636 if (assoc == 0 || assoc == nentries) 637 aprint_normal(" fully"); 638 else 639 aprint_normal(" %u-way set", assoc); 640 aprint_normal(" associative entries\n"); 641 } 642 643 static void 644 e500_cpu_attach(device_t self, u_int instance) 645 { 646 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 647 648 if (instance > 1) { 649 #ifdef MULTIPROCESSOR 650 #error still needs to be written 651 ci->ci_idepth = -1; 652 cpu_probe_cache(); 653 #else 654 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 655 return; 656 #endif 657 } 658 659 self->dv_private = ci; 660 661 ci->ci_cpuid = instance - (instance > 0); 662 ci->ci_dev = self; 663 //ci->ci_idlespin = cpu_idlespin; 664 uint64_t freq = board_info_get_number("processor-frequency"); 665 666 char freqbuf[10]; 667 if (freq >= 999500000) { 668 const uint32_t freq32 = (freq + 500000) / 10000000; 669 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 670 freq32 / 100, freq32 % 100); 671 } else { 672 const uint32_t freq32 = (freq + 500000) / 1000000; 673 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 674 } 675 676 const uint32_t pvr = mfpvr(); 677 const uint32_t svr = mfspr(SPR_SVR); 678 const uint32_t pir = mfspr(SPR_PIR); 679 680 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 681 "ID %u%s\n", 682 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 683 (svr >> 4) & 15, svr & 15, 684 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 685 (pvr >> 4) & 15, pvr & 15, 686 pir, (pir == 0 ? " (Primary)" : "")); 687 688 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 689 aprint_normal_dev(self, 690 "%uKB/%uB %u-way L1 %s cache\n", 691 L1CFG_CSIZE_GET(l1cfg0) >> 10, 692 32 << L1CFG_CBSIZE_GET(l1cfg0), 693 L1CFG_CNWAY_GET(l1cfg0), 694 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 695 ? "data" : "unified"); 696 697 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 698 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 699 aprint_normal_dev(self, 700 "%uKB/%uB %u-way L1 %s cache\n", 701 L1CFG_CSIZE_GET(l1cfg1) >> 10, 702 32 << L1CFG_CBSIZE_GET(l1cfg1), 703 L1CFG_CNWAY_GET(l1cfg1), 704 "instruction"); 705 } 706 707 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 708 aprint_normal_dev(self, 709 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 710 MMUCFG_NTLBS_GET(mmucfg) + 1, 711 MMUCFG_NPIDS_GET(mmucfg), 712 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 713 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 714 715 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 716 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 717 718 intr_cpu_attach(ci); 719 cpu_evcnt_attach(ci); 720 721 if (ci == curcpu()) 722 intr_cpu_hatch(ci); 723 } 724 725 void 726 e500_ipi_halt(void) 727 { 728 register_t msr, hid0; 729 730 msr = wrtee(0); 731 732 hid0 = mfspr(SPR_HID0); 733 hid0 = (hid0 & ~HID0_TBEN) | HID0_DOZE; 734 mtspr(SPR_HID0, hid0); 735 736 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 737 mtmsr(msr); 738 for (;;); /* loop forever */ 739 } 740 741 742 static void 743 calltozero(void) 744 { 745 panic("call to 0 from %p", __builtin_return_address(0)); 746 } 747 748 void 749 initppc(vaddr_t startkernel, vaddr_t endkernel) 750 { 751 struct cpu_info * const ci = curcpu(); 752 struct cpu_softc * const cpu = ci->ci_softc; 753 754 cn_tab = &e500_earlycons; 755 printf(" initppc<enter>"); 756 757 const register_t hid0 = mfspr(SPR_HID0); 758 mtspr(SPR_HID0, hid0 | HID0_TBEN | HID0_EMCP); 759 #ifdef CADMUS 760 /* 761 * Need to cache this from cadmus since we need to unmap cadmus since 762 * it falls in the middle of kernel address space. 763 */ 764 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 765 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 766 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 767 printf(" cadmus_pci=%#x", cadmus_pci); 768 printf(" cadmus_csr=%#x", cadmus_csr); 769 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 770 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 771 e500_sys_clk *= 2; 772 } 773 #endif 774 #ifdef PIXIS 775 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 776 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 777 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 778 #ifndef SYS_CLK 779 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 780 #else 781 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 782 #endif 783 #endif 784 printf(" porpllsr=0x%08x", 785 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 786 printf(" sys_clk=%"PRIu64, e500_sys_clk); 787 788 /* 789 * Make sure arguments are page aligned. 790 */ 791 startkernel = trunc_page(startkernel); 792 endkernel = round_page(endkernel); 793 794 /* 795 * Initialize the bus space tag used to access the 85xx general 796 * utility registers. It doesn't need to be extent protected. 797 * We know the GUR is mapped via a TLB1 entry so we add a limited 798 * mapiodev which allows mappings in GUR space. 799 */ 800 CTASSERT(offsetof(struct tlb_md_ops, md_tlb_mapiodev) == 0); 801 cpu_md_ops.md_tlb_ops = (const void *)&early_tlb_mapiodev; 802 bus_space_init(&gur_bst, NULL, NULL, 0); 803 bus_space_init(&gur_le_bst, NULL, NULL, 0); 804 cpu->cpu_bst = &gur_bst; 805 cpu->cpu_le_bst = &gur_le_bst; 806 cpu->cpu_bsh = gur_bsh; 807 808 /* 809 * Attach the console early, really early. 810 */ 811 consinit(); 812 813 /* 814 * Reset the PIC to a known state. 815 */ 816 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 817 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 818 ; 819 #if 0 820 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 821 #endif 822 printf(" openpic-reset(ctpr=%u)", 823 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 824 825 /* 826 * fill in with an absolute branch to a routine that will panic. 827 */ 828 *(int *)0 = 0x48000002 | (int) calltozero; 829 830 /* 831 * Get the cache sizes. 832 */ 833 cpu_probe_cache(); 834 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 835 ci->ci_ci.dcache_size >> 10, 836 ci->ci_ci.dcache_line_size, 837 ci->ci_ci.icache_size >> 10, 838 ci->ci_ci.icache_line_size); 839 840 /* 841 * Now find out how much memory is attached 842 */ 843 pmemsize = memprobe(endkernel); 844 cpu->cpu_highmem = pmemsize; 845 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 846 847 /* 848 * Now we need cleanout the TLB of stuff that we don't need. 849 */ 850 e500_tlb_init(endkernel, pmemsize); 851 printf(" e500_tlbinit(%#lx,%zuMB)", 852 endkernel, (size_t) (pmemsize >> 20)); 853 854 /* 855 * 856 */ 857 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 858 printf(" hid1=%#lx", mfspr(SPR_HID1)); 859 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 860 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 861 862 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 863 864 /* 865 * Initialize the message buffer. 866 */ 867 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 868 printf(" msgbuf=%p", (void *)msgbuf_paddr); 869 870 /* 871 * Initialize exception vectors and interrupts 872 */ 873 exception_init(&e500_intrsw); 874 printf(" exception_init=%p", &e500_intrsw); 875 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 876 877 /* 878 * Set the page size. 879 */ 880 uvm_setpagesize(); 881 882 /* 883 * Initialize the pmap. 884 */ 885 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 886 887 /* 888 * Let's take all the indirect calls via our stubs and patch 889 * them to be direct calls. 890 */ 891 booke_fixup_stubs(); 892 #if 0 893 /* 894 * As a debug measure we can change the TLB entry that maps all of 895 * memory to one that encompasses the 64KB with the kernel vectors. 896 * All other pages will be soft faulted into the TLB as needed. 897 */ 898 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 899 mtspr(SPR_MAS6, 0); 900 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 901 uint32_t mas0 = mfspr(SPR_MAS0); 902 uint32_t mas1 = mfspr(SPR_MAS1); 903 uint32_t mas2 = mfspr(SPR_MAS2); 904 uint32_t mas3 = mfspr(SPR_MAS3); 905 KASSERT(mas3 & MAS3_SW); 906 KASSERT(mas3 & MAS3_SR); 907 KASSERT(mas3 & MAS3_SX); 908 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 909 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 910 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 911 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 912 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 913 #if 1 914 mtspr(SPR_MAS1, mas1); 915 mtspr(SPR_MAS2, mas2); 916 mtspr(SPR_MAS3, mas3); 917 extern void tlbwe(void); 918 tlbwe(); 919 mtspr(SPR_MAS0, saved_mas0); 920 printf("(ok)"); 921 #endif 922 #endif 923 924 /* 925 * Set some more MD helpers 926 */ 927 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 928 cpu_md_ops.md_device_register = e500_device_register; 929 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 930 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 931 #if NGPIO > 0 932 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 933 #endif 934 935 printf(" initppc done!\n"); 936 937 /* 938 * Look for the Book-E modules in the right place. 939 */ 940 module_machine = module_machine_booke; 941 } 942 943 #ifdef MPC8548 944 static const char * const mpc8548cds_extirq_names[] = { 945 [0] = "pci inta", 946 [1] = "pci intb", 947 [2] = "pci intc", 948 [3] = "pci intd", 949 [4] = "irq4", 950 [5] = "gige phy", 951 [6] = "atm phy", 952 [7] = "cpld", 953 [8] = "irq8", 954 [9] = "nvram", 955 [10] = "debug", 956 [11] = "pci2 inta", 957 }; 958 #endif 959 960 static const char * const mpc85xx_extirq_names[] = { 961 [0] = "extirq 0", 962 [1] = "extirq 1", 963 [2] = "extirq 2", 964 [3] = "extirq 3", 965 [4] = "extirq 4", 966 [5] = "extirq 5", 967 [6] = "extirq 6", 968 [7] = "extirq 7", 969 [8] = "extirq 8", 970 [9] = "extirq 9", 971 [10] = "extirq 10", 972 [11] = "extirq 11", 973 }; 974 975 static void 976 mpc85xx_extirq_setup(void) 977 { 978 #ifdef MPC8548 979 const char * const * names = mpc8548cds_extirq_names; 980 const size_t n = __arraycount(mpc8548cds_extirq_names); 981 #else 982 const char * const * names = mpc85xx_extirq_names; 983 const size_t n = __arraycount(mpc85xx_extirq_names); 984 #endif 985 prop_array_t extirqs = prop_array_create_with_capacity(n); 986 for (u_int i = 0; i < n; i++) { 987 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 988 prop_array_set(extirqs, i, ps); 989 prop_object_release(ps); 990 } 991 board_info_add_object("external-irqs", extirqs); 992 prop_object_release(extirqs); 993 } 994 995 static void 996 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 997 { 998 prop_dictionary_t pci_intmap = prop_dictionary_create(); 999 KASSERT(pci_intmap != NULL); 1000 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1001 KASSERT(mask != NULL); 1002 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1003 prop_object_release(mask); 1004 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1005 KASSERT(pn_ist != NULL); 1006 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1007 KASSERT(pn_intr != NULL); 1008 prop_dictionary_t entry = prop_dictionary_create(); 1009 KASSERT(entry != NULL); 1010 prop_dictionary_set(entry, "interrupt", pn_intr); 1011 prop_dictionary_set(entry, "type", pn_ist); 1012 prop_dictionary_set(pci_intmap, "000000", entry); 1013 prop_object_release(pn_intr); 1014 prop_object_release(entry); 1015 va_list ap; 1016 va_start(ap, inta); 1017 u_int intrinc = __LOWEST_SET_BIT(intmask); 1018 for (u_int i = 0; i < intmask; i += intrinc) { 1019 char prop_name[12]; 1020 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1021 entry = prop_dictionary_create(); 1022 KASSERT(entry != NULL); 1023 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1024 KASSERT(pn_intr != NULL); 1025 prop_dictionary_set(entry, "interrupt", pn_intr); 1026 prop_dictionary_set(entry, "type", pn_ist); 1027 prop_dictionary_set(pci_intmap, prop_name, entry); 1028 prop_object_release(pn_intr); 1029 prop_object_release(entry); 1030 } 1031 va_end(ap); 1032 prop_object_release(pn_ist); 1033 board_info_add_object(name, pci_intmap); 1034 prop_object_release(pci_intmap); 1035 } 1036 1037 void 1038 cpu_startup(void) 1039 { 1040 struct cpu_info * const ci = curcpu(); 1041 const uint16_t svr = getsvr(); 1042 1043 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1044 1045 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1046 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1047 uint32_t e500_ratio = E500_RATIO_GET(v); 1048 1049 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1050 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1051 1052 ci->ci_khz = (cpu_freq + 500) / 1000; 1053 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1054 1055 board_info_add_number("my-id", svr); 1056 board_info_add_bool("pq3"); 1057 board_info_add_number("mem-size", pmemsize); 1058 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1059 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1060 uint32_t l2banks = l2siz >> 16; 1061 #ifdef MPC85555 1062 if (svr == (MPC8555v1 >> 16)) { 1063 l2siz >>= 1; 1064 l2banks >>= 1; 1065 } 1066 #endif 1067 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1068 if (boot_page & BPTR_EN) { 1069 bool found = false; 1070 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1071 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1072 * const bp = (void *)boot_page; 1073 bp <= dp; dp--) { 1074 if (*dp == boot_page) { 1075 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1076 spinup_table_addr = 1077 roundup2(spinup_table_addr, 32); 1078 board_info_add_number("mp-boot-page", 1079 boot_page); 1080 board_info_add_number("mp-spin-up-table", 1081 spinup_table_addr); 1082 printf("Found MP boot page @ %#"PRIxPADDR". " 1083 "Spin-up table @ %#"PRIxPTR"\n", 1084 boot_page, spinup_table_addr); 1085 found = true; 1086 break; 1087 } 1088 } 1089 if (!found) 1090 printf("Found MP boot page @ %#"PRIxPADDR 1091 " with missing U-boot signature!\n", boot_page); 1092 } 1093 board_info_add_number("l2-cache-size", l2siz); 1094 board_info_add_number("l2-cache-line-size", 32); 1095 board_info_add_number("l2-cache-banks", l2banks); 1096 board_info_add_number("l2-cache-ways", 8); 1097 1098 board_info_add_number("processor-frequency", cpu_freq); 1099 board_info_add_number("bus-frequency", ccb_freq); 1100 board_info_add_number("pci-frequency", e500_sys_clk); 1101 board_info_add_number("timebase-frequency", ccb_freq / 8); 1102 1103 #ifdef CADMUS 1104 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1105 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1106 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1107 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1108 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1109 #else 1110 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1111 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1112 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1113 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1114 #endif 1115 1116 uint64_t macstnaddr = 1117 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1118 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1119 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1120 1121 #if NPCI > 0 && defined(PCI_MEMBASE) 1122 pcimem_ex = extent_create("pcimem", 1123 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1124 M_DEVBUF, NULL, 0, EX_WAITOK); 1125 #endif 1126 #if NPCI > 0 && defined(PCI_IOBASE) 1127 pciio_ex = extent_create("pciio", 1128 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1129 M_DEVBUF, NULL, 0, EX_WAITOK); 1130 #endif 1131 mpc85xx_extirq_setup(); 1132 /* 1133 * PCI-Express virtual wire interrupts on combined with 1134 * External IRQ0/1/2/3. 1135 */ 1136 switch (svr) { 1137 #if defined(MPC8548) 1138 case SVR_MPC8548v1 >> 16: 1139 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1140 IST_LEVEL, 0, 1, 2, 3); 1141 break; 1142 #endif 1143 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1144 case SVR_MPC8536v1 >> 16: 1145 case SVR_MPC8544v1 >> 16: 1146 case SVR_MPC8572v1 >> 16: 1147 case SVR_P2010v2 >> 16: 1148 case SVR_P2020v2 >> 16: 1149 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1150 0, 1, 2, 3); 1151 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1152 4, 5, 6, 7); 1153 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1154 8, 9, 10, 11); 1155 break; 1156 #endif 1157 } 1158 switch (svr) { 1159 #if defined(MPC8536) 1160 case SVR_MPC8536v1 >> 16: 1161 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1162 1, 2, 3, 4); 1163 break; 1164 #endif 1165 #if defined(MPC8544) 1166 case SVR_MPC8544v1 >> 16: 1167 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1168 0, 1, 2, 3); 1169 break; 1170 #endif 1171 #if defined(MPC8548) 1172 case SVR_MPC8548v1 >> 16: 1173 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1174 0, 1, 2, 3); 1175 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1176 11, 1, 2, 3); 1177 break; 1178 #endif 1179 } 1180 } 1181
Indexes created Sun Sep 28 16:09:52 GMT 2025