mpc85xx_start.S revision 1.2.4.3
1 1.2.4.2 rmind /* $NetBSD: mpc85xx_start.S,v 1.2.4.3 2011/06/12 00:23:57 rmind Exp $ */ 2 1.2.4.2 rmind /*- 3 1.2.4.2 rmind * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 1.2.4.2 rmind * All rights reserved. 5 1.2.4.2 rmind * 6 1.2.4.2 rmind * This code is derived from software contributed to The NetBSD Foundation 7 1.2.4.2 rmind * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 1.2.4.2 rmind * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 1.2.4.2 rmind * 10 1.2.4.2 rmind * This material is based upon work supported by the Defense Advanced Research 11 1.2.4.2 rmind * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 1.2.4.2 rmind * Contract No. N66001-09-C-2073. 13 1.2.4.2 rmind * Approved for Public Release, Distribution Unlimited 14 1.2.4.2 rmind * 15 1.2.4.2 rmind * Redistribution and use in source and binary forms, with or without 16 1.2.4.2 rmind * modification, are permitted provided that the following conditions 17 1.2.4.2 rmind * are met: 18 1.2.4.2 rmind * 1. Redistributions of source code must retain the above copyright 19 1.2.4.2 rmind * notice, this list of conditions and the following disclaimer. 20 1.2.4.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 21 1.2.4.2 rmind * notice, this list of conditions and the following disclaimer in the 22 1.2.4.2 rmind * documentation and/or other materials provided with the distribution. 23 1.2.4.2 rmind * 24 1.2.4.2 rmind * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 1.2.4.2 rmind * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 1.2.4.2 rmind * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 1.2.4.2 rmind * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 1.2.4.2 rmind * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 1.2.4.2 rmind * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 1.2.4.2 rmind * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 1.2.4.2 rmind * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 1.2.4.2 rmind * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 1.2.4.2 rmind * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 1.2.4.2 rmind * POSSIBILITY OF SUCH DAMAGE. 35 1.2.4.2 rmind */ 36 1.2.4.2 rmind 37 1.2.4.2 rmind #include <sys/cdefs.h> 38 1.2.4.2 rmind #include <powerpc/asm.h> 39 1.2.4.2 rmind 40 1.2.4.2 rmind RCSID("$NetBSD: mpc85xx_start.S,v 1.2.4.3 2011/06/12 00:23:57 rmind Exp $") 41 1.2.4.2 rmind 42 1.2.4.2 rmind #include "opt_altivec.h" 43 1.2.4.2 rmind #include "opt_ddb.h" 44 1.2.4.2 rmind #include "opt_ipkdb.h" 45 1.2.4.2 rmind #include "opt_lockdebug.h" 46 1.2.4.2 rmind #include "opt_modular.h" 47 1.2.4.2 rmind #include "opt_multiprocessor.h" 48 1.2.4.2 rmind #include "opt_ppcarch.h" 49 1.2.4.2 rmind #include "opt_ppcparam.h" 50 1.2.4.2 rmind 51 1.2.4.2 rmind #include "ksyms.h" 52 1.2.4.2 rmind 53 1.2.4.2 rmind #include <sys/param.h> 54 1.2.4.2 rmind 55 1.2.4.2 rmind #include <powerpc/spr.h> 56 1.2.4.2 rmind #include <powerpc/trap.h> 57 1.2.4.2 rmind #include <powerpc/booke/pte.h> 58 1.2.4.2 rmind #include <powerpc/booke/spr.h> 59 1.2.4.2 rmind #define LBC_PRIVATE 60 1.2.4.2 rmind #include <powerpc/booke/e500reg.h> 61 1.2.4.2 rmind 62 1.2.4.2 rmind #include "assym.h" 63 1.2.4.2 rmind 64 1.2.4.2 rmind #define INTSTK 0 65 1.2.4.2 rmind 66 1.2.4.2 rmind .machine e500 67 1.2.4.2 rmind /* 68 1.2.4.2 rmind * This symbol is here for the benefit of kvm_mkdb, and is supposed to 69 1.2.4.2 rmind * mark the start of kernel text. 70 1.2.4.2 rmind */ 71 1.2.4.2 rmind .text 72 1.2.4.2 rmind .globl _C_LABEL(kernel_text) 73 1.2.4.2 rmind _C_LABEL(kernel_text): 74 1.2.4.2 rmind .globl __start 75 1.2.4.2 rmind __start: 76 1.2.4.2 rmind 77 1.2.4.2 rmind /* 78 1.2.4.2 rmind * Startup entry. Note, this must be the first thing in the text segment! 79 1.2.4.2 rmind */ 80 1.2.4.2 rmind mr %r8,%r6 81 1.2.4.2 rmind mr %r7,%r5 82 1.2.4.2 rmind mr %r6,%r4 83 1.2.4.2 rmind mr %r5,%r3 84 1.2.4.2 rmind #ifdef DEBUG 85 1.2.4.2 rmind /* 86 1.2.4.2 rmind * Set all the registers we don't care about to a known junk value. 87 1.2.4.2 rmind */ 88 1.2.4.2 rmind lis %r2,0xdeadbeef@ha 89 1.2.4.2 rmind addi %r2,%r2,0xdeadbeef@l 90 1.2.4.2 rmind mr %r9,%r2 91 1.2.4.2 rmind mr %r10,%r9 92 1.2.4.2 rmind mr %r11,%r9 93 1.2.4.2 rmind mr %r12,%r9 94 1.2.4.2 rmind mr %r13,%r9 95 1.2.4.2 rmind mr %r14,%r9 96 1.2.4.2 rmind mr %r15,%r9 97 1.2.4.2 rmind mr %r16,%r9 98 1.2.4.2 rmind mr %r17,%r9 99 1.2.4.2 rmind mr %r18,%r9 100 1.2.4.2 rmind mr %r19,%r9 101 1.2.4.2 rmind mr %r20,%r9 102 1.2.4.2 rmind mr %r21,%r9 103 1.2.4.2 rmind mr %r22,%r9 104 1.2.4.2 rmind mr %r23,%r9 105 1.2.4.2 rmind mr %r24,%r9 106 1.2.4.2 rmind mr %r25,%r9 107 1.2.4.2 rmind mr %r26,%r9 108 1.2.4.2 rmind mr %r27,%r9 109 1.2.4.2 rmind mr %r28,%r9 110 1.2.4.2 rmind mr %r29,%r9 111 1.2.4.2 rmind mr %r30,%r9 112 1.2.4.2 rmind mr %r31,%r9 113 1.2.4.2 rmind #endif /* DEBUG */ 114 1.2.4.2 rmind 115 1.2.4.2 rmind li %r0,0 116 1.2.4.2 rmind mtmsr %r0 /* Disable FPU/MMU/exceptions */ 117 1.2.4.2 rmind isync 118 1.2.4.2 rmind 119 1.2.4.2 rmind /* get start of bss */ 120 1.2.4.2 rmind lis %r15,_C_LABEL(_edata)-4@ha 121 1.2.4.2 rmind addi %r15,%r15,_C_LABEL(_edata)-4@l 122 1.2.4.2 rmind /* get end of kernel memory */ 123 1.2.4.2 rmind lis %r16,_C_LABEL(end)@ha 124 1.2.4.2 rmind addi %r16,%r16,_C_LABEL(end)@l 125 1.2.4.2 rmind /* zero bss */ 126 1.2.4.2 rmind sub %r17,%r16,%r15 127 1.2.4.2 rmind addi %r17,%r17,3+USPACE 128 1.2.4.3 rmind rlwinm %r3,%r17,32-2,2,31 /* srwl %r3,%r17,2 */ 129 1.2.4.2 rmind mtctr %r3 130 1.2.4.2 rmind li %r0,0 131 1.2.4.2 rmind 2: stwu %r0,4(%r15) 132 1.2.4.2 rmind bdnz 2b 133 1.2.4.2 rmind 134 1.2.4.2 rmind #if NKSYMS || defined(DDB) || defined(MODULAR) 135 1.2.4.2 rmind /* If we had symbol table location we'd store it here and would've adjusted r8 here */ 136 1.2.4.3 rmind lis %r17,_C_LABEL(startsym)@ha 137 1.2.4.3 rmind stw %r18,_C_LABEL(startsym)@l(%r17) 138 1.2.4.3 rmind lis %r17,_C_LABEL(endsym)@ha 139 1.2.4.3 rmind stw %r18,_C_LABEL(endsym)@l(%r17) 140 1.2.4.2 rmind #endif 141 1.2.4.2 rmind 142 1.2.4.2 rmind /* Set kernel MMU context. */ 143 1.2.4.2 rmind li %r0,KERNEL_PID 144 1.2.4.2 rmind mtpid %r0 145 1.2.4.2 rmind isync 146 1.2.4.2 rmind 147 1.2.4.3 rmind INIT_CPUINFO(16,1,18,17) /* r16 has &_end */ 148 1.2.4.3 rmind mr %r4,%r16 /* remember kernelend */ 149 1.2.4.3 rmind mtsprg2 %r13 /* r13 has &lwp0, put into sprg2 */ 150 1.2.4.3 rmind GET_CPUINFO(%r17) 151 1.2.4.3 rmind addi %r17,%r17,CI_SAVELIFO 152 1.2.4.3 rmind mtsprg3 %r17 153 1.2.4.3 rmind mr %r18,%r31 /* make deadbeef again */ 154 1.2.4.3 rmind mr %r17,%r31 /* make deadbeef again */ 155 1.2.4.3 rmind mr %r16,%r31 /* make deadbeef again */ 156 1.2.4.3 rmind mr %r15,%r31 /* make deadbeef again */ 157 1.2.4.2 rmind 158 1.2.4.2 rmind #if defined(GXEMUL) 159 1.2.4.2 rmind /* 160 1.2.4.2 rmind * This is used to step through the external interrupt vector 161 1.2.4.2 rmind * to validate it. 162 1.2.4.2 rmind */ 163 1.2.4.2 rmind lis %r29,3f@ha 164 1.2.4.2 rmind addi %r29,%r29,3f@l 165 1.2.4.2 rmind mtsrr0 %r29 166 1.2.4.2 rmind mfmsr %r0 167 1.2.4.2 rmind mtsrr1 %r0 168 1.2.4.2 rmind lis %r31,0xdeadf231@ha 169 1.2.4.2 rmind addi %r31,%r31,0xdeadf231@l 170 1.2.4.2 rmind mtlr %r31 171 1.2.4.2 rmind addi %r31,%r31,-0x10 172 1.2.4.2 rmind mtcr %r31 173 1.2.4.2 rmind addi %r31,%r31,-0x10 174 1.2.4.2 rmind mtctr %r31 175 1.2.4.2 rmind addi %r31,%r31,-0x10 176 1.2.4.2 rmind mtxer %r31 177 1.2.4.2 rmind addi %r31,%r31,-0x10 178 1.2.4.2 rmind addi %r30,%r31,-0x10 179 1.2.4.2 rmind addi %r29,%r30,-0x10 180 1.2.4.2 rmind addi %r28,%r29,-0x10 181 1.2.4.2 rmind addi %r27,%r28,-0x10 182 1.2.4.2 rmind addi %r26,%r27,-0x10 183 1.2.4.2 rmind addi %r25,%r26,-0x10 184 1.2.4.2 rmind addi %r24,%r25,-0x10 185 1.2.4.2 rmind addi %r23,%r24,-0x10 186 1.2.4.2 rmind addi %r22,%r23,-0x10 187 1.2.4.2 rmind addi %r21,%r22,-0x10 188 1.2.4.2 rmind addi %r20,%r21,-0x10 189 1.2.4.2 rmind addi %r19,%r20,-0x10 190 1.2.4.2 rmind addi %r18,%r19,-0x10 191 1.2.4.2 rmind addi %r17,%r18,-0x10 192 1.2.4.2 rmind addi %r16,%r17,-0x10 193 1.2.4.2 rmind addi %r15,%r16,-0x10 194 1.2.4.2 rmind addi %r14,%r15,-0x10 195 1.2.4.2 rmind addi %r13,%r14,-0x10 196 1.2.4.2 rmind addi %r12,%r13,-0x10 197 1.2.4.2 rmind addi %r11,%r12,-0x10 198 1.2.4.2 rmind addi %r10,%r11,-0x10 199 1.2.4.2 rmind addi %r9,%r10,-0x10 200 1.2.4.2 rmind addi %r8,%r9,-0x10 201 1.2.4.2 rmind addi %r7,%r8,-0x10 202 1.2.4.2 rmind addi %r6,%r7,-0x10 203 1.2.4.2 rmind addi %r5,%r6,-0x10 204 1.2.4.2 rmind addi %r4,%r5,-0x10 205 1.2.4.2 rmind addi %r3,%r4,-0x10 206 1.2.4.2 rmind addi %r2,%r3,-0x10 207 1.2.4.2 rmind /* leave r1 alone */ 208 1.2.4.2 rmind addi %r0,%r2,-0x20 209 1.2.4.2 rmind b _C_LABEL(instruction_tlb_error_vector) 210 1.2.4.2 rmind //b _C_LABEL(program_vector) 211 1.2.4.2 rmind //b _C_LABEL(external_input_vector) 212 1.2.4.2 rmind 3: 213 1.2.4.2 rmind #endif 214 1.2.4.2 rmind 215 1.2.4.2 rmind /* 216 1.2.4.2 rmind * TB is 50Mhz, watchdog should be ~10 seconds which makes that 217 1.2.4.2 rmind * 500 million or 0x20000000. Since it takes 3 bit transitions 218 1.2.4.2 rmind * we really want 0x10000000. That's bit 63-28 or 35. This 219 1.2.4.2 rmind * means we want WPEXT,WP to be 0b10_0011. 220 1.2.4.2 rmind */ 221 1.2.4.2 rmind lis %r3,(TCR_WRC_RESET|TCR_WP_2_N(0x23))@ha 222 1.2.4.2 rmind addi %r3,%r3,(TCR_WRC_RESET|TCR_WP_2_N(0x23))@l 223 1.2.4.2 rmind mtspr SPR_TCR, %r3 224 1.2.4.2 rmind li %r0, 0 225 1.2.4.2 rmind mtspr SPR_TBL, %r0 226 1.2.4.2 rmind mtspr SPR_TBU, %r0 227 1.2.4.2 rmind mtspr SPR_DBCR0, %r0 228 1.2.4.2 rmind 229 1.2.4.2 rmind #if 0 230 1.2.4.2 rmind /* 231 1.2.4.2 rmind * Force all dirty lines in the kernel area to memory. 232 1.2.4.2 rmind */ 233 1.2.4.2 rmind lis %r8,kernel_text@ha 234 1.2.4.2 rmind addi %r8,%r8,kernel_text@l 235 1.2.4.2 rmind 4: dcbst %r0,%r8 236 1.2.4.2 rmind addi %r8,%r8,32 237 1.2.4.2 rmind cmplw %r8,%r4 238 1.2.4.2 rmind blt %cr0,4b 239 1.2.4.2 rmind mbar 1 240 1.2.4.2 rmind msync 241 1.2.4.2 rmind 242 1.2.4.2 rmind /* 243 1.2.4.2 rmind * Turn off the data cache, and then invalidate it. 244 1.2.4.2 rmind */ 245 1.2.4.2 rmind li %r3, 0 246 1.2.4.2 rmind mtspr SPR_L1CSR0, %r3 247 1.2.4.2 rmind li %r3, L1CSR_CFI 248 1.2.4.2 rmind mtspr SPR_L1CSR0, %r3 249 1.2.4.2 rmind #endif 250 1.2.4.2 rmind 251 1.2.4.2 rmind #if 1 252 1.2.4.2 rmind /* 253 1.2.4.2 rmind * Clear any locks from the data or instruction caches. 254 1.2.4.2 rmind */ 255 1.2.4.2 rmind mfspr %r3, SPR_L1CSR0 256 1.2.4.2 rmind ori %r3, %r3, L1CSR_CLFR 257 1.2.4.2 rmind mtspr SPR_L1CSR0, %r3 258 1.2.4.2 rmind mfspr %r3, SPR_L1CSR1 259 1.2.4.2 rmind ori %r3, %r3, L1CSR_CLFR 260 1.2.4.2 rmind mtspr SPR_L1CSR1, %r3 261 1.2.4.2 rmind #endif 262 1.2.4.2 rmind 263 1.2.4.2 rmind lis %r3,__start@ha 264 1.2.4.2 rmind addi %r3,%r3,__start@l 265 1.2.4.2 rmind 266 1.2.4.2 rmind bl _C_LABEL(initppc) 267 1.2.4.2 rmind bl _C_LABEL(main) 268 1.2.4.2 rmind 269 1.2.4.2 rmind loop: b loop /* XXX not reached */ 270 1.2.4.2 rmind 271 1.2.4.2 rmind #include <powerpc/booke/trap_subr.S> 272 1.2.4.2 rmind #include <powerpc/powerpc/locore_subr.S> 273 1.2.4.2 rmind #include <powerpc/powerpc/pio_subr.S> 274 1.2.4.2 rmind #ifdef PPC_HAVE_SPE 275 1.2.4.2 rmind #include <powerpc/booke/spe_subr.S> 276 1.2.4.2 rmind #endif 277 1.2.4.3 rmind #if defined(MULTIPROCESSOR) 278 1.2.4.3 rmind #include <powerpc/booke/e500_mpsubr.S> 279 1.2.4.3 rmind #endif 280 1.2.4.2 rmind 281 1.2.4.2 rmind #if 0 282 1.2.4.2 rmind .p2align 5 283 1.2.4.2 rmind ENTRY(tlbwe) 284 1.2.4.2 rmind isync 285 1.2.4.2 rmind tlbwe 286 1.2.4.2 rmind isync 287 1.2.4.2 rmind blr 288 1.2.4.2 rmind #endif 289
Indexes created Mon Oct 20 11:09:49 GMT 2025