mpc85xx_start.S revision 1.5.2.1
1 /* $NetBSD: mpc85xx_start.S,v 1.5.2.1 2012/10/30 17:19:31 yamt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 #include <powerpc/asm.h> 39 40 RCSID("$NetBSD: mpc85xx_start.S,v 1.5.2.1 2012/10/30 17:19:31 yamt Exp $") 41 42 #include "opt_altivec.h" 43 #include "opt_ddb.h" 44 #include "opt_ipkdb.h" 45 #include "opt_lockdebug.h" 46 #include "opt_modular.h" 47 #include "opt_multiprocessor.h" 48 #include "opt_ppcarch.h" 49 #include "opt_ppcparam.h" 50 51 #include "ksyms.h" 52 53 #include <sys/param.h> 54 55 #include <powerpc/spr.h> 56 #include <powerpc/trap.h> 57 #include <powerpc/psl.h> 58 #include <powerpc/booke/pte.h> 59 #include <powerpc/booke/spr.h> 60 #define LBC_PRIVATE 61 #include <powerpc/booke/e500reg.h> 62 63 #include "assym.h" 64 65 #define INTSTK 0 66 67 .machine e500 68 /* 69 * This symbol is here for the benefit of kvm_mkdb, and is supposed to 70 * mark the start of kernel text. 71 */ 72 .text 73 .globl _C_LABEL(kernel_text) 74 _C_LABEL(kernel_text): 75 .globl __start 76 __start: 77 78 /* 79 * Startup entry. Note, this must be the first thing in the text segment! 80 */ 81 mr %r8,%r6 /* cmdline (char *) */ 82 mr %r7,%r5 /* consdev (char *) */ 83 mr %r6,%r4 /* os_hdr * */ 84 mr %r5,%r3 /* board info * */ 85 #ifdef DEBUG 86 /* 87 * Set all the registers we don't care about to a known junk value. 88 */ 89 lis %r2,0xdeadbeef@ha 90 addi %r2,%r2,0xdeadbeef@l 91 mr %r9,%r2 92 mr %r10,%r9 93 mr %r11,%r9 94 mr %r12,%r9 95 mr %r13,%r9 96 mr %r14,%r9 97 mr %r15,%r9 98 mr %r16,%r9 99 mr %r17,%r9 100 mr %r18,%r9 101 mr %r19,%r9 102 mr %r20,%r9 103 mr %r21,%r9 104 mr %r22,%r9 105 mr %r23,%r9 106 mr %r24,%r9 107 mr %r25,%r9 108 mr %r26,%r9 109 mr %r27,%r9 110 mr %r28,%r9 111 mr %r29,%r9 112 mr %r30,%r9 113 mr %r31,%r9 114 #endif /* DEBUG */ 115 116 li %r0,0 117 mtmsr %r0 /* Disable FPU/MMU/exceptions */ 118 isync 119 120 /* get start of bss */ 121 lis %r15,_C_LABEL(_edata)-4@ha 122 addi %r15,%r15,_C_LABEL(_edata)-4@l 123 /* get end of kernel memory */ 124 lis %r16,_C_LABEL(end)@ha 125 addi %r16,%r16,_C_LABEL(end)@l 126 /* zero bss */ 127 sub %r17,%r16,%r15 128 addi %r17,%r17,3+USPACE 129 rlwinm %r3,%r17,32-2,2,31 /* srwl %r3,%r17,2 */ 130 mtctr %r3 131 li %r0,0 132 2: stwu %r0,4(%r15) 133 bdnz 2b 134 135 #if NKSYMS || defined(DDB) || defined(MODULAR) 136 /* If we had symbol table location we'd store it here and would've adjusted r8 here */ 137 lis %r17,_C_LABEL(startsym)@ha 138 stw %r18,_C_LABEL(startsym)@l(%r17) 139 lis %r17,_C_LABEL(endsym)@ha 140 stw %r18,_C_LABEL(endsym)@l(%r17) 141 #endif 142 143 /* Set kernel MMU context. */ 144 li %r0,KERNEL_PID 145 mtpid %r0 146 isync 147 148 INIT_CPUINFO(16,1,18,17) /* r16 has &_end */ 149 mr %r4,%r16 /* remember kernelend */ 150 mtsprg2 %r13 /* r13 has &lwp0, put into sprg2 */ 151 GET_CPUINFO(%r17) 152 addi %r17,%r17,CI_SAVELIFO 153 mtsprg3 %r17 154 mr %r18,%r31 /* make deadbeef again */ 155 mr %r17,%r31 /* make deadbeef again */ 156 mr %r16,%r31 /* make deadbeef again */ 157 mr %r15,%r31 /* make deadbeef again */ 158 159 #if defined(GXEMUL) 160 /* 161 * This is used to step through the external interrupt vector 162 * to validate it. 163 */ 164 lis %r29,3f@ha 165 addi %r29,%r29,3f@l 166 mtsrr0 %r29 167 mfmsr %r0 168 mtsrr1 %r0 169 lis %r31,0xdeadf231@ha 170 addi %r31,%r31,0xdeadf231@l 171 mtlr %r31 172 addi %r31,%r31,-0x10 173 mtcr %r31 174 addi %r31,%r31,-0x10 175 mtctr %r31 176 addi %r31,%r31,-0x10 177 mtxer %r31 178 addi %r31,%r31,-0x10 179 addi %r30,%r31,-0x10 180 addi %r29,%r30,-0x10 181 addi %r28,%r29,-0x10 182 addi %r27,%r28,-0x10 183 addi %r26,%r27,-0x10 184 addi %r25,%r26,-0x10 185 addi %r24,%r25,-0x10 186 addi %r23,%r24,-0x10 187 addi %r22,%r23,-0x10 188 addi %r21,%r22,-0x10 189 addi %r20,%r21,-0x10 190 addi %r19,%r20,-0x10 191 addi %r18,%r19,-0x10 192 addi %r17,%r18,-0x10 193 addi %r16,%r17,-0x10 194 addi %r15,%r16,-0x10 195 addi %r14,%r15,-0x10 196 addi %r13,%r14,-0x10 197 addi %r12,%r13,-0x10 198 addi %r11,%r12,-0x10 199 addi %r10,%r11,-0x10 200 addi %r9,%r10,-0x10 201 addi %r8,%r9,-0x10 202 addi %r7,%r8,-0x10 203 addi %r6,%r7,-0x10 204 addi %r5,%r6,-0x10 205 addi %r4,%r5,-0x10 206 addi %r3,%r4,-0x10 207 addi %r2,%r3,-0x10 208 /* leave r1 alone */ 209 addi %r0,%r2,-0x20 210 b _C_LABEL(instruction_tlb_error_vector) 211 //b _C_LABEL(program_vector) 212 //b _C_LABEL(external_input_vector) 213 3: 214 #endif 215 216 /* 217 * TB is 50Mhz, watchdog should be ~10 seconds which makes that 218 * 500 million or 0x20000000. Since it takes 3 bit transitions 219 * we really want 0x10000000. That's bit 63-28 or 35. This 220 * means we want WPEXT,WP to be 0b10_0011. 221 */ 222 lis %r3,(TCR_WRC_RESET|TCR_WP_2_N(0x23))@ha 223 addi %r3,%r3,(TCR_WRC_RESET|TCR_WP_2_N(0x23))@l 224 mtspr SPR_TCR, %r3 225 li %r0, 0 226 mtspr SPR_TBL, %r0 227 mtspr SPR_TBU, %r0 228 mtspr SPR_DBCR0, %r0 229 230 #if 0 231 /* 232 * Force all dirty lines in the kernel area to memory. 233 */ 234 lis %r9,kernel_text@ha 235 addi %r9,%r9,kernel_text@l 236 4: dcbst %r0,%r9 237 addi %r9,%r9,32 238 cmplw %r9,%r4 239 blt %cr0,4b 240 mbar 1 241 msync 242 243 /* 244 * Turn off the data cache, and then invalidate it. 245 */ 246 li %r3, 0 247 mtspr SPR_L1CSR0, %r3 248 li %r3, L1CSR_CFI 249 mtspr SPR_L1CSR0, %r3 250 #endif 251 252 #if 1 253 /* 254 * Clear any locks from the data or instruction caches. 255 */ 256 mfspr %r3, SPR_L1CSR0 257 ori %r3, %r3, L1CSR_CLFR 258 mtspr SPR_L1CSR0, %r3 259 mfspr %r3, SPR_L1CSR1 260 ori %r3, %r3, L1CSR_CLFR 261 mtspr SPR_L1CSR1, %r3 262 #endif 263 264 lis %r3,__start@ha 265 addi %r3,%r3,__start@l 266 267 bl _C_LABEL(initppc) 268 bl _C_LABEL(main) 269 270 loop: b loop /* XXX not reached */ 271 272 #include <powerpc/booke/trap_subr.S> 273 #include <powerpc/powerpc/locore_subr.S> 274 #include <powerpc/powerpc/pio_subr.S> 275 #ifdef PPC_HAVE_SPE 276 #include <powerpc/booke/spe_subr.S> 277 #endif 278 #if defined(MULTIPROCESSOR) 279 #include <powerpc/booke/e500_mpsubr.S> 280 #endif 281 282 #if 0 283 .p2align 5 284 ENTRY(tlbwe) 285 isync 286 tlbwe 287 isync 288 blr 289 #endif 290
Indexes created Wed Oct 15 14:09:57 GMT 2025