mpc85xx_start.S revision 1.9.26.1
1 /* $NetBSD: mpc85xx_start.S,v 1.9.26.1 2018/07/28 04:37:33 pgoyette Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 #include <powerpc/asm.h> 39 40 RCSID("$NetBSD: mpc85xx_start.S,v 1.9.26.1 2018/07/28 04:37:33 pgoyette Exp $") 41 42 #include "opt_altivec.h" 43 #include "opt_ddb.h" 44 #include "opt_lockdebug.h" 45 #include "opt_modular.h" 46 #include "opt_multiprocessor.h" 47 #include "opt_ppcarch.h" 48 #include "opt_ppcparam.h" 49 50 #include "ksyms.h" 51 52 #include <sys/param.h> 53 54 #include <powerpc/spr.h> 55 #include <powerpc/trap.h> 56 #include <powerpc/psl.h> 57 #include <powerpc/booke/pte.h> 58 #include <powerpc/booke/spr.h> 59 #define LBC_PRIVATE 60 #include <powerpc/booke/e500reg.h> 61 62 #include "assym.h" 63 64 #define INTSTK 0 65 66 /* 67 * This symbol is here for the benefit of kvm_mkdb, and is supposed to 68 * mark the start of kernel text. 69 */ 70 .text 71 .globl _C_LABEL(kernel_text) 72 _C_LABEL(kernel_text): 73 .globl __start 74 __start: 75 76 /* 77 * Startup entry. Note, this must be the first thing in the text segment! 78 */ 79 mr %r8,%r6 /* cmdline (char *) */ 80 mr %r7,%r5 /* consdev (char *) */ 81 mr %r6,%r4 /* os_hdr * */ 82 mr %r5,%r3 /* board info * */ 83 #ifdef DEBUG 84 /* 85 * Set all the registers we don't care about to a known junk value. 86 */ 87 lis %r2,0xdeadbeef@h 88 ori %r2,%r2,0xdeadbeef@l 89 mr %r9,%r2 90 mr %r10,%r9 91 mr %r11,%r9 92 mr %r12,%r9 93 mr %r13,%r9 94 mr %r14,%r9 95 mr %r15,%r9 96 mr %r16,%r9 97 mr %r17,%r9 98 mr %r18,%r9 99 mr %r19,%r9 100 mr %r20,%r9 101 mr %r21,%r9 102 mr %r22,%r9 103 mr %r23,%r9 104 mr %r24,%r9 105 mr %r25,%r9 106 mr %r26,%r9 107 mr %r27,%r9 108 mr %r28,%r9 109 mr %r29,%r9 110 mr %r30,%r9 111 mr %r31,%r9 112 #endif /* DEBUG */ 113 114 li %r0,0 115 mtmsr %r0 /* Disable FPU/MMU/exceptions */ 116 isync 117 118 /* get start of bss */ 119 lis %r15,_C_LABEL(_edata)-4@ha 120 addi %r15,%r15,_C_LABEL(_edata)-4@l 121 /* get end of kernel memory */ 122 lis %r16,_C_LABEL(end)@ha 123 addi %r16,%r16,_C_LABEL(end)@l 124 /* zero bss */ 125 sub %r17,%r16,%r15 126 addi %r17,%r17,3+USPACE 127 rlwinm %r3,%r17,32-2,2,31 /* srwl %r3,%r17,2 */ 128 mtctr %r3 129 li %r0,0 130 2: stwu %r0,4(%r15) 131 bdnz 2b 132 133 #if NKSYMS || defined(DDB) || defined(MODULAR) 134 /* If we had symbol table location we'd store it here and would've adjusted r8 here */ 135 lis %r17,_C_LABEL(startsym)@ha 136 stw %r18,_C_LABEL(startsym)@l(%r17) 137 lis %r17,_C_LABEL(endsym)@ha 138 stw %r18,_C_LABEL(endsym)@l(%r17) 139 #endif 140 141 /* Set kernel MMU context. */ 142 li %r0,KERNEL_PID 143 mtpid %r0 144 isync 145 146 INIT_CPUINFO(16,1,18,17) /* r16 has &_end */ 147 mr %r4,%r16 /* remember kernelend */ 148 mtsprg2 %r13 /* r13 has &lwp0, put into sprg2 */ 149 GET_CPUINFO(%r17) 150 addi %r17,%r17,CI_SAVELIFO 151 mtsprg3 %r17 152 mr %r18,%r31 /* make deadbeef again */ 153 mr %r17,%r31 /* make deadbeef again */ 154 mr %r16,%r31 /* make deadbeef again */ 155 mr %r15,%r31 /* make deadbeef again */ 156 157 #if defined(GXEMUL) 158 /* 159 * This is used to step through the external interrupt vector 160 * to validate it. 161 */ 162 lis %r29,3f@ha 163 addi %r29,%r29,3f@l 164 mtsrr0 %r29 165 mfmsr %r0 166 mtsrr1 %r0 167 lis %r31,0xdeadf231@ha 168 addi %r31,%r31,0xdeadf231@l 169 mtlr %r31 170 addi %r31,%r31,-0x10 171 mtcr %r31 172 addi %r31,%r31,-0x10 173 mtctr %r31 174 addi %r31,%r31,-0x10 175 mtxer %r31 176 addi %r31,%r31,-0x10 177 addi %r30,%r31,-0x10 178 addi %r29,%r30,-0x10 179 addi %r28,%r29,-0x10 180 addi %r27,%r28,-0x10 181 addi %r26,%r27,-0x10 182 addi %r25,%r26,-0x10 183 addi %r24,%r25,-0x10 184 addi %r23,%r24,-0x10 185 addi %r22,%r23,-0x10 186 addi %r21,%r22,-0x10 187 addi %r20,%r21,-0x10 188 addi %r19,%r20,-0x10 189 addi %r18,%r19,-0x10 190 addi %r17,%r18,-0x10 191 addi %r16,%r17,-0x10 192 addi %r15,%r16,-0x10 193 addi %r14,%r15,-0x10 194 addi %r13,%r14,-0x10 195 addi %r12,%r13,-0x10 196 addi %r11,%r12,-0x10 197 addi %r10,%r11,-0x10 198 addi %r9,%r10,-0x10 199 addi %r8,%r9,-0x10 200 addi %r7,%r8,-0x10 201 addi %r6,%r7,-0x10 202 addi %r5,%r6,-0x10 203 addi %r4,%r5,-0x10 204 addi %r3,%r4,-0x10 205 addi %r2,%r3,-0x10 206 /* leave r1 alone */ 207 addi %r0,%r2,-0x20 208 b _C_LABEL(instruction_tlb_error_vector) 209 //b _C_LABEL(program_vector) 210 //b _C_LABEL(external_input_vector) 211 3: 212 #endif 213 214 /* 215 * TB is 50Mhz, watchdog should be ~10 seconds which makes that 216 * 500 million or 0x20000000. Since it takes 3 bit transitions 217 * we really want 0x10000000. That's bit 63-28 or 35. This 218 * means we want WPEXT,WP to be 0b10_0011. 219 */ 220 lis %r3,(TCR_WRC_RESET|TCR_WP_2_N(0x23))@ha 221 addi %r3,%r3,(TCR_WRC_RESET|TCR_WP_2_N(0x23))@l 222 mtspr SPR_TCR, %r3 223 li %r0, 0 224 mtspr SPR_TBL, %r0 225 mtspr SPR_TBU, %r0 226 mtspr SPR_DBCR0, %r0 227 228 #if 0 229 /* 230 * Force all dirty lines in the kernel area to memory. 231 */ 232 lis %r9,kernel_text@ha 233 addi %r9,%r9,kernel_text@l 234 4: dcbst %r0,%r9 235 addi %r9,%r9,32 236 cmplw %r9,%r4 237 blt %cr0,4b 238 mbar 1 239 msync 240 241 /* 242 * Turn off the data cache, and then invalidate it. 243 */ 244 li %r3, 0 245 mtspr SPR_L1CSR0, %r3 246 li %r3, L1CSR_CFI 247 mtspr SPR_L1CSR0, %r3 248 #endif 249 250 #if 1 251 /* 252 * Clear any locks from the data or instruction caches. 253 */ 254 mfspr %r3, SPR_L1CSR0 255 ori %r3, %r3, L1CSR_CLFR 256 mtspr SPR_L1CSR0, %r3 257 mfspr %r3, SPR_L1CSR1 258 ori %r3, %r3, L1CSR_CLFR 259 mtspr SPR_L1CSR1, %r3 260 #endif 261 262 lis %r3,__start@ha 263 addi %r3,%r3,__start@l 264 265 bl _C_LABEL(initppc) 266 bl _C_LABEL(main) 267 268 loop: b loop /* XXX not reached */ 269 270 #include <powerpc/booke/trap_subr.S> 271 #include <powerpc/powerpc/locore_subr.S> 272 #include <powerpc/powerpc/pio_subr.S> 273 #ifdef PPC_HAVE_SPE 274 #include <powerpc/booke/spe_subr.S> 275 #endif 276 #if defined(MULTIPROCESSOR) 277 #include <powerpc/booke/e500_mpsubr.S> 278 #endif 279 280 #if 0 281 .p2align 5 282 ENTRY(tlbwe) 283 isync 284 tlbwe 285 isync 286 blr 287 #endif 288
Indexes created Wed Oct 15 16:09:53 GMT 2025