obs266_machdep.c revision 1.24 1 1.24 rin /* $NetBSD: obs266_machdep.c,v 1.24 2021/03/30 01:47:44 rin Exp $ */
2 1.1 shige /* Original: md_machdep.c,v 1.3 2005/01/24 18:47:37 shige Exp $ */
3 1.1 shige
4 1.1 shige /*
5 1.1 shige * Copyright 2001, 2002 Wasabi Systems, Inc.
6 1.1 shige * All rights reserved.
7 1.1 shige *
8 1.1 shige * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
9 1.1 shige *
10 1.1 shige * Redistribution and use in source and binary forms, with or without
11 1.1 shige * modification, are permitted provided that the following conditions
12 1.1 shige * are met:
13 1.1 shige * 1. Redistributions of source code must retain the above copyright
14 1.1 shige * notice, this list of conditions and the following disclaimer.
15 1.1 shige * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 shige * notice, this list of conditions and the following disclaimer in the
17 1.1 shige * documentation and/or other materials provided with the distribution.
18 1.1 shige * 3. All advertising materials mentioning features or use of this software
19 1.1 shige * must display the following acknowledgement:
20 1.1 shige * This product includes software developed for the NetBSD Project by
21 1.1 shige * Wasabi Systems, Inc.
22 1.1 shige * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23 1.1 shige * or promote products derived from this software without specific prior
24 1.1 shige * written permission.
25 1.1 shige *
26 1.1 shige * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27 1.1 shige * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 shige * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 shige * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30 1.1 shige * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 shige * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 shige * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 shige * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 shige * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 shige * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 shige * POSSIBILITY OF SUCH DAMAGE.
37 1.1 shige */
38 1.1 shige
39 1.1 shige /*
40 1.1 shige * Copyright (C) 1995, 1996 Wolfgang Solfrank.
41 1.1 shige * Copyright (C) 1995, 1996 TooLs GmbH.
42 1.1 shige * All rights reserved.
43 1.1 shige *
44 1.1 shige * Redistribution and use in source and binary forms, with or without
45 1.1 shige * modification, are permitted provided that the following conditions
46 1.1 shige * are met:
47 1.1 shige * 1. Redistributions of source code must retain the above copyright
48 1.1 shige * notice, this list of conditions and the following disclaimer.
49 1.1 shige * 2. Redistributions in binary form must reproduce the above copyright
50 1.1 shige * notice, this list of conditions and the following disclaimer in the
51 1.1 shige * documentation and/or other materials provided with the distribution.
52 1.1 shige * 3. All advertising materials mentioning features or use of this software
53 1.1 shige * must display the following acknowledgement:
54 1.1 shige * This product includes software developed by TooLs GmbH.
55 1.1 shige * 4. The name of TooLs GmbH may not be used to endorse or promote products
56 1.1 shige * derived from this software without specific prior written permission.
57 1.1 shige *
58 1.1 shige * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
59 1.1 shige * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
60 1.1 shige * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
61 1.1 shige * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
62 1.1 shige * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
63 1.1 shige * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
64 1.1 shige * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
65 1.1 shige * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
66 1.1 shige * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
67 1.1 shige * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
68 1.1 shige */
69 1.1 shige
70 1.1 shige #include <sys/cdefs.h>
71 1.24 rin __KERNEL_RCSID(0, "$NetBSD: obs266_machdep.c,v 1.24 2021/03/30 01:47:44 rin Exp $");
72 1.1 shige
73 1.1 shige #include "opt_compat_netbsd.h"
74 1.1 shige #include "opt_ddb.h"
75 1.1 shige
76 1.1 shige #include <sys/param.h>
77 1.1 shige #include <sys/kernel.h>
78 1.1 shige #include <sys/ksyms.h>
79 1.1 shige #include <sys/mount.h>
80 1.1 shige #include <sys/reboot.h>
81 1.1 shige #include <sys/systm.h>
82 1.7 dyoung #include <sys/device.h>
83 1.16 mrg #include <sys/module.h>
84 1.18 matt #include <sys/bus.h>
85 1.18 matt #include <sys/cpu.h>
86 1.1 shige
87 1.1 shige #include <uvm/uvm_extern.h>
88 1.1 shige
89 1.1 shige #include <machine/obs266.h>
90 1.18 matt
91 1.12 kiyohara #include <powerpc/ibm4xx/dcr4xx.h>
92 1.18 matt #include <powerpc/ibm4xx/cpu.h>
93 1.12 kiyohara #include <powerpc/ibm4xx/ibm405gp.h>
94 1.20 matt #include <powerpc/ibm4xx/pci_machdep.h>
95 1.12 kiyohara #include <powerpc/ibm4xx/openbios.h>
96 1.20 matt #include <powerpc/ibm4xx/dev/comopbvar.h>
97 1.18 matt
98 1.18 matt #include <powerpc/spr.h>
99 1.11 matt #include <powerpc/ibm4xx/spr.h>
100 1.1 shige
101 1.13 kiyohara #include <dev/ic/comreg.h>
102 1.4 shige #include <dev/pci/pcivar.h>
103 1.4 shige #include <dev/pci/pciconf.h>
104 1.4 shige
105 1.1 shige #include "ksyms.h"
106 1.1 shige
107 1.13 kiyohara #include "com.h"
108 1.13 kiyohara #if (NCOM > 0)
109 1.13 kiyohara #include <sys/termios.h>
110 1.13 kiyohara
111 1.13 kiyohara #ifndef CONADDR
112 1.13 kiyohara #define CONADDR IBM405GP_UART0_BASE
113 1.13 kiyohara #endif
114 1.13 kiyohara #ifndef CONSPEED
115 1.13 kiyohara #define CONSPEED B9600
116 1.13 kiyohara #endif
117 1.13 kiyohara #ifndef CONMODE
118 1.13 kiyohara /* 8N1 */
119 1.13 kiyohara #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8)
120 1.13 kiyohara #endif
121 1.13 kiyohara #endif /* NCOM */
122 1.5 kiyohara
123 1.5 kiyohara #define TLB_PG_SIZE (16*1024*1024)
124 1.5 kiyohara
125 1.19 matt void initppc(vaddr_t, vaddr_t, char *, void *);
126 1.1 shige
127 1.1 shige void
128 1.19 matt initppc(vaddr_t startkernel, vaddr_t endkernel, char *args, void *info_block)
129 1.1 shige {
130 1.5 kiyohara vaddr_t va;
131 1.1 shige u_int memsize;
132 1.1 shige
133 1.1 shige /* Setup board from OpenBIOS */
134 1.24 rin openbios_board_init(info_block);
135 1.1 shige memsize = openbios_board_memsize_get();
136 1.1 shige
137 1.6 freza /* Linear map kernel memory */
138 1.6 freza for (va = 0; va < endkernel; va += TLB_PG_SIZE)
139 1.5 kiyohara ppc4xx_tlb_reserve(va, va, TLB_PG_SIZE, TLB_EX);
140 1.5 kiyohara
141 1.6 freza /* Map console after RAM (see pmap_tlbmiss()) */
142 1.13 kiyohara ppc4xx_tlb_reserve(CONADDR, roundup(memsize, TLB_PG_SIZE), TLB_PG_SIZE,
143 1.13 kiyohara TLB_I | TLB_G);
144 1.5 kiyohara
145 1.1 shige /* Initialize IBM405GPr CPU */
146 1.1 shige ibm40x_memsize_init(memsize, startkernel);
147 1.19 matt ibm4xx_init(startkernel, endkernel, pic_ext_intr);
148 1.1 shige
149 1.1 shige #ifdef DEBUG
150 1.1 shige openbios_board_print();
151 1.1 shige #endif
152 1.1 shige
153 1.1 shige #ifdef DDB
154 1.1 shige if (boothowto & RB_KDB)
155 1.1 shige Debugger();
156 1.1 shige #endif
157 1.16 mrg
158 1.16 mrg /*
159 1.16 mrg * Look for the ibm4xx modules in the right place.
160 1.16 mrg */
161 1.16 mrg module_machine = module_machine_ibm4xx;
162 1.1 shige }
163 1.1 shige
164 1.1 shige void
165 1.1 shige consinit(void)
166 1.1 shige {
167 1.1 shige
168 1.13 kiyohara #if (NCOM > 0)
169 1.13 kiyohara com_opb_cnattach(OBS266_COM_FREQ, CONADDR, CONSPEED, CONMODE);
170 1.13 kiyohara #endif
171 1.1 shige }
172 1.1 shige
173 1.1 shige /*
174 1.1 shige * Machine dependent startup code.
175 1.1 shige */
176 1.1 shige void
177 1.1 shige cpu_startup(void)
178 1.1 shige {
179 1.1 shige
180 1.1 shige /*
181 1.1 shige * cpu common startup
182 1.1 shige */
183 1.1 shige ibm4xx_cpu_startup("OpenBlockS266 IBM PowerPC 405GPr Board");
184 1.1 shige
185 1.1 shige /*
186 1.1 shige * Set up the board properties database.
187 1.1 shige */
188 1.1 shige openbios_board_info_set();
189 1.1 shige
190 1.1 shige /*
191 1.1 shige * Now that we have VM, malloc()s are OK in bus_space.
192 1.1 shige */
193 1.1 shige bus_space_mallocok();
194 1.1 shige
195 1.1 shige /*
196 1.1 shige * no fake mapiodev
197 1.1 shige */
198 1.1 shige fake_mapiodev = 0;
199 1.1 shige }
200 1.1 shige
201 1.4 shige int
202 1.20 matt ibm4xx_pci_bus_maxdevs(void *v, int busno)
203 1.12 kiyohara {
204 1.12 kiyohara
205 1.12 kiyohara /*
206 1.12 kiyohara * Bus number is irrelevant. Configuration Mechanism 1 is in
207 1.12 kiyohara * use, can have devices 0-32 (i.e. the `normal' range).
208 1.12 kiyohara */
209 1.12 kiyohara return 31;
210 1.12 kiyohara }
211 1.12 kiyohara
212 1.12 kiyohara int
213 1.20 matt ibm4xx_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
214 1.4 shige {
215 1.4 shige /*
216 1.4 shige * We need to map the interrupt pin to the interrupt bit
217 1.4 shige * in the UIC associated with it.
218 1.4 shige *
219 1.4 shige * This platform has 4 PCI devices.
220 1.4 shige *
221 1.4 shige # External IRQ Mappings:
222 1.4 shige * dev 1 (Ext IRQ3): PCI Connector
223 1.4 shige * dev 2 (Ext IRQ4): PCI Connector
224 1.4 shige * dev 3 (Ext IRQ5): HPT IDE Controller
225 1.4 shige * dev 4 (Ext IRQ6): Davicom Ethernet
226 1.4 shige */
227 1.4 shige static const int irqmap[4/*device*/][4/*pin*/] = {
228 1.4 shige { 3, 3, 3, 3 }, /* 1: PCI Connector 1 */
229 1.4 shige { 4, 4, 4, 4 }, /* 2: PCI Connector 2 */
230 1.4 shige { 5, 5, -1, -1 }, /* 3: HPT IDE Controller */
231 1.4 shige { 6, 6, -1, -1 }, /* 4: Damicom Ethernet */
232 1.4 shige };
233 1.4 shige
234 1.4 shige int pin, dev, irq;
235 1.4 shige
236 1.4 shige pin = pa->pa_intrpin;
237 1.4 shige dev = pa->pa_device;
238 1.4 shige *ihp = -1;
239 1.4 shige
240 1.4 shige /* if interrupt pin not used... */
241 1.4 shige if (pin == 0)
242 1.4 shige return 1;
243 1.4 shige
244 1.4 shige if (pin > 4) {
245 1.4 shige printf("pci_intr_map: bad interrupt pin %d\n", pin);
246 1.4 shige return 1;
247 1.4 shige }
248 1.4 shige
249 1.4 shige if ((dev < 1) || (dev > 4)) {
250 1.4 shige printf("pci_intr_map: bad device %d\n", dev);
251 1.4 shige return 1;
252 1.4 shige }
253 1.4 shige
254 1.4 shige
255 1.4 shige if ((irq = irqmap[dev - 1][pin - 1]) == -1) {
256 1.4 shige printf("pci_intr_map: no IRQ routing for device %d pin %d\n",
257 1.4 shige dev, pin);
258 1.4 shige return 1;
259 1.4 shige }
260 1.4 shige
261 1.4 shige *ihp = irq + 25;
262 1.4 shige return 0;
263 1.4 shige }
264 1.4 shige
265 1.4 shige void
266 1.20 matt ibm4xx_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
267 1.20 matt int *iline)
268 1.4 shige {
269 1.4 shige
270 1.4 shige static const int ilinemap[4/*device*/] = {
271 1.20 matt 28, 29, 30, 31
272 1.4 shige };
273 1.4 shige
274 1.4 shige if ((dev < 1) || (dev > 4)) {
275 1.20 matt printf("%s: bad device %d\n", __func__, dev);
276 1.4 shige *iline = 0;
277 1.4 shige return;
278 1.4 shige }
279 1.20 matt *iline = ilinemap[dev - 1];
280 1.4 shige }
281